--! Test divisor module
|
--! Test divisor module
|
library IEEE;
|
library IEEE;
|
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.std_logic_arith.all;
|
use IEEE.std_logic_arith.all;
|
|
|
--! Use Global Definitions package
|
--! Use Global Definitions package
|
use work.pkgDefinitions.all;
|
use work.pkgDefinitions.all;
|
|
|
ENTITY testDivisor IS
|
ENTITY testDivisor IS
|
END testDivisor;
|
END testDivisor;
|
|
|
ARCHITECTURE behavior OF testDivisor IS
|
ARCHITECTURE behavior OF testDivisor IS
|
|
|
-- Component Declaration for the Unit Under Test (UUT)
|
-- Component Declaration for the Unit Under Test (UUT)
|
|
|
COMPONENT divisor
|
COMPONENT divisor
|
PORT(
|
Port ( rst : in STD_LOGIC; --! Reset input
|
rst : IN std_logic;
|
clk : in STD_LOGIC; --! Clock input
|
clk : IN std_logic;
|
quotient : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); --! Division result (32 bits)
|
quotient : OUT std_logic_vector((nBitsLarge-1) downto 0);
|
reminder : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); --! Reminder result (32 bits)
|
reminder : OUT std_logic_vector((nBitsLarge-1) downto 0);
|
numerator : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); --! Numerator (32 bits)
|
numerator : IN std_logic_vector((nBitsLarge-1) downto 0);
|
divident : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); --! "Divide by" number (32 bits)
|
divident : IN std_logic_vector((nBitsLarge-1) downto 0);
|
done : out STD_LOGIC);
|
done : OUT std_logic
|
|
);
|
|
END COMPONENT;
|
END COMPONENT;
|
|
|
|
|
--Inputs
|
--Inputs
|
signal rst : std_logic := '0';
|
signal rst : std_logic := '0'; --! Signal to connect with UUT
|
signal clk : std_logic := '0';
|
signal clk : std_logic := '0'; --! Signal to connect with UUT
|
signal numerator : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0');
|
signal numerator : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0'); --! Signal to connect with UUT
|
signal divident : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0');
|
signal divident : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0'); --! Signal to connect with UUT
|
|
|
--Outputs
|
--Outputs
|
signal quotient : std_logic_vector((nBitsLarge-1) downto 0);
|
signal quotient : std_logic_vector((nBitsLarge-1) downto 0); --! Signal to connect with UUT
|
signal reminder : std_logic_vector((nBitsLarge-1) downto 0);
|
signal reminder : std_logic_vector((nBitsLarge-1) downto 0); --! Signal to connect with UUT
|
signal done : std_logic;
|
signal done : std_logic;
|
|
|
-- Clock period definitions
|
-- Clock period definitions
|
constant clk_period : time := 10 ns;
|
constant clk_period : time := 10 ns;
|
|
|
BEGIN
|
BEGIN
|
|
|
--! Instantiate the Unit Under Test (UUT)
|
--! Instantiate the Unit Under Test (UUT)
|
uut: divisor PORT MAP (
|
uut: divisor PORT MAP (
|
rst => rst,
|
rst => rst,
|
clk => clk,
|
clk => clk,
|
quotient => quotient,
|
quotient => quotient,
|
reminder => reminder,
|
reminder => reminder,
|
numerator => numerator,
|
numerator => numerator,
|
divident => divident,
|
divident => divident,
|
done => done
|
done => done
|
);
|
);
|
|
|
-- Clock process definitions
|
-- Clock process definitions
|
clk_process :process
|
clk_process :process
|
begin
|
begin
|
clk <= '0';
|
clk <= '0';
|
wait for clk_period/2;
|
wait for clk_period/2;
|
clk <= '1';
|
clk <= '1';
|
wait for clk_period/2;
|
wait for clk_period/2;
|
end process;
|
end process;
|
|
|
|
|
-- Stimulus process
|
-- Stimulus process
|
stim_proc: process
|
stim_proc: process
|
begin
|
begin
|
-- hold reset state for 100 ns.
|
-- hold reset state for 100 ns.
|
rst <= '1';
|
rst <= '1';
|
numerator <= conv_std_logic_vector(50000000, 32);
|
numerator <= conv_std_logic_vector(50000000, 32);
|
divident <= conv_std_logic_vector(115200, 32);
|
divident <= conv_std_logic_vector(115200, 32);
|
wait for 20 ns;
|
wait for 20 ns;
|
rst <= '0';
|
rst <= '0';
|
|
|
wait until done = '1';
|
wait until done = '1';
|
wait for clk_period;
|
wait for clk_period;
|
|
|
rst <= '1';
|
rst <= '1';
|
numerator <= conv_std_logic_vector(40, 32);
|
numerator <= conv_std_logic_vector(40, 32);
|
divident <= conv_std_logic_vector(5, 32);
|
divident <= conv_std_logic_vector(5, 32);
|
wait for 20 ns;
|
wait for 20 ns;
|
rst <= '0';
|
rst <= '0';
|
|
|
wait until done = '1';
|
wait until done = '1';
|
wait for clk_period;
|
wait for clk_period;
|
|
|
-- insert stimulus here
|
-- insert stimulus here
|
assert false report "NONE. End of simulation." severity failure;
|
assert false report "NONE. End of simulation." severity failure;
|
|
|
end process;
|
end process;
|
|
|
END;
|
END;
|
|
|
