--! Test divisor module
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--! @file
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--! @brief Test divisor module
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--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_arith.all;
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--! Use Global Definitions package
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--! Use Global Definitions package
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use work.pkgDefinitions.all;
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use work.pkgDefinitions.all;
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ENTITY testDivisor IS
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ENTITY testDivisor IS
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END testDivisor;
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END testDivisor;
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--! @brief Test divisor module
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--! @details Calculate some divisions and verify if we have the right value
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ARCHITECTURE behavior OF testDivisor IS
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ARCHITECTURE behavior OF testDivisor IS
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-- Component Declaration for the Unit Under Test (UUT)
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT divisor
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COMPONENT divisor
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Port ( rst : in STD_LOGIC; --! Reset input
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Port ( rst : in STD_LOGIC; --! Reset input
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clk : in STD_LOGIC; --! Clock input
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clk : in STD_LOGIC; --! Clock input
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quotient : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); --! Division result (32 bits)
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quotient : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); --! Division result (32 bits)
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reminder : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); --! Reminder result (32 bits)
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reminder : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); --! Reminder result (32 bits)
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numerator : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); --! Numerator (32 bits)
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numerator : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); --! Numerator (32 bits)
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divident : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); --! "Divide by" number (32 bits)
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divident : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); --! "Divide by" number (32 bits)
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done : out STD_LOGIC);
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done : out STD_LOGIC);
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END COMPONENT;
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END COMPONENT;
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--Inputs
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--Inputs
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signal rst : std_logic := '0'; --! Signal to connect with UUT
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signal rst : std_logic := '0'; --! Signal to connect with UUT
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signal clk : std_logic := '0'; --! Signal to connect with UUT
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signal clk : std_logic := '0'; --! Signal to connect with UUT
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signal numerator : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0'); --! Signal to connect with UUT
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signal numerator : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0'); --! Signal to connect with UUT
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signal divident : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0'); --! Signal to connect with UUT
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signal divident : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0'); --! Signal to connect with UUT
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--Outputs
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--Outputs
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signal quotient : std_logic_vector((nBitsLarge-1) downto 0); --! Signal to connect with UUT
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signal quotient : std_logic_vector((nBitsLarge-1) downto 0); --! Signal to connect with UUT
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signal reminder : std_logic_vector((nBitsLarge-1) downto 0); --! Signal to connect with UUT
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signal reminder : std_logic_vector((nBitsLarge-1) downto 0); --! Signal to connect with UUT
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signal done : std_logic;
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signal done : std_logic;
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-- Clock period definitions
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-- Clock period definitions
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constant clk_period : time := 10 ns;
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constant clk_period : time := 10 ns;
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BEGIN
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BEGIN
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--! Instantiate the Unit Under Test (UUT)
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--! Instantiate the Unit Under Test (UUT)
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uut: divisor PORT MAP (
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uut: divisor PORT MAP (
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rst => rst,
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rst => rst,
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clk => clk,
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clk => clk,
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quotient => quotient,
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quotient => quotient,
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reminder => reminder,
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reminder => reminder,
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numerator => numerator,
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numerator => numerator,
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divident => divident,
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divident => divident,
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done => done
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done => done
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);
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);
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-- Clock process definitions
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-- Clock process definitions
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clk_process :process
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clk_process :process
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begin
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begin
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clk <= '0';
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clk <= '0';
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wait for clk_period/2;
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wait for clk_period/2;
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clk <= '1';
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clk <= '1';
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wait for clk_period/2;
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wait for clk_period/2;
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end process;
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end process;
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-- Stimulus process
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-- Stimulus process
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stim_proc: process
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stim_proc: process
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begin
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begin
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-- hold reset state for 100 ns.
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-- hold reset state for 100 ns.
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rst <= '1';
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rst <= '1';
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numerator <= conv_std_logic_vector(50000000, 32);
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numerator <= conv_std_logic_vector(50000000, 32);
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divident <= conv_std_logic_vector(115200, 32);
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divident <= conv_std_logic_vector(115200, 32);
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wait for 20 ns;
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wait for clk_period;
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rst <= '0';
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rst <= '0';
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wait until done = '1';
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wait until done = '1';
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assert quotient = conv_std_logic_vector(434, 32) report "Wrong result... expected 434." severity failure;
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wait for clk_period;
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wait for clk_period;
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rst <= '1';
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rst <= '1';
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numerator <= conv_std_logic_vector(40, 32);
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numerator <= conv_std_logic_vector(40, 32);
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divident <= conv_std_logic_vector(5, 32);
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divident <= conv_std_logic_vector(5, 32);
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wait for 20 ns;
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wait for clk_period;
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rst <= '0';
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rst <= '0';
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wait until done = '1';
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wait until done = '1';
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assert quotient = conv_std_logic_vector(8, 32) report "Wrong result... expected 8." severity failure;
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wait for clk_period;
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wait for clk_period;
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-- insert stimulus here
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-- insert stimulus here
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assert false report "NONE. End of simulation." severity failure;
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assert false report "NONE. End of simulation." severity failure;
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end process;
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end process;
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END;
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END;
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