--! Test serial_receiver module
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--! Test serial_receiver module
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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--! Use CPU Definitions package
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--! Use CPU Definitions package
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use work.pkgDefinitions.all;
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use work.pkgDefinitions.all;
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ENTITY testSerial_receiver IS
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ENTITY testSerial_receiver IS
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END testSerial_receiver;
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END testSerial_receiver;
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ARCHITECTURE behavior OF testSerial_receiver IS
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ARCHITECTURE behavior OF testSerial_receiver IS
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-- Component Declaration for the Unit Under Test (UUT)
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT serial_receiver
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COMPONENT serial_receiver
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PORT(
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Port (
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rst : IN std_logic;
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rst : in STD_LOGIC; --! Reset input
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baudOverSampleClk : IN std_logic;
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baudOverSampleClk : in STD_LOGIC; --! Baud oversampled 8x (Best way to detect start bit)
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serial_in : IN std_logic;
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serial_in : in STD_LOGIC; --! Uart serial input
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data_ready : OUT std_logic;
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data_ready : out STD_LOGIC; --! Data received and ready to be read
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data_byte : OUT std_logic_vector((nBits-1) downto 0)
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data_byte : out STD_LOGIC_VECTOR ((nBits-1) downto 0)); --! Data byte received
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);
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END COMPONENT;
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END COMPONENT;
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--Inputs
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--Inputs
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signal rst : std_logic := '0';
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signal rst : std_logic := '0'; --! Signal to connect with UUT
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signal baudClk : std_logic := '0';
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signal baudClk : std_logic := '0'; --! Signal to connect with UUT
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signal baudOverSampleClk : std_logic := '0';
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signal baudOverSampleClk : std_logic := '0'; --! Signal to connect with UUT
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signal serial_in : std_logic := '0';
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signal serial_in : std_logic := '0'; --! Signal to connect with UUT
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--Outputs
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--Outputs
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signal data_ready : std_logic;
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signal data_ready : std_logic; --! Signal to connect with UUT
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signal data_byte : std_logic_vector((nBits-1) downto 0);
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signal data_byte : std_logic_vector((nBits-1) downto 0); --! Signal to connect with UUT
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-- Clock period definitions
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-- Clock period definitions
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constant baudClk_period : time := 8.6805 us;
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constant baudClk_period : time := 8.6805 us;
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constant baudOverSampleClk_period : time :=1.085 us;
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constant baudOverSampleClk_period : time :=1.085 us;
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BEGIN
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BEGIN
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--! Instantiate the Unit Under Test (UUT)
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--! Instantiate the Unit Under Test (UUT)
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uut: serial_receiver PORT MAP (
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uut: serial_receiver PORT MAP (
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rst => rst,
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rst => rst,
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baudOverSampleClk => baudOverSampleClk,
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baudOverSampleClk => baudOverSampleClk,
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serial_in => serial_in,
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serial_in => serial_in,
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data_ready => data_ready,
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data_ready => data_ready,
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data_byte => data_byte
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data_byte => data_byte
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);
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);
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-- Clock process definitions
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-- Clock process definitions
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baudClk_process :process
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baudClk_process :process
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begin
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begin
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baudClk <= '0';
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baudClk <= '0';
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wait for baudClk_period/2;
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wait for baudClk_period/2;
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baudClk <= '1';
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baudClk <= '1';
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wait for baudClk_period/2;
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wait for baudClk_period/2;
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end process;
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end process;
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baudOverSampleClk_process :process
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baudOverSampleClk_process :process
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begin
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begin
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baudOverSampleClk <= '0';
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baudOverSampleClk <= '0';
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wait for baudOverSampleClk_period/2;
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wait for baudOverSampleClk_period/2;
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baudOverSampleClk <= '1';
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baudOverSampleClk <= '1';
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wait for baudOverSampleClk_period/2;
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wait for baudOverSampleClk_period/2;
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end process;
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end process;
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-- Stimulus process
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-- Stimulus process
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stim_proc: process
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stim_proc: process
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begin
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begin
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rst <= '1';
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rst <= '1';
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serial_in <= '1'; -- Idle
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serial_in <= '1'; -- Idle
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wait for 3 us;
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wait for 3 us;
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rst <= '0';
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rst <= '0';
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wait for baudClk_period * 3;
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wait for baudClk_period * 3;
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-- Receive 0xC4 value (11000100)
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-- Receive 0xC4 value (11000100)
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-- Start bit here
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-- Start bit here
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serial_in <= '0';
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serial_in <= '0';
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wait for baudClk_period;
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wait for baudClk_period;
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serial_in <= '0';
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serial_in <= '0';
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wait for baudClk_period;
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wait for baudClk_period;
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serial_in <= '0';
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serial_in <= '0';
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wait for baudClk_period;
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wait for baudClk_period;
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serial_in <= '1';
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serial_in <= '1';
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wait for baudClk_period;
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wait for baudClk_period;
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serial_in <= '0';
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serial_in <= '0';
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wait for baudClk_period;
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wait for baudClk_period;
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serial_in <= '0';
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serial_in <= '0';
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wait for baudClk_period;
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wait for baudClk_period;
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serial_in <= '0';
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serial_in <= '0';
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wait for baudClk_period;
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wait for baudClk_period;
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serial_in <= '1';
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serial_in <= '1';
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wait for baudClk_period;
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wait for baudClk_period;
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serial_in <= '1';
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serial_in <= '1';
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wait for baudClk_period;
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wait for baudClk_period;
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-- Stop bit here
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-- Stop bit here
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serial_in <= '1';
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serial_in <= '1';
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wait for baudClk_period * 8;
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wait for baudClk_period * 8;
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-- Receive 0x55 value (01010101)
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-- Receive 0x55 value (01010101)
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-- Start bit here
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-- Start bit here
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serial_in <= '0';
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serial_in <= '0';
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wait for baudClk_period;
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wait for baudClk_period;
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serial_in <= '1';
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serial_in <= '1';
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wait for baudClk_period;
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wait for baudClk_period;
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serial_in <= '0';
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serial_in <= '0';
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wait for baudClk_period;
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wait for baudClk_period;
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serial_in <= '1';
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serial_in <= '1';
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wait for baudClk_period;
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wait for baudClk_period;
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serial_in <= '0';
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serial_in <= '0';
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wait for baudClk_period;
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wait for baudClk_period;
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serial_in <= '1';
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serial_in <= '1';
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wait for baudClk_period;
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wait for baudClk_period;
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serial_in <= '0';
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serial_in <= '0';
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wait for baudClk_period;
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wait for baudClk_period;
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serial_in <= '1';
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serial_in <= '1';
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wait for baudClk_period;
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wait for baudClk_period;
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serial_in <= '0';
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serial_in <= '0';
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wait for baudClk_period;
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wait for baudClk_period;
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-- Stop bit here
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-- Stop bit here
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serial_in <= '1';
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serial_in <= '1';
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wait for baudClk_period * 1;
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wait for baudClk_period * 1;
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-- Stop Simulation
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-- Stop Simulation
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assert false report "NONE. End of simulation." severity failure;
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assert false report "NONE. End of simulation." severity failure;
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wait;
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wait;
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end process;
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end process;
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END;
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END;
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