--! Test serial_receiver module
|
--! @file
|
|
--! @brief Test serial_receiver module module
|
|
|
|
--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
|
LIBRARY ieee;
|
LIBRARY ieee;
|
USE ieee.std_logic_1164.ALL;
|
USE ieee.std_logic_1164.ALL;
|
|
|
--! Use CPU Definitions package
|
--! Use CPU Definitions package
|
use work.pkgDefinitions.all;
|
use work.pkgDefinitions.all;
|
|
|
ENTITY testSerial_receiver IS
|
ENTITY testSerial_receiver IS
|
END testSerial_receiver;
|
END testSerial_receiver;
|
|
|
|
--! @brief Test serial_receiver module module
|
|
--! @details Receive some simulated byte stream and verify received values
|
ARCHITECTURE behavior OF testSerial_receiver IS
|
ARCHITECTURE behavior OF testSerial_receiver IS
|
|
|
-- Component Declaration for the Unit Under Test (UUT)
|
-- Component Declaration for the Unit Under Test (UUT)
|
|
|
COMPONENT serial_receiver
|
COMPONENT serial_receiver
|
Port (
|
Port (
|
rst : in STD_LOGIC; --! Reset input
|
rst : in STD_LOGIC; --! Reset input
|
baudOverSampleClk : in STD_LOGIC; --! Baud oversampled 8x (Best way to detect start bit)
|
baudOverSampleClk : in STD_LOGIC; --! Baud oversampled 8x (Best way to detect start bit)
|
serial_in : in STD_LOGIC; --! Uart serial input
|
serial_in : in STD_LOGIC; --! Uart serial input
|
data_ready : out STD_LOGIC; --! Data received and ready to be read
|
data_ready : out STD_LOGIC; --! Data received and ready to be read
|
data_byte : out STD_LOGIC_VECTOR ((nBits-1) downto 0)); --! Data byte received
|
data_byte : out STD_LOGIC_VECTOR ((nBits-1) downto 0)); --! Data byte received
|
END COMPONENT;
|
END COMPONENT;
|
|
|
|
|
--Inputs
|
--Inputs
|
signal rst : std_logic := '0'; --! Signal to connect with UUT
|
signal rst : std_logic := '0'; --! Signal to connect with UUT
|
signal baudClk : std_logic := '0'; --! Signal to connect with UUT
|
signal baudClk : std_logic := '0'; --! Signal to connect with UUT
|
signal baudOverSampleClk : std_logic := '0'; --! Signal to connect with UUT
|
signal baudOverSampleClk : std_logic := '0'; --! Signal to connect with UUT
|
signal serial_in : std_logic := '0'; --! Signal to connect with UUT
|
signal serial_in : std_logic := '0'; --! Signal to connect with UUT
|
|
|
--Outputs
|
--Outputs
|
signal data_ready : std_logic; --! Signal to connect with UUT
|
signal data_ready : std_logic; --! Signal to connect with UUT
|
signal data_byte : std_logic_vector((nBits-1) downto 0); --! Signal to connect with UUT
|
signal data_byte : std_logic_vector((nBits-1) downto 0); --! Signal to connect with UUT
|
|
|
-- Clock period definitions
|
-- Clock period definitions
|
constant baudClk_period : time := 8.6805 us;
|
constant baudClk_period : time := 8.6805 us;
|
constant baudOverSampleClk_period : time :=1.085 us;
|
constant baudOverSampleClk_period : time :=1.085 us;
|
|
|
BEGIN
|
BEGIN
|
|
|
--! Instantiate the Unit Under Test (UUT)
|
--! Instantiate the Unit Under Test (UUT)
|
uut: serial_receiver PORT MAP (
|
uut: serial_receiver PORT MAP (
|
rst => rst,
|
rst => rst,
|
baudOverSampleClk => baudOverSampleClk,
|
baudOverSampleClk => baudOverSampleClk,
|
serial_in => serial_in,
|
serial_in => serial_in,
|
data_ready => data_ready,
|
data_ready => data_ready,
|
data_byte => data_byte
|
data_byte => data_byte
|
);
|
);
|
|
|
-- Clock process definitions
|
-- Clock process definitions
|
baudClk_process :process
|
baudClk_process :process
|
begin
|
begin
|
baudClk <= '0';
|
baudClk <= '0';
|
wait for baudClk_period/2;
|
wait for baudClk_period/2;
|
baudClk <= '1';
|
baudClk <= '1';
|
wait for baudClk_period/2;
|
wait for baudClk_period/2;
|
end process;
|
end process;
|
|
|
baudOverSampleClk_process :process
|
baudOverSampleClk_process :process
|
begin
|
begin
|
baudOverSampleClk <= '0';
|
baudOverSampleClk <= '0';
|
wait for baudOverSampleClk_period/2;
|
wait for baudOverSampleClk_period/2;
|
baudOverSampleClk <= '1';
|
baudOverSampleClk <= '1';
|
wait for baudOverSampleClk_period/2;
|
wait for baudOverSampleClk_period/2;
|
end process;
|
end process;
|
|
|
|
|
-- Stimulus process
|
-- Stimulus process
|
stim_proc: process
|
stim_proc: process
|
begin
|
begin
|
rst <= '1';
|
rst <= '1';
|
serial_in <= '1'; -- Idle
|
serial_in <= '1'; -- Idle
|
wait for 3 us;
|
wait for 3 us;
|
rst <= '0';
|
rst <= '0';
|
wait for baudClk_period * 3;
|
wait for baudClk_period * 3;
|
|
|
-- Receive 0xC4 value (11000100)
|
-- Receive 0xC4 value (11000100)
|
-- Start bit here
|
-- Start bit here
|
serial_in <= '0';
|
serial_in <= '0';
|
wait for baudClk_period;
|
wait for baudClk_period;
|
|
|
serial_in <= '0';
|
serial_in <= '0';
|
wait for baudClk_period;
|
wait for baudClk_period;
|
serial_in <= '0';
|
serial_in <= '0';
|
wait for baudClk_period;
|
wait for baudClk_period;
|
serial_in <= '1';
|
serial_in <= '1';
|
wait for baudClk_period;
|
wait for baudClk_period;
|
serial_in <= '0';
|
serial_in <= '0';
|
wait for baudClk_period;
|
wait for baudClk_period;
|
serial_in <= '0';
|
serial_in <= '0';
|
wait for baudClk_period;
|
wait for baudClk_period;
|
serial_in <= '0';
|
serial_in <= '0';
|
wait for baudClk_period;
|
wait for baudClk_period;
|
serial_in <= '1';
|
serial_in <= '1';
|
wait for baudClk_period;
|
wait for baudClk_period;
|
serial_in <= '1';
|
serial_in <= '1';
|
wait for baudClk_period;
|
wait for baudClk_period;
|
|
|
-- Stop bit here
|
-- Stop bit here
|
serial_in <= '1';
|
serial_in <= '1';
|
|
---wait until data_ready = '1';
|
|
assert data_byte = X"C4" report "Wrong result... expected 0xC4" severity failure;
|
wait for baudClk_period * 8;
|
wait for baudClk_period * 8;
|
|
|
-- Receive 0x55 value (01010101)
|
-- Receive 0x55 value (01010101)
|
-- Start bit here
|
-- Start bit here
|
serial_in <= '0';
|
serial_in <= '0';
|
wait for baudClk_period;
|
wait for baudClk_period;
|
|
|
serial_in <= '1';
|
serial_in <= '1';
|
wait for baudClk_period;
|
wait for baudClk_period;
|
serial_in <= '0';
|
serial_in <= '0';
|
wait for baudClk_period;
|
wait for baudClk_period;
|
serial_in <= '1';
|
serial_in <= '1';
|
wait for baudClk_period;
|
wait for baudClk_period;
|
serial_in <= '0';
|
serial_in <= '0';
|
wait for baudClk_period;
|
wait for baudClk_period;
|
serial_in <= '1';
|
serial_in <= '1';
|
wait for baudClk_period;
|
wait for baudClk_period;
|
serial_in <= '0';
|
serial_in <= '0';
|
wait for baudClk_period;
|
wait for baudClk_period;
|
serial_in <= '1';
|
serial_in <= '1';
|
wait for baudClk_period;
|
wait for baudClk_period;
|
serial_in <= '0';
|
serial_in <= '0';
|
wait for baudClk_period;
|
wait for baudClk_period;
|
|
|
-- Stop bit here
|
-- Stop bit here
|
serial_in <= '1';
|
serial_in <= '1';
|
wait for baudClk_period * 1;
|
wait for baudClk_period * 1;
|
|
---wait until data_ready = '1';
|
|
assert data_byte = X"55" report "Wrong result... expected 0x55" severity failure;
|
|
|
-- Stop Simulation
|
-- Stop Simulation
|
assert false report "NONE. End of simulation." severity failure;
|
assert false report "NONE. End of simulation." severity failure;
|
|
|
wait;
|
wait;
|
end process;
|
end process;
|
|
|
END;
|
END;
|
|
|