--! Test serial_transmitter module
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--! @file
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--! @brief Test serial_transmitter module
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--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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--! Use CPU Definitions package
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--! Use CPU Definitions package
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use work.pkgDefinitions.all;
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use work.pkgDefinitions.all;
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ENTITY testSerial_transmitter IS
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ENTITY testSerial_transmitter IS
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END testSerial_transmitter;
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END testSerial_transmitter;
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--! @brief Test serial_transmitter module
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--! @details Just send the date over the serial_out and analyse the results
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ARCHITECTURE behavior OF testSerial_transmitter IS
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ARCHITECTURE behavior OF testSerial_transmitter IS
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-- Component Declaration for the Unit Under Test (UUT)
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT serial_transmitter
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COMPONENT serial_transmitter
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Port ( rst : in STD_LOGIC; --! Reset input
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Port ( rst : in STD_LOGIC; --! Reset input
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baudClk : in STD_LOGIC; --! Baud rate clock input
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baudClk : in STD_LOGIC; --! Baud rate clock input
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data_byte : in STD_LOGIC_VECTOR ((nBits-1) downto 0); --! Byte to be sent
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data_byte : in STD_LOGIC_VECTOR ((nBits-1) downto 0); --! Byte to be sent
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data_sent : out STD_LOGIC; --! Indicate that byte has been sent
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data_sent : out STD_LOGIC; --! Indicate that byte has been sent
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serial_out : out STD_LOGIC); --! Uart serial output
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serial_out : out STD_LOGIC); --! Uart serial output
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END COMPONENT;
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END COMPONENT;
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--Inputs
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--Inputs
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signal rst : std_logic := '0'; --! Signal to connect with UUT
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signal rst : std_logic := '0'; --! Signal to connect with UUT
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signal baudClk : std_logic := '0'; --! Signal to connect with UUT
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signal baudClk : std_logic := '0'; --! Signal to connect with UUT
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signal data_byte : std_logic_vector(7 downto 0) := (others => '0'); --! Signal to connect with UUT
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signal data_byte : std_logic_vector(7 downto 0) := (others => '0'); --! Signal to connect with UUT
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--Outputs
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--Outputs
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signal data_sent : std_logic; --! Signal to connect with UUT
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signal data_sent : std_logic; --! Signal to connect with UUT
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signal serial_out : std_logic; --! Signal to connect with UUT
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signal serial_out : std_logic; --! Signal to connect with UUT
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-- Clock period definitions
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-- Clock period definitions
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constant baudClk_period : time := 10 ns;
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constant baudClk_period : time := 10 ns;
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BEGIN
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BEGIN
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--! Instantiate the Unit Under Test (UUT)
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--! Instantiate the Unit Under Test (UUT)
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uut: serial_transmitter PORT MAP (
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uut: serial_transmitter PORT MAP (
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rst => rst,
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rst => rst,
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baudClk => baudClk,
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baudClk => baudClk,
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data_byte => data_byte,
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data_byte => data_byte,
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data_sent => data_sent,
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data_sent => data_sent,
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serial_out => serial_out
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serial_out => serial_out
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);
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);
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-- Clock process definitions
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-- Clock process definitions
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baudClk_process :process
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baudClk_process :process
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begin
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begin
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baudClk <= '0';
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baudClk <= '0';
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wait for baudClk_period/2;
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wait for baudClk_period/2;
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baudClk <= '1';
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baudClk <= '1';
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wait for baudClk_period/2;
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wait for baudClk_period/2;
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end process;
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end process;
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-- Stimulus process
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-- Stimulus process
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stim_proc: process
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stim_proc: process
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begin
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begin
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-- Prepare the data to be sent 0x55
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-- Prepare the data to be sent 0x55
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rst <= '1';
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rst <= '1';
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data_byte <= "01010101";
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data_byte <= "01010101";
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wait for 50 ns;
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wait for 50 ns;
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rst <= '0';
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rst <= '0';
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-- Test serial data...
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wait until rising_edge(baudClk); -- Start bit
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wait for 1 ns;
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assert serial_out = '0' report "Invalid value " severity failure;
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for numBit in 0 to 7 loop
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wait until rising_edge(baudClk);
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wait for 1 ns;
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-- The image attribute convert a typed value into a string
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report "Testing bit:" & integer'image(numBit) & " value " & std_logic'image(serial_out);
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assert serial_out = data_byte(numBit) report "Invalid value on bit:" severity failure;
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end loop;
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wait until data_sent = '1';
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wait until data_sent = '1';
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wait for baudClk_period*3;
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wait for baudClk_period*3;
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-- Prepare the data to be sent
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-- Prepare the data to be sent
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rst <= '1';
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rst <= '1';
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data_byte <= "11000100";
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data_byte <= "11000100";
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wait for 50 ns;
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wait for 50 ns;
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rst <= '0';
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rst <= '0';
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-- Test serial data...
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wait until rising_edge(baudClk); -- Start bit
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wait for 1 ns;
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assert serial_out = '0' report "Invalid value " severity failure;
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for numBit in 0 to (data_byte'LENGTH-1) loop
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-- Wait for the clock rising edge
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wait until rising_edge(baudClk);
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wait for 1 ns;
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report "Testing bit:" & integer'image(numBit) & " value " & std_logic'image(serial_out);
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assert serial_out = data_byte(numBit) report "Invalid value on bit:" severity failure;
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end loop;
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wait until data_sent = '1';
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wait until data_sent = '1';
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wait for baudClk_period*3;
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wait for baudClk_period*3;
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-- Stop Simulation
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-- Stop Simulation
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assert false report "NONE. End of simulation." severity failure;
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assert false report "NONE. End of simulation." severity failure;
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wait;
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wait;
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end process;
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end process;
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END;
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END;
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