--! Test baud_generator module
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--! Test baud_generator module
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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--! Use Global Definitions package
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--! Use Global Definitions package
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use work.pkgDefinitions.all;
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use work.pkgDefinitions.all;
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ENTITY testUart_communication_block IS
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ENTITY testUart_communication_block IS
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END testUart_communication_block;
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END testUart_communication_block;
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ARCHITECTURE behavior OF testUart_communication_block IS
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ARCHITECTURE behavior OF testUart_communication_block IS
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-- Component Declaration for the Unit Under Test (UUT)
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT uart_communication_blocks
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COMPONENT uart_communication_blocks
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Port ( rst : in STD_LOGIC;
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Port ( rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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clk : in STD_LOGIC;
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cycle_wait_baud : in std_logic_vector((nBitsLarge-1) downto 0);
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cycle_wait_baud : in std_logic_vector((nBitsLarge-1) downto 0);
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byte_tx : in STD_LOGIC_VECTOR ((nBits-1) downto 0);
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byte_tx : in STD_LOGIC_VECTOR ((nBits-1) downto 0);
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byte_rx : out STD_LOGIC_VECTOR ((nBits-1) downto 0);
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byte_rx : out STD_LOGIC_VECTOR ((nBits-1) downto 0);
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data_sent_tx : out STD_LOGIC;
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data_sent_tx : out STD_LOGIC;
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data_received_rx : out STD_LOGIC;
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data_received_rx : out STD_LOGIC;
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serial_out : out std_logic;
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serial_out : out std_logic;
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serial_in : in std_logic;
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serial_in : in std_logic;
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start_tx : in STD_LOGIC);
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start_tx : in STD_LOGIC);
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END COMPONENT;
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END COMPONENT;
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--Inputs
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--Inputs
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signal rst : std_logic := '0';
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signal rst : std_logic := '0';
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signal clk : std_logic := '0';
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signal clk : std_logic := '0';
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signal cycle_wait_baud : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0');
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signal cycle_wait_baud : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0');
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signal byte_tx : std_logic_vector((nBits-1) downto 0) := (others => '0');
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signal byte_tx : std_logic_vector((nBits-1) downto 0) := (others => '0');
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signal serial_in : std_logic := '0';
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signal serial_in : std_logic := '0';
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signal start_tx : std_logic := '0';
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signal start_tx : std_logic := '0';
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--Outputs
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--Outputs
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signal byte_rx : std_logic_vector((nBits-1) downto 0);
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signal byte_rx : std_logic_vector((nBits-1) downto 0);
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signal data_sent_tx : std_logic;
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signal data_sent_tx : std_logic;
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signal data_received_rx : std_logic;
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signal data_received_rx : std_logic;
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signal serial_out : std_logic;
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signal serial_out : std_logic;
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-- Clock period definitions
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-- Clock period definitions
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constant clk_period : time := 0.543 us; -- 0.543us (1.8432Mhz) 2ns (50Mhz)
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constant clk_period : time := 0.543 us; -- 0.543us (1.8432Mhz) 2ns (50Mhz)
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BEGIN
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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-- Instantiate the Unit Under Test (UUT)
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uut: uart_communication_blocks PORT MAP (
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uut: uart_communication_blocks PORT MAP (
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rst => rst,
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rst => rst,
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clk => clk,
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clk => clk,
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cycle_wait_baud => cycle_wait_baud,
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cycle_wait_baud => cycle_wait_baud,
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byte_tx => byte_tx,
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byte_tx => byte_tx,
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byte_rx => byte_rx,
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byte_rx => byte_rx,
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data_sent_tx => data_sent_tx,
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data_sent_tx => data_sent_tx,
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data_received_rx => data_received_rx,
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data_received_rx => data_received_rx,
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serial_out => serial_out,
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serial_out => serial_out,
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serial_in => serial_in,
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serial_in => serial_in,
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start_tx => start_tx
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start_tx => start_tx
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);
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);
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-- Clock process definitions
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-- Clock process definitions
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clk_process :process
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clk_process :process
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begin
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begin
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clk <= '0';
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clk <= '0';
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wait for clk_period/2;
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wait for clk_period/2;
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clk <= '1';
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clk <= '1';
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wait for clk_period/2;
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wait for clk_period/2;
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end process;
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end process;
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-- Stimulus process
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-- Stimulus process
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stim_proc: process
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stim_proc: process
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begin
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begin
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-- Setup communication blocks
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-- Setup communication blocks
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rst <= '1';
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rst <= '1';
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serial_in <= '1'; -- Idle..
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cycle_wait_baud <= conv_std_logic_vector(16, (nBitsLarge));
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cycle_wait_baud <= conv_std_logic_vector(16, (nBitsLarge));
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start_tx <= '0';
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wait for 2 ns;
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wait for 2 ns;
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rst <= '0';
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rst <= '0';
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wait for clk_period*10;
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-- Send data..
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start_tx <= '1';
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byte_tx <= "01010101";
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wait until data_sent_tx = '1';
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wait for clk_period*3;
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start_tx <= '0';
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wait for clk_period*3;
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start_tx <= '1';
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byte_tx <= "11000100";
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wait until data_sent_tx = '1';
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wait for clk_period*3;
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start_tx <= '0';
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wait for clk_period*3;
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-- Receive data...
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-- Receive 0x55 value (01010101)
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serial_in <= '0'; -- Start bit
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wait for 8.68 us;
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serial_in <= '1';
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wait for 8.68 us;
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serial_in <= '0';
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wait for 8.68 us;
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serial_in <= '1';
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wait for 8.68 us;
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serial_in <= '0';
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wait for 8.68 us;
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serial_in <= '1';
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wait for 8.68 us;
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serial_in <= '0';
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wait for 8.68 us;
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serial_in <= '1';
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wait for 8.68 us;
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serial_in <= '0';
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wait for 8.68 us;
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-- Stop bit here
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serial_in <= '1';
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wait for clk_period*20;
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-- Receive 0xC4 value (11000100)
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serial_in <= '0'; -- Start bit
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wait for 8.68 us;
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serial_in <= '0';
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wait for 8.68 us;
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serial_in <= '0';
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wait for 8.68 us;
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serial_in <= '1';
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wait for 8.68 us;
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serial_in <= '0';
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wait for 8.68 us;
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serial_in <= '0';
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wait for 8.68 us;
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serial_in <= '0';
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wait for 8.68 us;
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serial_in <= '1';
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wait for 8.68 us;
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serial_in <= '1';
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wait for 8.68 us;
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-- Stop bit here
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serial_in <= '1';
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wait for clk_period*20;
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-- insert stimulus here
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wait;
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-- Stop Simulation
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assert false report "NONE. End of simulation." severity failure;
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end process;
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end process;
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END;
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END;
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