--! Test baud_generator module
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--! Test baud_generator module
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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--! Use Global Definitions package
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--! Use Global Definitions package
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use work.pkgDefinitions.all;
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use work.pkgDefinitions.all;
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ENTITY testUart_control IS
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ENTITY testUart_control IS
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END testUart_control;
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END testUart_control;
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ARCHITECTURE behavior OF testUart_control IS
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ARCHITECTURE behavior OF testUart_control IS
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-- Component Declaration for the Unit Under Test (UUT)
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT uart_control
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COMPONENT uart_control
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Port ( rst : in std_logic; -- Global reset
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Port ( rst : in std_logic; -- Global reset
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clk : in std_logic; -- Global clock
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clk : in std_logic; -- Global clock
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WE : in std_logic; -- Write enable
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WE : in std_logic; -- Write enable
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reg_addr : in std_logic_vector (1 downto 0); -- Register address
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reg_addr : in std_logic_vector (1 downto 0); -- Register address
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start : in std_logic; -- Start (Strobe)
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start : in std_logic; -- Start (Strobe)
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done : out std_logic; -- Done (ACK)
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done : out std_logic; -- Done (ACK)
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DAT_I : in std_logic_vector ((nBitsLarge-1) downto 0); -- Data Input (Wishbone)
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DAT_I : in std_logic_vector ((nBitsLarge-1) downto 0); -- Data Input (Wishbone)
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DAT_O : out std_logic_vector ((nBitsLarge-1) downto 0); -- Data output (Wishbone)
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DAT_O : out std_logic_vector ((nBitsLarge-1) downto 0); -- Data output (Wishbone)
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baud_wait : out std_logic_vector ((nBitsLarge-1) downto 0); -- Signal to control the baud rate frequency
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baud_wait : out std_logic_vector ((nBitsLarge-1) downto 0); -- Signal to control the baud rate frequency
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data_byte_tx : out std_logic_vector((nBits-1) downto 0); -- 1 Byte to be send to serial_transmitter
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data_byte_tx : out std_logic_vector((nBits-1) downto 0); -- 1 Byte to be send to serial_transmitter
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data_byte_rx : in std_logic_vector((nBits-1) downto 0); -- 1 Byte to be received by serial_receiver
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data_byte_rx : in std_logic_vector((nBits-1) downto 0); -- 1 Byte to be received by serial_receiver
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tx_data_sent : in std_logic; -- Signal comming from serial_transmitter
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tx_data_sent : in std_logic; -- Signal comming from serial_transmitter
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tx_start : out std_logic; -- Signal to start sending serial data...
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tx_start : out std_logic; -- Signal to start sending serial data...
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rst_comm_blocks : out std_logic; -- Reset Communication blocks
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rst_comm_blocks : out std_logic; -- Reset Communication blocks
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rx_data_ready : in std_logic);
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rx_data_ready : in std_logic);
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END COMPONENT;
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END COMPONENT;
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--Inputs
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--Inputs
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signal rst : std_logic := '0';
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signal rst : std_logic := '0';
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signal clk : std_logic := '0';
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signal clk : std_logic := '0';
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signal WE : std_logic := '0';
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signal WE : std_logic := '0';
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signal reg_addr : std_logic_vector(1 downto 0) := (others => '0');
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signal reg_addr : std_logic_vector(1 downto 0) := (others => '0');
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signal start : std_logic := '0';
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signal start : std_logic := '0';
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signal DAT_I : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0');
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signal DAT_I : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0');
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signal data_byte_rx : std_logic_vector((nBits-1) downto 0) := (others => '0');
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signal data_byte_rx : std_logic_vector((nBits-1) downto 0) := (others => '0');
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signal tx_data_sent : std_logic := '0';
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signal tx_data_sent : std_logic := '0';
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signal rx_data_ready : std_logic := '0';
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signal rx_data_ready : std_logic := '0';
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--Outputs
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--Outputs
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signal done : std_logic;
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signal done : std_logic;
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signal tx_start : std_logic;
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signal tx_start : std_logic;
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signal rst_comm_blocks : std_logic;
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signal rst_comm_blocks : std_logic;
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signal DAT_O : std_logic_vector((nBitsLarge-1) downto 0);
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signal DAT_O : std_logic_vector((nBitsLarge-1) downto 0);
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signal baud_wait : std_logic_vector((nBitsLarge-1) downto 0);
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signal baud_wait : std_logic_vector((nBitsLarge-1) downto 0);
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signal data_byte_tx : std_logic_vector((nBits-1) downto 0);
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signal data_byte_tx : std_logic_vector((nBits-1) downto 0);
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-- Clock period definitions
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-- Clock period definitions
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constant clk_period : time := 2 ns; -- 2ns (50Mhz)
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constant clk_period : time := 20 ns; -- 20ns (50Mhz)
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BEGIN
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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-- Instantiate the Unit Under Test (UUT)
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uut: uart_control PORT MAP (
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uut: uart_control PORT MAP (
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rst => rst,
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rst => rst,
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clk => clk,
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clk => clk,
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WE => WE,
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WE => WE,
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reg_addr => reg_addr,
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reg_addr => reg_addr,
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start => start,
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start => start,
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done => done,
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done => done,
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DAT_I => DAT_I,
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DAT_I => DAT_I,
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DAT_O => DAT_O,
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DAT_O => DAT_O,
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baud_wait => baud_wait,
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baud_wait => baud_wait,
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data_byte_tx => data_byte_tx,
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data_byte_tx => data_byte_tx,
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data_byte_rx => data_byte_rx,
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data_byte_rx => data_byte_rx,
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tx_data_sent => tx_data_sent,
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tx_data_sent => tx_data_sent,
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rst_comm_blocks => rst_comm_blocks,
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rst_comm_blocks => rst_comm_blocks,
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tx_start => tx_start,
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tx_start => tx_start,
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rx_data_ready => rx_data_ready
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rx_data_ready => rx_data_ready
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);
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);
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-- Clock process definitions
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-- Clock process definitions
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clk_process :process
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clk_process :process
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begin
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begin
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clk <= '0';
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clk <= '0';
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wait for clk_period/2;
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wait for clk_period/2;
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clk <= '1';
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clk <= '1';
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wait for clk_period/2;
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wait for clk_period/2;
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end process;
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end process;
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-- Stimulus process
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-- Stimulus process
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stim_proc: process
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stim_proc: process
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begin
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begin
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rst <= '1';
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rst <= '1';
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wait for 1 ns;
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wait for 1 ns;
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rst <= '0';
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rst <= '0';
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wait for clk_period*3;
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wait for clk_period*3;
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-- Configure the clock...
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-- Configure the clock...
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reg_addr <= "00";
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reg_addr <= "00";
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WE <= '1';
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WE <= '1';
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start <= '1';
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start <= '1';
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DAT_I <= conv_std_logic_vector(50000000, (nBitsLarge));
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DAT_I <= conv_std_logic_vector(50000000, (nBitsLarge));
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wait until done = '1';
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wait until done = '1';
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WE <= '0';
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WE <= '0';
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start <= '0';
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start <= '0';
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reg_addr <= (others => 'U');
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reg_addr <= (others => 'U');
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wait for clk_period;
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wait for clk_period;
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-- Configure the Baud...
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-- Configure the Baud...
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reg_addr <= "01";
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reg_addr <= "01";
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WE <= '1';
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WE <= '1';
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start <= '1';
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start <= '1';
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DAT_I <= conv_std_logic_vector(115200, (nBitsLarge));
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DAT_I <= conv_std_logic_vector(115200, (nBitsLarge));
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wait until done = '1';
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wait until done = '1';
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WE <= '0';
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WE <= '0';
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start <= '0';
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start <= '0';
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reg_addr <= (others => 'U');
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reg_addr <= (others => 'U');
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wait for clk_period;
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wait for clk_period;
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-- Ask to send some data...(0x55)
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-- Ask to send some data...(0x55)
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reg_addr <= "10";
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reg_addr <= "10";
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WE <= '1';
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WE <= '1';
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start <= '1';
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start <= '1';
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DAT_I <= x"00000055";
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DAT_I <= x"00000055";
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wait for clk_period*10; -- No point to use wait until because we're not connected to the comm block yet
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wait for clk_period*10; -- No point to use wait until because we're not connected to the comm block yet
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-- Stop Simulation
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-- Stop Simulation
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assert false report "NONE. End of simulation." severity failure;
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assert false report "NONE. End of simulation." severity failure;
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end process;
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end process;
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END;
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END;
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