--! Top level for interconnection between communication blocks: serial_transmitter, serial_receiver, baud_generator
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--! Top level for interconnection between communication blocks: serial_transmitter, serial_receiver, baud_generator
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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--! Use CPU Definitions package
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--! Use CPU Definitions package
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use work.pkgDefinitions.all;
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use work.pkgDefinitions.all;
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entity uart_communication_blocks is
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entity uart_communication_blocks is
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Port ( rst : in STD_LOGIC;
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Port ( rst : in STD_LOGIC; --! Global reset
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clk : in STD_LOGIC;
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clk : in STD_LOGIC; --! Global clock
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cycle_wait_baud : in std_logic_vector((nBitsLarge-1) downto 0);
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cycle_wait_baud : in std_logic_vector((nBitsLarge-1) downto 0); --! Number of cycles to wait in order to generate desired baud
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byte_tx : in STD_LOGIC_VECTOR ((nBits-1) downto 0);
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byte_tx : in STD_LOGIC_VECTOR ((nBits-1) downto 0); --! Byte to transmit
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byte_rx : out STD_LOGIC_VECTOR ((nBits-1) downto 0);
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byte_rx : out STD_LOGIC_VECTOR ((nBits-1) downto 0); --! Byte to receive
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data_sent_tx : out STD_LOGIC;
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data_sent_tx : out STD_LOGIC; --! Indicate that byte has been sent
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data_received_rx : out STD_LOGIC;
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data_received_rx : out STD_LOGIC; --! Indicate that we got a byte
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serial_out : out std_logic;
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serial_out : out std_logic; --! Uart serial out
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serial_in : in std_logic;
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serial_in : in std_logic; --! Uart serial in
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start_tx : in STD_LOGIC);
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start_tx : in STD_LOGIC); --! Initiate transmission
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end uart_communication_blocks;
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end uart_communication_blocks;
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architecture Behavioral of uart_communication_blocks is
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architecture Behavioral of uart_communication_blocks is
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-- Declare components...
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-- Declare components...
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component baud_generator is
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component baud_generator is
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Port ( rst : in STD_LOGIC;
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Port ( rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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clk : in STD_LOGIC;
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cycle_wait : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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cycle_wait : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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baud_oversample : out std_logic;
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baud_oversample : out std_logic;
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baud : out STD_LOGIC);
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baud : out STD_LOGIC);
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end component;
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end component;
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component serial_transmitter is
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component serial_transmitter is
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Port ( rst : in STD_LOGIC;
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Port ( rst : in STD_LOGIC;
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baudClk : in STD_LOGIC;
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baudClk : in STD_LOGIC;
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data_byte : in STD_LOGIC_VECTOR ((nBits-1) downto 0);
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data_byte : in STD_LOGIC_VECTOR ((nBits-1) downto 0);
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data_sent : out STD_LOGIC;
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data_sent : out STD_LOGIC;
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serial_out : out STD_LOGIC);
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serial_out : out STD_LOGIC);
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end component;
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end component;
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component serial_receiver is
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component serial_receiver is
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Port (
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Port (
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rst : in STD_LOGIC;
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rst : in STD_LOGIC;
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baudOverSampleClk : in STD_LOGIC;
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baudOverSampleClk : in STD_LOGIC;
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serial_in : in STD_LOGIC;
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serial_in : in STD_LOGIC;
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data_ready : out STD_LOGIC;
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data_ready : out STD_LOGIC;
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data_byte : out STD_LOGIC_VECTOR ((nBits-1) downto 0));
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data_byte : out STD_LOGIC_VECTOR ((nBits-1) downto 0));
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end component;
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end component;
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signal baud_tick : std_logic;
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signal baud_tick : std_logic;
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signal baud_tick_oversample : std_logic;
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signal baud_tick_oversample : std_logic;
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begin
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begin
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-- Instantiate baud generator
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--! Instantiate baud generator
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uBaudGen : baud_generator port map (
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uBaudGen : baud_generator port map (
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rst => rst,
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rst => rst,
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clk => clk,
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clk => clk,
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cycle_wait => cycle_wait_baud,
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cycle_wait => cycle_wait_baud,
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baud_oversample => baud_tick_oversample,
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baud_oversample => baud_tick_oversample,
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baud => baud_tick
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baud => baud_tick
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);
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);
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-- Instantiate serial_transmitter
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--! Instantiate serial_transmitter
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uTransmitter : serial_transmitter port map (
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uTransmitter : serial_transmitter port map (
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rst => not start_tx,
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rst => not start_tx,
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baudClk => baud_tick,
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baudClk => baud_tick,
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data_byte => byte_tx,
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data_byte => byte_tx,
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data_sent => data_sent_tx,
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data_sent => data_sent_tx,
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serial_out => serial_out
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serial_out => serial_out
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);
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);
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-- Instantiate serial_receiver
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--! Instantiate serial_receiver
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uReceiver : serial_receiver port map(
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uReceiver : serial_receiver port map(
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rst => rst,
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rst => rst,
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baudOverSampleClk => baud_tick_oversample,
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baudOverSampleClk => baud_tick_oversample,
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serial_in => serial_in,
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serial_in => serial_in,
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data_ready => data_received_rx,
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data_ready => data_received_rx,
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data_byte => byte_rx
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data_byte => byte_rx
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);
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);
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end Behavioral;
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end Behavioral;
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