--! uart control unit
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--! uart control unit
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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--! Use CPU Definitions package
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--! Use CPU Definitions package
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use work.pkgDefinitions.all;
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use work.pkgDefinitions.all;
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entity uart_control is
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entity uart_control is
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Port ( rst : in std_logic; -- Global reset
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Port ( rst : in std_logic; -- Global reset
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clk : in std_logic; -- Global clock
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clk : in std_logic; -- Global clock
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WE : in std_logic; -- Write enable
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WE : in std_logic; -- Write enable
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reg_addr : in std_logic_vector (1 downto 0); -- Register address
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reg_addr : in std_logic_vector (1 downto 0); -- Register address
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start : in std_logic; -- Start (Strobe)
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start : in std_logic; -- Start (Strobe)
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done : out std_logic; -- Done (ACK)
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done : out std_logic; -- Done (ACK)
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DAT_I : in std_logic_vector ((nBitsLarge-1) downto 0); -- Data Input (Wishbone)
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DAT_I : in std_logic_vector ((nBitsLarge-1) downto 0); -- Data Input (Wishbone)
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DAT_O : out std_logic_vector ((nBitsLarge-1) downto 0); -- Data output (Wishbone)
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DAT_O : out std_logic_vector ((nBitsLarge-1) downto 0); -- Data output (Wishbone)
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baud_wait : out std_logic_vector ((nBitsLarge-1) downto 0); -- Signal to control the baud rate frequency
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baud_wait : out std_logic_vector ((nBitsLarge-1) downto 0); -- Signal to control the baud rate frequency
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data_byte_tx : out std_logic_vector((nBits-1) downto 0); -- 1 Byte to be send to serial_transmitter
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data_byte_tx : out std_logic_vector((nBits-1) downto 0); -- 1 Byte to be send to serial_transmitter
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data_byte_rx : in std_logic_vector((nBits-1) downto 0); -- 1 Byte to be received by serial_receiver
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data_byte_rx : in std_logic_vector((nBits-1) downto 0); -- 1 Byte to be received by serial_receiver
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tx_data_sent : in std_logic; -- Signal comming from serial_transmitter
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tx_data_sent : in std_logic; -- Signal comming from serial_transmitter
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tx_start : out std_logic; -- Signal to start sending serial data...
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tx_start : out std_logic; -- Signal to start sending serial data...
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rst_comm_blocks : out std_logic; -- Reset Communication blocks
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rst_comm_blocks : out std_logic; -- Reset Communication blocks
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rx_data_ready : in std_logic); -- Signal comming from serial_receiver
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rx_data_ready : in std_logic); -- Signal comming from serial_receiver
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end uart_control;
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end uart_control;
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architecture Behavioral of uart_control is
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architecture Behavioral of uart_control is
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signal config_clk : std_logic_vector((nBitsLarge-1) downto 0);
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signal config_clk : std_logic_vector((nBitsLarge-1) downto 0);
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signal config_baud : std_logic_vector((nBitsLarge-1) downto 0);
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signal config_baud : std_logic_vector((nBitsLarge-1) downto 0);
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signal received_byte : std_logic_vector((nBits-1) downto 0);
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signal received_byte : std_logic_vector((nBits-1) downto 0);
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signal byte_to_transmit : std_logic_vector((nBits-1) downto 0);
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signal byte_to_transmit : std_logic_vector((nBits-1) downto 0);
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signal sigDivRst : std_logic;
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signal sigDivRst : std_logic;
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signal sigDivDone : std_logic;
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signal sigDivDone : std_logic;
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signal sigDivQuotient : std_logic_vector((nBitsLarge-1) downto 0);
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signal sigDivQuotient : std_logic_vector((nBitsLarge-1) downto 0);
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signal sigDivNumerator : std_logic_vector((nBitsLarge-1) downto 0);
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signal sigDivNumerator : std_logic_vector((nBitsLarge-1) downto 0);
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signal sigDivDividend : std_logic_vector((nBitsLarge-1) downto 0);
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signal sigDivDividend : std_logic_vector((nBitsLarge-1) downto 0);
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-- Signals used to control the configuration
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-- Signals used to control the configuration
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signal startConfigBaud : std_logic;
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signal startConfigBaud : std_logic;
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signal startConfigClk : std_logic;
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signal startConfigClk : std_logic;
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signal startDataSend : std_logic;
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signal startDataSend : std_logic;
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signal commBlocksInitiated : std_logic;
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signal commBlocksInitiated : std_logic;
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signal doneWriteReg : std_logic;
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signal startReadReg : std_logic;
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signal startReadReg : std_logic;
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signal alreadyConfBaud : std_logic;
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signal alreadyConfBaud : std_logic;
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signal alreadyConfClk : std_logic;
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signal alreadyConfClk : std_logic;
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-- Divisor component
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-- Divisor component
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component divisor is
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component divisor is
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Port ( rst : in STD_LOGIC;
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Port ( rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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clk : in STD_LOGIC;
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quotient : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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quotient : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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reminder : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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reminder : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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numerator : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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numerator : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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divident : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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divident : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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done : out STD_LOGIC);
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done : out STD_LOGIC);
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end component;
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end component;
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begin
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begin
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-- Instantiate block for calculate division
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-- Instantiate block for calculate division
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uDiv : divisor port map (
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uDiv : divisor port map (
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rst => sigDivRst,
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rst => sigDivRst,
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clk => clk,
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clk => clk,
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quotient => sigDivQuotient,
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quotient => sigDivQuotient,
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reminder => open, -- Indicates that this port will not be connected to anything
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reminder => open, -- Indicates that this port will not be connected to anything
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numerator => sigDivNumerator,
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numerator => sigDivNumerator,
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divident => sigDivDividend,
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divident => sigDivDividend,
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done => sigDivDone
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done => sigDivDone
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);
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);
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-- Process to handle the of writting the registers
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-- Process to handle the of writting the registers
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process (clk)
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process (clk)
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begin
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begin
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-- On the wishbone specification we should handle the reset synchronously
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-- On the wishbone specification we should handle the reset synchronously
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if rising_edge(clk) then
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if rising_edge(clk) then
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if rst = '1' then
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if rst = '1' then
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config_clk <= (others => '0');
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config_clk <= (others => '0');
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config_baud <= (others => '0');
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config_baud <= (others => '0');
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byte_to_transmit <= (others => '0');
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byte_to_transmit <= (others => '0');
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startConfigBaud <= '0';
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startConfigBaud <= '0';
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startConfigClk <= '0';
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startConfigClk <= '0';
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startDataSend <= '0';
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startDataSend <= '0';
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doneWriteReg <= '0';
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alreadyConfClk <= '0';
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alreadyConfClk <= '0';
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alreadyConfBaud <= '0';
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alreadyConfBaud <= '0';
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elsif (WE and start) = '1' then
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elsif (WE and start) = '1' then
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case reg_addr is
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case reg_addr is
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when "00" =>
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when "00" =>
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config_clk <= DAT_I;
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config_clk <= DAT_I;
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startConfigClk <= '1';
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startConfigClk <= '1';
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startDataSend <= '0';
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startDataSend <= '0';
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startConfigBaud <= '0';
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startConfigBaud <= '0';
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alreadyConfClk <= '1';
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alreadyConfClk <= '1';
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when "01" =>
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when "01" =>
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config_baud <= DAT_I;
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config_baud <= DAT_I;
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startConfigBaud <= '1';
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startConfigBaud <= '1';
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startDataSend <= '0';
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startDataSend <= '0';
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startConfigClk <= '0';
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startConfigClk <= '0';
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alreadyConfBaud <= '1';
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alreadyConfBaud <= '1';
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when "10" =>
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when "10" =>
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-- If we have an overrun, discard the byte
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byte_to_transmit <= DAT_I((nBits-1) downto 0);
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byte_to_transmit <= DAT_I((nBits-1) downto 0);
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startConfigBaud <= '0';
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startConfigBaud <= '0';
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startConfigClk <= '0';
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startConfigClk <= '0';
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startDataSend <= '1';
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startDataSend <= '1';
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when others =>
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when others =>
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startConfigBaud <= '0';
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startConfigBaud <= '0';
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startConfigClk <= '0';
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startConfigClk <= '0';
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startDataSend <= '0';
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startDataSend <= '0';
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end case;
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end case;
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else
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startDataSend <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- Process to handle the reading of registers
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-- Process to handle the reading of registers
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process (clk)
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process (clk)
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begin
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begin
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-- On the wishbone specification we should handle the reset synchronously
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-- On the wishbone specification we should handle the reset synchronously
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if rising_edge(clk) then
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if rising_edge(clk) then
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if rst = '1' then
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if rst = '1' then
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DAT_O <= (others => 'Z');
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DAT_O <= (others => 'Z');
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startReadReg <= '0';
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startReadReg <= '0';
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elsif ((WE = '0') and (start = '1')) then
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elsif ((WE = '0') and (start = '1')) then
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startReadReg <= '1';
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startReadReg <= '1';
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case reg_addr is
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case reg_addr is
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when "00" =>
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when "00" =>
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DAT_O <= config_clk;
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DAT_O <= config_clk;
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when "01" =>
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when "01" =>
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DAT_O <= config_baud;
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DAT_O <= config_baud;
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when "10" =>
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when "10" =>
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DAT_O <= conv_std_logic_vector(0, (nBitsLarge-nBits)) & byte_to_transmit;
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DAT_O <= conv_std_logic_vector(0, (nBitsLarge-nBits)) & byte_to_transmit;
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when "11" =>
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when "11" =>
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DAT_O <= conv_std_logic_vector(0, (nBitsLarge-nBits)) & received_byte;
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DAT_O <= conv_std_logic_vector(0, (nBitsLarge-nBits)) & received_byte;
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- Process that stores the data that comes from the serial receiver block
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-- Process that stores the data that comes from the serial receiver block
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process (rx_data_ready)
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process (rx_data_ready)
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begin
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begin
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if rising_edge(rx_data_ready) then
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if rising_edge(rx_data_ready) then
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received_byte <= data_byte_rx;
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received_byte <= data_byte_rx;
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else
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else
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received_byte <= received_byte;
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received_byte <= received_byte;
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end if;
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end if;
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end process;
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end process;
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-- Process to send data over the serial transmitter
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-- Process to send data over the serial transmitter
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process (clk)
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process (clk)
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variable cont_steps : integer range 0 to 3;
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variable sendDataStates : sendByte;
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if (rst = '1') then
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if (rst = '1') then
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cont_steps := 0;
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sendDataStates := idle;
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else
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else
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case sendDataStates is
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when idle =>
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if commBlocksInitiated = '1' and startDataSend = '1' then
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if commBlocksInitiated = '1' and startDataSend = '1' then
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case cont_steps is
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sendDataStates := prepare_byte;
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when 0 =>
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end if;
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when prepare_byte =>
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data_byte_tx <= byte_to_transmit;
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data_byte_tx <= byte_to_transmit;
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tx_start <= '0';
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tx_start <= '0';
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when 1 =>
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sendDataStates := start_sending;
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when start_sending =>
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tx_start <= '1';
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tx_start <= '1';
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when others =>
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sendDataStates := wait_completion;
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null;
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end case;
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when wait_completion =>
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if cont_steps < 3 then
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if tx_data_sent = '1' then
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cont_steps := cont_steps + 1;
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sendDataStates := idle;
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else
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cont_steps := 3;
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end if;
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end if;
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end if;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- Process to send the ACK signal, remember that optimally this ACK should be as fast as possible
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-- Process to send the ACK signal, remember that optimally this ACK should be as fast as possible
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-- to avoid locking the bus, on this case if you send a more bytes then you can transmit the ideal
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-- to avoid locking the bus, on this case if you send a more bytes then you can transmit the ideal
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-- is to create an error flag to indicate overrun.
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-- is to create an error flag to indicate overrun.
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-- On this case on any attempt of reading or writting on registers we will be lock on 1 cycle
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-- On this case on any attempt of reading or writting on registers we will be lock on 1 cycle
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process (clk, rst, startConfigBaud, startConfigClk, startDataSend, startReadReg )
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process (clk, rst, startConfigBaud, startConfigClk, startDataSend, startReadReg )
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variable joinSignal : std_logic_vector(3 downto 0);
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variable joinSignal : std_logic_vector(3 downto 0);
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variable cont_steps : integer range 0 to 3;
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variable cont_steps : integer range 0 to 3;
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if rst = '1' then
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if rst = '1' then
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done <= '1';
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done <= '1';
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cont_steps := 0;
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cont_steps := 0;
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else
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else
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joinSignal := startConfigBaud & startConfigClk & startDataSend & startReadReg;
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joinSignal := startConfigBaud & startConfigClk & startDataSend & startReadReg;
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if (joinSignal = "0000") then
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if (joinSignal = "0000") then
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done <= '1';
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done <= '1';
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else
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else
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case cont_steps is
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case cont_steps is
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when 0 =>
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when 0 =>
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if start = '1' then
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if start = '1' then
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done <= '0';
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done <= '0';
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end if;
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end if;
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when others =>
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when others =>
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done <= '1';
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done <= '1';
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end case;
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end case;
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if cont_steps < 2 then
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if cont_steps < 2 then
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cont_steps := cont_steps + 1;
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cont_steps := cont_steps + 1;
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else
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else
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cont_steps := 0;
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cont_steps := 0;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- Process to calculate the amount of cycles to wait (clock_speed / desired_baud), and initiate the board
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-- Process to calculate the amount of cycles to wait (clock_speed / desired_baud), and initiate the board
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process (startConfigBaud,startConfigClk, clk)
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process (alreadyConfClk,alreadyConfBaud, clk)
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variable cont_steps : integer range 0 to 3;
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variable cont_steps : integer range 0 to 3;
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begin
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begin
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if (alreadyConfClk and alreadyConfBaud) = '0' then
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if (alreadyConfClk and alreadyConfBaud) = '0' then
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sigDivRst <= '1';
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sigDivRst <= '1';
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cont_steps := 0;
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cont_steps := 0;
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baud_wait <= (others => '0');
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baud_wait <= (others => '0');
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commBlocksInitiated <= '0';
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commBlocksInitiated <= '0';
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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if cont_steps < 3 then
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if cont_steps < 3 then
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cont_steps := cont_steps + 1;
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cont_steps := cont_steps + 1;
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else
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else
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cont_steps := 3;
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cont_steps := 3;
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end if;
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end if;
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case cont_steps is
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case cont_steps is
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when 1 =>
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when 1 =>
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sigDivNumerator <= config_clk;
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sigDivNumerator <= config_clk;
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sigDivDividend <= config_baud;
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sigDivDividend <= config_baud;
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sigDivRst <= '1';
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sigDivRst <= '1';
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when 2 =>
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when 2 =>
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sigDivRst <= '0';
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sigDivRst <= '0';
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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-- Enable the communication block when the baud is calculated
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-- Enable the communication block when the baud is calculated
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if sigDivDone = '1' then
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if sigDivDone = '1' then
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rst_comm_blocks <= '0';
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rst_comm_blocks <= '0';
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baud_wait <= sigDivQuotient;
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baud_wait <= sigDivQuotient;
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commBlocksInitiated <= '1';
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commBlocksInitiated <= '1';
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else
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else
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baud_wait <= (others => '0');
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baud_wait <= (others => '0');
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rst_comm_blocks <= '1';
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rst_comm_blocks <= '1';
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commBlocksInitiated <= '0';
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commBlocksInitiated <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end Behavioral;
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end Behavioral;
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