-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- --
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-- --
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-- --
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-- --
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-- --
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-- --
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-- --
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-- --
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- unit name: register_rx_handler
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-- unit name: register_rx_handler
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--
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--
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-- author: Mauro Predonzani (predmauro@libero.it)
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-- author: Mauro Predonzani (predmauro@libero.it)
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-- Andrea Borga (andrea.borga@nikhef.nl)
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-- Andrea Borga (andrea.borga@nikhef.nl)
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--
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--
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-- date: 20/02/2009 $: created
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-- date: 20/02/2009 $: created
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--
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--
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-- version: $Rev 1.0 $:
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-- version: $Rev 1.0 $:
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--
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--
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-- description:
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-- description:
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--
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--
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-- the module acquires byte
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-- the module acquires byte
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-- and decodes the data as follows:
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-- and decodes the data as follows:
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--
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--
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-- -----------------------------------------------------
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-- -----------------------------------------------------
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-- | ADDRESS | DATA |
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-- | ADDRESS | DATA |
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-- -----------------------------------------------------
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-- -----------------------------------------------------
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-- | 15-08 | 07-00 | 31-24 | 23-16 | 15-08 |07-00 |
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-- | 15-08 | 07-00 | 31-24 | 23-16 | 15-08 |07-00 |
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-- | reghnd_full_add | reghnd_full_data |
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-- | reghnd_full_add | reghnd_full_data |
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-- -----------------------------------------------------
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-- -----------------------------------------------------
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-- BYTE NUM | BYTEO | BYTE1 | BYTE2 | BYTE3 | BYTE4 | BYTE5 |
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-- BYTE NUM | BYTEO | BYTE1 | BYTE2 | BYTE3 | BYTE4 | BYTE5 |
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-- -----------------------------------------------------
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-- -----------------------------------------------------
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--
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--
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-- number of register cells: 2^16
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-- number of register cells: 2^16
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-- data word lenght: 32 bits
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-- data word lenght: 32 bits
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--
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--
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--
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--
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-- dependencies: Lantronix_wrapper
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-- dependencies: uart_wrapper
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-- uart_lbus_slave
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-- uart_lbus_slave
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-- gh_uart_16550
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-- gh_uart_16550
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--
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--
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-- references: <reference one>
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-- references: <reference one>
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-- <reference two> ...
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-- <reference two> ...
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--
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--
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-- modified by: $Author:: $:
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-- modified by: $Author:: $:
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-- 04-08-2011 Andrea Borga
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-- 04-08-2011 Andrea Borga
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-- missing s_tick reset value
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-- missing s_tick reset value
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-- 18-08-2011 Andrea Borga
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-- 18-08-2011 Andrea Borga
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-- removed unused vraious v_registers
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-- removed unused vraious v_registers
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- last changes: <date> <initials> <log>
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-- last changes: <date> <initials> <log>
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-- <extended description>
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-- <extended description>
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- TODO:
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-- TODO:
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--
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--
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--
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--
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--
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--
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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|
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--=============================================================================
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--=============================================================================
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-- Libraries
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-- Libraries
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--=============================================================================
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--=============================================================================
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library ieee ;
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.std_logic_1164.all ;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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|
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--=============================================================================
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--=============================================================================
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-- Entity declaration for ada_register_handler
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-- Entity declaration for ada_register_handler
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--=============================================================================
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--=============================================================================
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entity register_rx_handler is
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entity register_rx_handler is
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port(
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port(
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reghnd_clk : in std_logic; -- system clock
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reghnd_clk : in std_logic; -- system clock
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reghnd_rst : in std_logic; -- system reset
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reghnd_rst : in std_logic; -- system reset
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reghnd_data_in : in std_logic_vector(7 downto 0); -- 8 bits fragments
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reghnd_data_in : in std_logic_vector(7 downto 0); -- 8 bits fragments
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reghnd_data_cs_rd : in std_logic; -- cs strobe of gh16550 during a read process
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reghnd_data_cs_rd : in std_logic; -- cs strobe of gh16550 during a read process
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reghnd_data_wr_rd : in std_logic; -- wr state of gh16550 during a read process
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reghnd_data_wr_rd : in std_logic; -- wr state of gh16550 during a read process
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reghnd_rd_rdy : out std_logic; -- Read data ready
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reghnd_rd_rdy : out std_logic; -- Read data ready
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reghnd_full_add : out std_logic_vector(15 downto 0); -- 16 bits RAM address
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reghnd_full_add : out std_logic_vector(15 downto 0); -- 16 bits RAM address
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reghnd_full_data : out std_logic_vector(31 downto 0); -- 32 bits RAM data
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reghnd_full_data : out std_logic_vector(31 downto 0); -- 32 bits RAM data
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reghnd_full_cs : in std_logic -- strobe data/address acquired (1 acquired - 0 not acquired)
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reghnd_full_cs : in std_logic -- strobe data/address acquired (1 acquired - 0 not acquired)
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);
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);
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end entity;
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end entity;
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--=============================================================================
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--=============================================================================
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-- architecture declaration
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-- architecture declaration
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--=============================================================================
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--=============================================================================
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architecture a of register_rx_handler is
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architecture a of register_rx_handler is
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-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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-- Components declaration
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-- Components declaration
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-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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--
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--
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-- Internal signal declaration
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-- Internal signal declaration
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--
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--
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signal s_rst : std_logic; -- global reset
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signal s_rst : std_logic; -- global reset
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signal s_clk : std_logic; -- uart to parallel interface clock
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signal s_clk : std_logic; -- uart to parallel interface clock
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|
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signal s_read_mem : std_logic; -- read data from memory
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signal s_read_mem : std_logic; -- read data from memory
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|
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signal s_write_mem : std_logic; -- write data into memory
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signal s_write_mem : std_logic; -- write data into memory
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signal v_wr_add : std_logic_vector(15 downto 0); -- full write ADDRESS
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signal v_wr_add : std_logic_vector(15 downto 0); -- full write ADDRESS
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signal v_wr_data : std_logic_vector(31 downto 0); -- full write DATA
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signal v_wr_data : std_logic_vector(31 downto 0); -- full write DATA
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|
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signal s_tick : std_logic;
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signal s_tick : std_logic;
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--
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--
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-- State Machine states
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-- State Machine states
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--
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--
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type t_reg_decoder is (IDLE, BYTE0, BYTE1, BYTE2, BYTE3, BYTE4, BYTE5, WRITE_MEM);
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type t_reg_decoder is (IDLE, BYTE0, BYTE1, BYTE2, BYTE3, BYTE4, BYTE5, WRITE_MEM);
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signal s_reg_decoder : t_reg_decoder;
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signal s_reg_decoder : t_reg_decoder;
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--=============================================================================
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--=============================================================================
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-- architecture begin
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-- architecture begin
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--=============================================================================
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--=============================================================================
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|
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begin
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begin
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|
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s_rst <= reghnd_rst;
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s_rst <= reghnd_rst;
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s_clk <= reghnd_clk;
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s_clk <= reghnd_clk;
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reghnd_rd_rdy <= s_write_mem;
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reghnd_rd_rdy <= s_write_mem;
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p_register_decoder : process(s_rst, s_clk)
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p_register_decoder : process(s_rst, s_clk)
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begin
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begin
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if s_rst = '1' then -- reset
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if s_rst = '1' then -- reset
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s_write_mem <= '0';
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s_write_mem <= '0';
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reghnd_full_add <= (others => '0');
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reghnd_full_add <= (others => '0');
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reghnd_full_data <= (others => '0');
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reghnd_full_data <= (others => '0');
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v_wr_add <= (others => '0');
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v_wr_add <= (others => '0');
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v_wr_data <= (others => '0');
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v_wr_data <= (others => '0');
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s_tick <= '0';
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s_tick <= '0';
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s_reg_decoder <= IDLE;
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s_reg_decoder <= IDLE;
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elsif Rising_edge(s_clk) then
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elsif Rising_edge(s_clk) then
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case s_reg_decoder is
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case s_reg_decoder is
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when IDLE => -- IDLE state
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when IDLE => -- IDLE state
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s_write_mem <= '0';
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s_write_mem <= '0';
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reghnd_full_add <= (others => '0');
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reghnd_full_add <= (others => '0');
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reghnd_full_data <= (others => '0');
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reghnd_full_data <= (others => '0');
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v_wr_add <= (others => '0');
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v_wr_add <= (others => '0');
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v_wr_data <= (others => '0');
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v_wr_data <= (others => '0');
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if reghnd_data_cs_rd = '1' and reghnd_data_wr_rd = '0' then -- check if BYTE0 is ready
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if reghnd_data_cs_rd = '1' and reghnd_data_wr_rd = '0' then -- check if BYTE0 is ready
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s_reg_decoder <= BYTE0;
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s_reg_decoder <= BYTE0;
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else
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else
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s_reg_decoder <= IDLE;
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s_reg_decoder <= IDLE;
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s_tick <= '0';
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s_tick <= '0';
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end if;
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end if;
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when BYTE0 => -- decode byte 0 ADDRESS upper
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when BYTE0 => -- decode byte 0 ADDRESS upper
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s_write_mem <= '0';
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s_write_mem <= '0';
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if s_tick = '0' then -- only first time in this cycle acq the byte
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if s_tick = '0' then -- only first time in this cycle acq the byte
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v_wr_add (15 downto 8) <= reghnd_data_in;
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v_wr_add (15 downto 8) <= reghnd_data_in;
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s_tick <= '1';
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s_tick <= '1';
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elsif reghnd_data_cs_rd = '1' and reghnd_data_wr_rd = '0' then -- check if BYTE1 is ready
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elsif reghnd_data_cs_rd = '1' and reghnd_data_wr_rd = '0' then -- check if BYTE1 is ready
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s_reg_decoder <= BYTE1;
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s_reg_decoder <= BYTE1;
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s_tick <= '0';
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s_tick <= '0';
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else
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else
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s_reg_decoder <= BYTE0;
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s_reg_decoder <= BYTE0;
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s_tick <= '1';
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s_tick <= '1';
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end if;
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end if;
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when BYTE1 => -- decode byte 1 ADDRESS lower
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when BYTE1 => -- decode byte 1 ADDRESS lower
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s_write_mem <= '0';
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s_write_mem <= '0';
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if s_tick = '0' then -- only first time in this cycle acq the byte
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if s_tick = '0' then -- only first time in this cycle acq the byte
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v_wr_add (7 downto 0) <= reghnd_data_in;
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v_wr_add (7 downto 0) <= reghnd_data_in;
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s_tick <= '1';
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s_tick <= '1';
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elsif reghnd_data_cs_rd = '1' and reghnd_data_wr_rd = '0' then -- check if BYTE2 is ready
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elsif reghnd_data_cs_rd = '1' and reghnd_data_wr_rd = '0' then -- check if BYTE2 is ready
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s_reg_decoder <= BYTE2;
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s_reg_decoder <= BYTE2;
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s_tick <= '0';
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s_tick <= '0';
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else
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else
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s_reg_decoder <= BYTE1;
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s_reg_decoder <= BYTE1;
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s_tick <= '1';
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s_tick <= '1';
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end if;
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end if;
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when BYTE2 => -- decode byte 2 = DATA1
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when BYTE2 => -- decode byte 2 = DATA1
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s_write_mem <= '0';
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s_write_mem <= '0';
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if s_tick = '0' then -- only first time in this cycle acq the byte
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if s_tick = '0' then -- only first time in this cycle acq the byte
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v_wr_data (31 downto 24) <= reghnd_data_in;
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v_wr_data (31 downto 24) <= reghnd_data_in;
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s_tick <= '1';
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s_tick <= '1';
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elsif reghnd_data_cs_rd = '1' and reghnd_data_wr_rd = '0' then -- check if BYTE3 is ready
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elsif reghnd_data_cs_rd = '1' and reghnd_data_wr_rd = '0' then -- check if BYTE3 is ready
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s_reg_decoder <= BYTE3;
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s_reg_decoder <= BYTE3;
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s_tick <= '0';
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s_tick <= '0';
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else
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else
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s_reg_decoder <= BYTE2;
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s_reg_decoder <= BYTE2;
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s_tick <= '1';
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s_tick <= '1';
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end if;
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end if;
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when BYTE3 => -- decode byte 3 = DATA2
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when BYTE3 => -- decode byte 3 = DATA2
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s_write_mem <= '0';
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s_write_mem <= '0';
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if s_tick = '0' then -- only first time in this cycle acq the byte
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if s_tick = '0' then -- only first time in this cycle acq the byte
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v_wr_data (23 downto 16) <= reghnd_data_in;
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v_wr_data (23 downto 16) <= reghnd_data_in;
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s_tick <= '1';
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s_tick <= '1';
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elsif reghnd_data_cs_rd = '1' and reghnd_data_wr_rd = '0' then -- check if BYTE4 is ready
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elsif reghnd_data_cs_rd = '1' and reghnd_data_wr_rd = '0' then -- check if BYTE4 is ready
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s_reg_decoder <= BYTE4;
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s_reg_decoder <= BYTE4;
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s_tick <= '0';
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s_tick <= '0';
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else
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else
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s_reg_decoder <= BYTE3;
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s_reg_decoder <= BYTE3;
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s_tick <= '1';
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s_tick <= '1';
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end if;
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end if;
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when BYTE4 => -- decode byte 4 = DATA3
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when BYTE4 => -- decode byte 4 = DATA3
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s_write_mem <= '0';
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s_write_mem <= '0';
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if s_tick = '0' then -- only first time in this cycle acq the byte
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if s_tick = '0' then -- only first time in this cycle acq the byte
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v_wr_data (15 downto 8) <= reghnd_data_in;
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v_wr_data (15 downto 8) <= reghnd_data_in;
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s_tick <= '1';
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s_tick <= '1';
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elsif reghnd_data_cs_rd = '1' and reghnd_data_wr_rd = '0' then -- check if BYTE5 is ready
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elsif reghnd_data_cs_rd = '1' and reghnd_data_wr_rd = '0' then -- check if BYTE5 is ready
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s_reg_decoder <= BYTE5;
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s_reg_decoder <= BYTE5;
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s_tick <= '0';
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s_tick <= '0';
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else
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else
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s_reg_decoder <= BYTE4;
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s_reg_decoder <= BYTE4;
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s_tick <= '1';
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s_tick <= '1';
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end if;
|
end if;
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when BYTE5 => -- decode byte 5 = DATA4
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when BYTE5 => -- decode byte 5 = DATA4
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s_write_mem <= '0';
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s_write_mem <= '0';
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if s_tick = '0' then -- only first time in this cycle acq the byte
|
if s_tick = '0' then -- only first time in this cycle acq the byte
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v_wr_data (7 downto 0) <= reghnd_data_in;
|
v_wr_data (7 downto 0) <= reghnd_data_in;
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s_tick <= '1';
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s_tick <= '1';
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else -- add and data are ready => ready to use
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else -- add and data are ready => ready to use
|
s_reg_decoder <= WRITE_MEM;
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s_reg_decoder <= WRITE_MEM;
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s_tick <= '0';
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s_tick <= '0';
|
reghnd_full_add <= v_wr_add; -- address latch to the ouput
|
reghnd_full_add <= v_wr_add; -- address latch to the ouput
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reghnd_full_data <= v_wr_data; -- data latch to the output
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reghnd_full_data <= v_wr_data; -- data latch to the output
|
end if;
|
end if;
|
when WRITE_MEM => -- write data into RAM
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when WRITE_MEM => -- write data into RAM
|
s_write_mem <= '1'; -- data and address stable and ready
|
s_write_mem <= '1'; -- data and address stable and ready
|
if reghnd_full_cs = '1' then -- check if data is transfer to RAM or not
|
if reghnd_full_cs = '1' then -- check if data is transfer to RAM or not
|
s_reg_decoder <= IDLE;
|
s_reg_decoder <= IDLE;
|
else
|
else
|
s_reg_decoder <= WRITE_MEM;
|
s_reg_decoder <= WRITE_MEM;
|
end if;
|
end if;
|
when others =>
|
when others =>
|
s_reg_decoder <= IDLE;
|
s_reg_decoder <= IDLE;
|
end case;
|
end case;
|
end if;
|
end if;
|
end process p_register_decoder;
|
end process p_register_decoder;
|
|
|
|
|
end a;
|
end a;
|
|
|
--=============================================================================
|
--=============================================================================
|
-- architecture end
|
-- architecture end
|
--=============================================================================
|
--=============================================================================
|
|
|
