--
|
--
|
-- unit name: ab_top (Register map access)
|
-- unit name: ab_top (Register map access)
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--
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--
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-- author: Andrea Borga (andrea.borga@nikhef.nl)
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-- author: Andrea Borga (andrea.borga@nikhef.nl)
|
--
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--
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--
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--
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-- date: $26/08/2011 $: created
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-- date: $26/08/2011 $: created
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--
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--
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-- version: $Rev 0 $:
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-- version: $Rev 0 $:
|
--
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--
|
-- description:
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-- description:
|
-- NOTE: look through the code for this
|
-- NOTE: look through the code for this
|
--
|
--
|
-- -- #####################
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-- -- #####################
|
-- -- #####################
|
-- -- #####################
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--
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--
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-- to spot where the code needs customization
|
-- to spot where the code needs customization
|
--
|
--
|
-- dependencies:
|
-- dependencies:
|
-- gh_uart_16550
|
-- gh_uart_16550
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-- ab_uart_lbus_slave
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-- ab_uart_lbus_slave
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-- ab_uart_16550_wrapper
|
-- ab_uart_16550_wrapper
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-- ab_register_rx_handler
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-- ab_register_rx_handler
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-- ab_register_tx_handler
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-- ab_register_tx_handler
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--
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--
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-- references: <reference one>
|
-- references: <reference one>
|
-- <reference two> ...
|
-- <reference two> ...
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--
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--
|
-- modified by: $Author:: $:
|
-- modified by: $Author:: $:
|
--
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--
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--
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--
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
|
-- last changes: <date> <initials> <log>
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-- last changes: <date> <initials> <log>
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-- <extended description>
|
-- <extended description>
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- TODO:
|
-- TODO:
|
--
|
--
|
--
|
--
|
--
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--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
--=============================================================================
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--=============================================================================
|
-- Libraries
|
-- Libraries
|
--=============================================================================
|
--=============================================================================
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|
|
library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
|
|
|
--=============================================================================
|
--=============================================================================
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-- Entity declaration for ab_top
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-- Entity declaration for ab_top
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--=============================================================================
|
--=============================================================================
|
|
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entity ab_top is
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entity ab_top is
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port(
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port(
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clk_uart_29MHz_i : in std_logic;
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clk_uart_29MHz_i : in std_logic;
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uart_rst_i : in std_logic;
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uart_rst_i : in std_logic;
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uart_leds_o : out std_logic_vector(7 downto 0);
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uart_leds_o : out std_logic_vector(7 downto 0);
|
clk_uart_monitor_o : out std_logic;
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clk_uart_monitor_o : out std_logic;
|
-- #####################
|
-- #####################
|
-- ADD your registers toward the rest of the logic here
|
-- ADD your registers toward the rest of the logic here
|
-- #####################
|
-- #####################
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uart_din_o : out std_logic;
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uart_din_o : out std_logic;
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uart_dout_i : in std_logic);
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uart_dout_i : in std_logic);
|
|
|
end ab_top;
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end ab_top;
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|
|
|
|
--=============================================================================
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--=============================================================================
|
-- architecture declaration
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-- architecture declaration
|
--=============================================================================
|
--=============================================================================
|
|
|
architecture a0 of ab_top is
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architecture a0 of ab_top is
|
|
|
component uart_16550_wrapper
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component uart_16550_wrapper
|
port(
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port(
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-- general purpose
|
-- general purpose
|
sys_clk_i : in std_logic; -- system clock
|
sys_clk_i : in std_logic; -- system clock
|
sys_rst_i : in std_logic; -- system reset
|
sys_rst_i : in std_logic; -- system reset
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-- TX/RX process command line
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-- TX/RX process command line
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echo_en_i : in std_logic; -- Echo enable (byte by byte) enable/disable = 1/0
|
echo_en_i : in std_logic; -- Echo enable (byte by byte) enable/disable = 1/0
|
tx_addr_wwo_i : in std_logic; -- control of TX process With or WithOut address W/WO=(1/0)
|
tx_addr_wwo_i : in std_logic; -- control of TX process With or WithOut address W/WO=(1/0)
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-- serial I/O side
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-- serial I/O side
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lantronix_output_i : in std_logic; -- Lantronix Serial data OUTPUT signal
|
uart_din_i : in std_logic; -- Serial data INPUT signal (from the FPGA)
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lantronix_input_o : out std_logic; -- Lantronix Serial data INPUT signal
|
uart_dout_o : out std_logic; -- Serial data OUTPUT signal (to the FPGA)
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cp_b : inout std_logic_vector(2 downto 0); -- general purpose IO pins
|
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-- parallel I/O side
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-- parallel I/O side
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s_br_clk_uart_o : out std_logic; -- br_clk clock probe signal
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s_br_clk_uart_o : out std_logic; -- br_clk clock probe signal
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-- RX part/control
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-- RX part/control
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v_rx_add_o : out std_logic_vector(15 downto 0); -- 16 bits full addr ram input
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v_rx_add_o : out std_logic_vector(15 downto 0); -- 16 bits full addr ram input
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v_rx_data_o : out std_logic_vector(31 downto 0); -- 32 bits full data ram input
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v_rx_data_o : out std_logic_vector(31 downto 0); -- 32 bits full data ram input
|
s_rx_rdy_o : out std_logic; -- add/data ready to be write into RAM
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s_rx_rdy_o : out std_logic; -- add/data ready to be write into RAM
|
s_rx_stb_read_data_i : in std_logic; -- strobe signal from RAM ...
|
s_rx_stb_read_data_i : in std_logic; -- strobe signal from RAM ...
|
-- TX part/control
|
-- TX part/control
|
s_tx_proc_rqst_i : in std_logic; -- stream TX process request 1/0 tx enable/disable
|
s_tx_proc_rqst_i : in std_logic; -- stream TX process request 1/0 tx enable/disable
|
v_tx_add_ram_i : in std_logic_vector(15 downto 0); -- 16 bits full addr ram output
|
v_tx_add_ram_i : in std_logic_vector(15 downto 0); -- 16 bits full addr ram output
|
v_tx_data_ram_i : in std_logic_vector(31 downto 0); -- 32 bits full data ram output
|
v_tx_data_ram_i : in std_logic_vector(31 downto 0); -- 32 bits full data ram output
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s_tx_ram_data_rdy_i : in std_logic; -- ram output data ready and stable
|
s_tx_ram_data_rdy_i : in std_logic; -- ram output data ready and stable
|
s_tx_stb_ram_data_acq_o : out std_logic -- strobe ram data/address output acquired 1/0 acquired/not acquired
|
s_tx_stb_ram_data_acq_o : out std_logic -- strobe ram data/address output acquired 1/0 acquired/not acquired
|
);
|
);
|
end component;
|
end component;
|
|
|
--
|
--
|
-- Internal signal declaration
|
-- Internal signal declaration
|
--
|
--
|
|
|
-- generic signals
|
-- generic signals
|
signal s_rst : std_logic; -- main reset
|
signal s_rst : std_logic; -- main reset
|
signal s_clk_uart : std_logic; -- slow (29 MHz) clock
|
signal s_clk_uart : std_logic; -- slow (29 MHz) clock
|
|
|
-- uart control signals
|
-- uart control signals
|
signal s_uart_cp : std_logic_vector (2 downto 0); -- unused
|
|
signal s_uart_br_clk : std_logic; -- unused clock monitor
|
signal s_uart_br_clk : std_logic; -- unused clock monitor
|
signal s_uart_rx_add : std_logic_vector (15 downto 0);
|
signal s_uart_rx_add : std_logic_vector (15 downto 0);
|
signal s_uart_rx_data : std_logic_vector (31 downto 0);
|
signal s_uart_rx_data : std_logic_vector (31 downto 0);
|
signal s_uart_rx_rdy : std_logic;
|
signal s_uart_rx_rdy : std_logic;
|
signal s_uart_rx_stb_read_data : std_logic;
|
signal s_uart_rx_stb_read_data : std_logic;
|
signal s_update : std_logic;
|
signal s_update : std_logic;
|
signal s_uart_tx_add : std_logic_vector (15 downto 0);
|
signal s_uart_tx_add : std_logic_vector (15 downto 0);
|
signal s_uart_tx_data : std_logic_vector (31 downto 0);
|
signal s_uart_tx_data : std_logic_vector (31 downto 0);
|
signal s_uart_tx_data_rdy : std_logic;
|
signal s_uart_tx_data_rdy : std_logic;
|
signal s_uart_tx_req : std_logic;
|
signal s_uart_tx_req : std_logic;
|
signal s_uart_tx_stb_acq : std_logic;
|
signal s_uart_tx_stb_acq : std_logic;
|
signal s_tx_complete : std_logic;
|
signal s_tx_complete : std_logic;
|
|
|
|
|
-- address decoder signals
|
-- address decoder signals
|
|
|
signal r_config_addr_uart : std_logic_vector (1 downto 0);
|
signal r_config_addr_uart : std_logic_vector (1 downto 0);
|
signal r_open : std_logic_vector (31 downto 0);
|
signal r_open : std_logic_vector (31 downto 0);
|
signal r_leds : std_logic_vector (7 downto 0);
|
signal r_leds : std_logic_vector (7 downto 0);
|
signal r_test_reg01 : std_logic_vector (31 downto 0);
|
signal r_test_reg01 : std_logic_vector (31 downto 0);
|
signal r_test_reg02 : std_logic_vector (31 downto 0);
|
signal r_test_reg02 : std_logic_vector (31 downto 0);
|
signal r_test_reg03 : std_logic_vector (31 downto 0);
|
signal r_test_reg03 : std_logic_vector (31 downto 0);
|
signal r_test_reg04 : std_logic_vector (31 downto 0);
|
signal r_test_reg04 : std_logic_vector (31 downto 0);
|
signal r_test_reg05 : std_logic_vector (31 downto 0);
|
signal r_test_reg05 : std_logic_vector (31 downto 0);
|
-- #####################
|
-- #####################
|
-- declare your registers here
|
-- declare your registers here
|
-- #####################
|
-- #####################
|
|
|
--
|
--
|
-- State Machine states
|
-- State Machine states
|
--
|
--
|
|
|
type t_tx_reg_map is (IDLE, WAIT_A_BYTE, LATCH, TRANSMIT);
|
type t_tx_reg_map is (IDLE, WAIT_A_BYTE, LATCH, TRANSMIT);
|
signal s_tx_fsm : t_tx_reg_map;
|
signal s_tx_fsm : t_tx_reg_map;
|
|
|
begin
|
begin
|
|
|
s_rst <= not uart_rst_i;
|
s_rst <= not uart_rst_i;
|
|
|
uart_leds_o <= r_leds; -- Let there be light ...
|
uart_leds_o <= r_leds; -- Let there be light ...
|
|
|
-- UART simple register map
|
-- UART simple register map
|
register_map : process (s_rst, s_clk_uart)
|
register_map : process (s_rst, s_clk_uart)
|
begin
|
begin
|
if s_rst = '1' then -- reset all registers here
|
if s_rst = '1' then -- reset all registers here
|
s_uart_rx_stb_read_data <= '0';
|
s_uart_rx_stb_read_data <= '0';
|
s_update <= '0';
|
s_update <= '0';
|
r_leds <= (others => '0');
|
r_leds <= (others => '0');
|
r_config_addr_uart <= "10";
|
r_config_addr_uart <= "10";
|
r_test_reg01 <= (others => '0');
|
r_test_reg01 <= (others => '0');
|
r_test_reg02 <= (others => '0');
|
r_test_reg02 <= (others => '0');
|
r_test_reg03 <= (others => '0');
|
r_test_reg03 <= (others => '0');
|
r_test_reg04 <= (others => '0');
|
r_test_reg04 <= (others => '0');
|
r_test_reg05 <= (others => '0');
|
r_test_reg05 <= (others => '0');
|
-- #####################
|
-- #####################
|
-- reset your registers here
|
-- reset your registers here
|
-- #####################
|
-- #####################
|
elsif rising_edge(s_clk_uart) then
|
elsif rising_edge(s_clk_uart) then
|
if s_uart_rx_rdy = '1' then
|
if s_uart_rx_rdy = '1' then
|
case (s_uart_rx_add) is
|
case (s_uart_rx_add) is
|
when X"0020" => r_leds <= s_uart_rx_data(7 downto 0);
|
when X"0020" => r_leds <= s_uart_rx_data(7 downto 0);
|
-- #####################
|
-- #####################
|
-- declare more registers here to WRITE
|
-- declare more registers here to WRITE
|
-- #####################
|
-- #####################
|
when X"0030" => r_test_reg03 <= s_uart_rx_data;
|
when X"0030" => r_test_reg03 <= s_uart_rx_data;
|
when X"0031" => r_test_reg04 <= s_uart_rx_data;
|
when X"0031" => r_test_reg04 <= s_uart_rx_data;
|
when X"0032" => r_test_reg05 <= s_uart_rx_data;
|
when X"0032" => r_test_reg05 <= s_uart_rx_data;
|
when X"0040" => r_test_reg01 <= s_uart_rx_data;
|
when X"0040" => r_test_reg01 <= s_uart_rx_data;
|
when X"0050" => r_test_reg02 <= s_uart_rx_data;
|
when X"0050" => r_test_reg02 <= s_uart_rx_data;
|
when X"8000" => s_update <= '1'; -- register update self clearing
|
when X"8000" => s_update <= '1'; -- register update self clearing
|
when others => r_open <= s_uart_rx_data;
|
when others => r_open <= s_uart_rx_data;
|
end case;
|
end case;
|
s_uart_rx_stb_read_data <= '1';
|
s_uart_rx_stb_read_data <= '1';
|
else
|
else
|
s_uart_rx_stb_read_data <= '0';
|
s_uart_rx_stb_read_data <= '0';
|
s_update <= '0';
|
s_update <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
register_update : process (s_rst, s_clk_uart)
|
register_update : process (s_rst, s_clk_uart)
|
variable v_uart_tx_add : unsigned (15 downto 0);
|
variable v_uart_tx_add : unsigned (15 downto 0);
|
variable v_count : unsigned (15 downto 0);
|
variable v_count : unsigned (15 downto 0);
|
begin
|
begin
|
if s_rst = '1' then -- reset all registers here
|
if s_rst = '1' then -- reset all registers here
|
s_uart_tx_data_rdy <= '0';
|
s_uart_tx_data_rdy <= '0';
|
s_uart_tx_req <= '0';
|
s_uart_tx_req <= '0';
|
v_uart_tx_add := (others => '0');
|
v_uart_tx_add := (others => '0');
|
v_count := (others => '0');
|
v_count := (others => '0');
|
s_uart_tx_data <= (others => '0');
|
s_uart_tx_data <= (others => '0');
|
s_uart_tx_add <= (others => '0');
|
s_uart_tx_add <= (others => '0');
|
-- #####################
|
-- #####################
|
-- reset your registers here
|
-- reset your registers here
|
-- #####################
|
-- #####################
|
s_tx_fsm <= IDLE;
|
s_tx_fsm <= IDLE;
|
elsif rising_edge(s_clk_uart) then
|
elsif rising_edge(s_clk_uart) then
|
case s_tx_fsm is
|
case s_tx_fsm is
|
when IDLE =>
|
when IDLE =>
|
if s_update = '1' then
|
if s_update = '1' then
|
s_tx_fsm <= WAIT_A_BYTE;
|
s_tx_fsm <= WAIT_A_BYTE;
|
else
|
else
|
s_tx_fsm <= IDLE;
|
s_tx_fsm <= IDLE;
|
s_uart_tx_data_rdy <= '0';
|
s_uart_tx_data_rdy <= '0';
|
s_uart_tx_req <= '0';
|
s_uart_tx_req <= '0';
|
v_uart_tx_add := (others => '0');
|
v_uart_tx_add := (others => '0');
|
v_count := (others => '0');
|
v_count := (others => '0');
|
s_uart_tx_data <= (others => '0');
|
s_uart_tx_data <= (others => '0');
|
s_uart_tx_add <= (others => '0');
|
s_uart_tx_add <= (others => '0');
|
end if;
|
end if;
|
when WAIT_A_BYTE =>
|
when WAIT_A_BYTE =>
|
s_uart_tx_data_rdy <= '0';
|
s_uart_tx_data_rdy <= '0';
|
v_count := v_count + 1;
|
v_count := v_count + 1;
|
if v_count = X"0900" then
|
if v_count = X"0900" then
|
v_uart_tx_add := v_uart_tx_add + 1;
|
v_uart_tx_add := v_uart_tx_add + 1;
|
s_tx_fsm <= LATCH;
|
s_tx_fsm <= LATCH;
|
else
|
else
|
s_tx_fsm <= WAIT_A_BYTE;
|
s_tx_fsm <= WAIT_A_BYTE;
|
end if;
|
end if;
|
when LATCH =>
|
when LATCH =>
|
if s_uart_tx_stb_acq = '0' then
|
if s_uart_tx_stb_acq = '0' then
|
s_uart_tx_req <= '1';
|
s_uart_tx_req <= '1';
|
s_uart_tx_add <= std_logic_vector (v_uart_tx_add);
|
s_uart_tx_add <= std_logic_vector (v_uart_tx_add);
|
case v_uart_tx_add is
|
case v_uart_tx_add is
|
when X"0001" => s_uart_tx_data <= (others => '0'); -- reserved synch register
|
when X"0001" => s_uart_tx_data <= (others => '0'); -- reserved synch register
|
s_tx_fsm <= TRANSMIT;
|
s_tx_fsm <= TRANSMIT;
|
-- #####################
|
-- #####################
|
-- declare more registers here to READ
|
-- declare more registers here to READ
|
-- #####################
|
-- #####################
|
when X"0010" => s_uart_tx_data <= (others => '0');
|
when X"0010" => s_uart_tx_data <= (others => '0');
|
s_tx_fsm <= TRANSMIT;
|
s_tx_fsm <= TRANSMIT;
|
when X"0011" => s_uart_tx_data <= (others => '0');
|
when X"0011" => s_uart_tx_data <= (others => '0');
|
s_tx_fsm <= TRANSMIT;
|
s_tx_fsm <= TRANSMIT;
|
when X"0020" => s_uart_tx_data (7 downto 0) <= r_leds;
|
when X"0020" => s_uart_tx_data (7 downto 0) <= r_leds;
|
s_tx_fsm <= TRANSMIT;
|
s_tx_fsm <= TRANSMIT;
|
when X"0030" => s_uart_tx_data <= r_test_reg03;
|
when X"0030" => s_uart_tx_data <= r_test_reg03;
|
s_tx_fsm <= TRANSMIT;
|
s_tx_fsm <= TRANSMIT;
|
when X"0031" => s_uart_tx_data <= r_test_reg04;
|
when X"0031" => s_uart_tx_data <= r_test_reg04;
|
s_tx_fsm <= TRANSMIT;
|
s_tx_fsm <= TRANSMIT;
|
when X"0032" => s_uart_tx_data <= r_test_reg05;
|
when X"0032" => s_uart_tx_data <= r_test_reg05;
|
s_tx_fsm <= TRANSMIT;
|
s_tx_fsm <= TRANSMIT;
|
when X"0040" => s_uart_tx_data <= r_test_reg01;
|
when X"0040" => s_uart_tx_data <= r_test_reg01;
|
s_tx_fsm <= TRANSMIT;
|
s_tx_fsm <= TRANSMIT;
|
when X"0050" => s_uart_tx_data <= r_test_reg02;
|
when X"0050" => s_uart_tx_data <= r_test_reg02;
|
s_tx_fsm <= TRANSMIT;
|
s_tx_fsm <= TRANSMIT;
|
-- End Of Transmission register = last register + 1
|
-- End Of Transmission register = last register + 1
|
when X"0051" => s_tx_fsm <= IDLE; -- end of transmission
|
when X"0051" => s_tx_fsm <= IDLE; -- end of transmission
|
when others => s_uart_tx_data <= (others => '0');
|
when others => s_uart_tx_data <= (others => '0');
|
v_uart_tx_add := v_uart_tx_add + 1;
|
v_uart_tx_add := v_uart_tx_add + 1;
|
s_uart_tx_data_rdy <= '0';
|
s_uart_tx_data_rdy <= '0';
|
s_tx_fsm <= LATCH;
|
s_tx_fsm <= LATCH;
|
end case;
|
end case;
|
else
|
else
|
v_count := (others => '0');
|
v_count := (others => '0');
|
s_tx_fsm <= WAIT_A_BYTE;
|
s_tx_fsm <= WAIT_A_BYTE;
|
end if;
|
end if;
|
when TRANSMIT =>
|
when TRANSMIT =>
|
s_uart_tx_data_rdy <= '1';
|
s_uart_tx_data_rdy <= '1';
|
v_count := (others => '0');
|
v_count := (others => '0');
|
s_tx_fsm <= WAIT_A_BYTE;
|
s_tx_fsm <= WAIT_A_BYTE;
|
when others =>
|
when others =>
|
s_tx_fsm <= IDLE;
|
s_tx_fsm <= IDLE;
|
end case;
|
end case;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
s_clk_uart <= clk_uart_29MHz_i; -- UART system clock 29.4912 MHz
|
s_clk_uart <= clk_uart_29MHz_i; -- UART system clock 29.4912 MHz
|
clk_uart_monitor_o <= s_uart_br_clk;
|
clk_uart_monitor_o <= s_uart_br_clk;
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uart_wrapper : uart_16550_wrapper
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uart_wrapper : uart_16550_wrapper
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port map(
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port map(
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sys_clk_i => s_clk_uart,
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sys_clk_i => s_clk_uart,
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sys_rst_i => s_rst,
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sys_rst_i => s_rst,
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echo_en_i => r_config_addr_uart(0),
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echo_en_i => r_config_addr_uart(0),
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tx_addr_wwo_i => r_config_addr_uart(1),
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tx_addr_wwo_i => r_config_addr_uart(1),
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lantronix_output_i => uart_dout_i,
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uart_dout_i => uart_dout_i,
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lantronix_input_o => uart_din_o,
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uart_din_o => uart_din_o,
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cp_b => s_uart_cp,
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s_br_clk_uart_o => s_uart_br_clk,
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s_br_clk_uart_o => s_uart_br_clk,
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v_rx_add_o => s_uart_rx_add,
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v_rx_add_o => s_uart_rx_add,
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v_rx_data_o => s_uart_rx_data,
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v_rx_data_o => s_uart_rx_data,
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s_rx_rdy_o => s_uart_rx_rdy,
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s_rx_rdy_o => s_uart_rx_rdy,
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s_rx_stb_read_data_i => s_uart_rx_stb_read_data,
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s_rx_stb_read_data_i => s_uart_rx_stb_read_data,
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s_tx_proc_rqst_i => s_uart_tx_req,
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s_tx_proc_rqst_i => s_uart_tx_req,
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v_tx_add_ram_i => s_uart_tx_add,
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v_tx_add_ram_i => s_uart_tx_add,
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v_tx_data_ram_i => s_uart_tx_data,
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v_tx_data_ram_i => s_uart_tx_data,
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s_tx_ram_data_rdy_i => s_uart_tx_data_rdy,
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s_tx_ram_data_rdy_i => s_uart_tx_data_rdy,
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s_tx_stb_ram_data_acq_o => s_uart_tx_stb_acq
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s_tx_stb_ram_data_acq_o => s_uart_tx_stb_acq
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);
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);
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|
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end architecture a0 ; -- of UART_control
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end architecture a0 ; -- of UART_control
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