----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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-- Company:
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-- Company:
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-- Engineer: Peter Fall
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-- Engineer: Peter Fall
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--
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--
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-- Create Date: 5 June 2011
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-- Create Date: 5 June 2011
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-- Design Name:
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-- Design Name:
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-- Module Name: UDP_RX - Behavioral
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-- Module Name: UDP_RX - Behavioral
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-- Project Name:
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-- Project Name:
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-- Target Devices:
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-- Target Devices:
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-- Tool versions:
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-- Tool versions:
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-- Description:
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-- Description:
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-- handle simple UDP RX
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-- handle simple UDP RX
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-- doesnt check the checsum
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-- doesnt check the checsum
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-- Dependencies:
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-- Dependencies:
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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-- Revision 0.02 - Improved error handling
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-- Revision 0.02 - Improved error handling
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-- Additional Comments:
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-- Additional Comments:
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--
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.axi.all;
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use work.axi.all;
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use work.ipv4_types.all;
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use work.ipv4_types.all;
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|
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entity UDP_RX is
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entity UDP_RX is
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Port (
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Port (
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-- UDP Layer signals
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-- UDP Layer signals
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udp_rx_start : out std_logic; -- indicates receipt of udp header
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udp_rx_start : out std_logic; -- indicates receipt of udp header
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udp_rxo : out udp_rx_type;
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udp_rxo : out udp_rx_type;
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-- system signals
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-- system signals
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clk : in STD_LOGIC;
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clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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reset : in STD_LOGIC;
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-- IP layer RX signals
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-- IP layer RX signals
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ip_rx_start : in std_logic; -- indicates receipt of ip header
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ip_rx_start : in std_logic; -- indicates receipt of ip header
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ip_rx : in ipv4_rx_type
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ip_rx : in ipv4_rx_type
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);
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);
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end UDP_RX;
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end UDP_RX;
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|
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architecture Behavioral of UDP_RX is
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architecture Behavioral of UDP_RX is
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|
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type rx_state_type is (IDLE, UDP_HDR, USER_DATA, WAIT_END, ERR);
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type rx_state_type is (IDLE, UDP_HDR, USER_DATA, WAIT_END, ERR);
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|
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type rx_event_type is (NO_EVENT,DATA);
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type rx_event_type is (NO_EVENT,DATA);
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type count_mode_type is (RST, INCR, HOLD);
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type count_mode_type is (RST, INCR, HOLD);
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type settable_count_mode_type is (RST, INCR, SET_VAL, HOLD);
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type settable_count_mode_type is (RST, INCR, SET_VAL, HOLD);
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type set_clr_type is (SET, CLR, HOLD);
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type set_clr_type is (SET, CLR, HOLD);
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|
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-- state variables
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-- state variables
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signal rx_state : rx_state_type;
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signal rx_state : rx_state_type;
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signal rx_count : unsigned (15 downto 0);
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signal rx_count : unsigned (15 downto 0);
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signal src_port : std_logic_vector (15 downto 0); -- src port captured from input
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signal src_port : std_logic_vector (15 downto 0); -- src port captured from input
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signal dst_port : std_logic_vector (15 downto 0); -- dst port captured from input
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signal dst_port : std_logic_vector (15 downto 0); -- dst port captured from input
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signal data_len : std_logic_vector (15 downto 0); -- user data length captured from input
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signal data_len : std_logic_vector (15 downto 0); -- user data length captured from input
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signal udp_rx_start_reg : std_logic; -- indicates start of user data
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signal udp_rx_start_reg : std_logic; -- indicates start of user data
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signal hdr_valid_reg : std_logic; -- indicates that hdr data is valid
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signal hdr_valid_reg : std_logic; -- indicates that hdr data is valid
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signal src_ip_addr : std_logic_vector (31 downto 0); -- captured from IP hdr
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signal src_ip_addr : std_logic_vector (31 downto 0); -- captured from IP hdr
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|
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-- rx control signals
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-- rx control signals
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signal next_rx_state : rx_state_type;
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signal next_rx_state : rx_state_type;
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signal set_rx_state : std_logic;
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signal set_rx_state : std_logic;
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signal rx_event : rx_event_type;
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signal rx_event : rx_event_type;
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signal rx_count_mode : settable_count_mode_type;
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signal rx_count_mode : settable_count_mode_type;
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signal rx_count_val : unsigned (15 downto 0);
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signal rx_count_val : unsigned (15 downto 0);
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signal set_sph : std_logic;
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signal set_sph : std_logic;
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signal set_spl : std_logic;
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signal set_spl : std_logic;
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signal set_dph : std_logic;
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signal set_dph : std_logic;
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signal set_dpl : std_logic;
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signal set_dpl : std_logic;
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signal set_len_H : std_logic;
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signal set_len_H : std_logic;
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signal set_len_L : std_logic;
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signal set_len_L : std_logic;
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signal set_udp_rx_start : set_clr_type;
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signal set_udp_rx_start : set_clr_type;
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signal set_hdr_valid : set_clr_type;
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signal set_hdr_valid : set_clr_type;
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signal dataval : std_logic_vector (7 downto 0);
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signal dataval : std_logic_vector (7 downto 0);
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signal set_pkt_cnt : count_mode_type;
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signal set_pkt_cnt : count_mode_type;
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signal set_src_ip : std_logic;
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signal set_src_ip : std_logic;
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signal set_data_last : std_logic;
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signal set_data_last : std_logic;
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|
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-- IP datagram header format
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-- IP datagram header format
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--
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--
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-- 0 4 8 16 19 24 31
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-- 0 4 8 16 19 24 31
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-- --------------------------------------------------------------------------------------------
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-- --------------------------------------------------------------------------------------------
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-- | source port number | dest port number |
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-- | source port number | dest port number |
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-- | | |
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-- | | |
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-- --------------------------------------------------------------------------------------------
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-- --------------------------------------------------------------------------------------------
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-- | length (bytes) | checksum |
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-- | length (bytes) | checksum |
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-- | (header and data combined) | |
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-- | (header and data combined) | |
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-- --------------------------------------------------------------------------------------------
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-- --------------------------------------------------------------------------------------------
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-- | Data |
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-- | Data |
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-- | |
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-- | |
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-- --------------------------------------------------------------------------------------------
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-- --------------------------------------------------------------------------------------------
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-- | .... |
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-- | .... |
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-- | |
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-- | |
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-- --------------------------------------------------------------------------------------------
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-- --------------------------------------------------------------------------------------------
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begin
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begin
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-----------------------------------------------------------------------
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-----------------------------------------------------------------------
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-- combinatorial process to implement FSM and determine control signals
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-- combinatorial process to implement FSM and determine control signals
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-----------------------------------------------------------------------
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-----------------------------------------------------------------------
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rx_combinatorial : process (
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rx_combinatorial : process (
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-- input signals
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-- input signals
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ip_rx, ip_rx_start,
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ip_rx, ip_rx_start,
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-- state variables
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-- state variables
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rx_state, rx_count, src_port, dst_port, data_len, udp_rx_start_reg, hdr_valid_reg, src_ip_addr,
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rx_state, rx_count, src_port, dst_port, data_len, udp_rx_start_reg, hdr_valid_reg, src_ip_addr,
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-- control signals
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-- control signals
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next_rx_state, set_rx_state, rx_event, rx_count_mode, rx_count_val,
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next_rx_state, set_rx_state, rx_event, rx_count_mode, rx_count_val,
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set_sph, set_spl, set_dph, set_dpl, set_len_H, set_len_L, set_data_last,
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set_sph, set_spl, set_dph, set_dpl, set_len_H, set_len_L, set_data_last,
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set_udp_rx_start, set_hdr_valid, dataval, set_pkt_cnt, set_src_ip
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set_udp_rx_start, set_hdr_valid, dataval, set_pkt_cnt, set_src_ip
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)
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)
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begin
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begin
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-- set output followers
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-- set output followers
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udp_rx_start <= udp_rx_start_reg;
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udp_rx_start <= udp_rx_start_reg;
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udp_rxo.hdr.is_valid <= hdr_valid_reg;
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udp_rxo.hdr.is_valid <= hdr_valid_reg;
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udp_rxo.hdr.data_length <= data_len;
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udp_rxo.hdr.data_length <= data_len;
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udp_rxo.hdr.src_port <= src_port;
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udp_rxo.hdr.src_port <= src_port;
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udp_rxo.hdr.dst_port <= dst_port;
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udp_rxo.hdr.dst_port <= dst_port;
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udp_rxo.hdr.src_ip_addr <= src_ip_addr;
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udp_rxo.hdr.src_ip_addr <= src_ip_addr;
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|
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-- transfer data upstream if in user data phase
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-- transfer data upstream if in user data phase
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if rx_state = USER_DATA then
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if rx_state = USER_DATA then
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udp_rxo.data.data_in <= ip_rx.data.data_in;
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udp_rxo.data.data_in <= ip_rx.data.data_in;
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udp_rxo.data.data_in_valid <= ip_rx.data.data_in_valid;
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udp_rxo.data.data_in_valid <= ip_rx.data.data_in_valid;
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udp_rxo.data.data_in_last <= set_data_last;
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udp_rxo.data.data_in_last <= set_data_last;
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else
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else
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udp_rxo.data.data_in <= (others => '0');
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udp_rxo.data.data_in <= (others => '0');
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udp_rxo.data.data_in_valid <= '0';
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udp_rxo.data.data_in_valid <= '0';
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udp_rxo.data.data_in_last <= '0';
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udp_rxo.data.data_in_last <= '0';
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end if;
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end if;
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-- set signal defaults
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-- set signal defaults
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next_rx_state <= IDLE;
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next_rx_state <= IDLE;
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set_rx_state <= '0';
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set_rx_state <= '0';
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rx_event <= NO_EVENT;
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rx_event <= NO_EVENT;
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rx_count_mode <= HOLD;
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rx_count_mode <= HOLD;
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set_sph <= '0';
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set_sph <= '0';
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set_spl <= '0';
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set_spl <= '0';
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set_dph <= '0';
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set_dph <= '0';
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set_dpl <= '0';
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set_dpl <= '0';
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set_len_H <= '0';
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set_len_H <= '0';
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set_len_L <= '0';
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set_len_L <= '0';
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set_udp_rx_start <= HOLD;
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set_udp_rx_start <= HOLD;
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set_hdr_valid <= HOLD;
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set_hdr_valid <= HOLD;
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dataval <= (others => '0');
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dataval <= (others => '0');
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set_src_ip <= '0';
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set_src_ip <= '0';
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rx_count_val <= (others => '0');
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rx_count_val <= (others => '0');
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set_data_last <= '0';
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set_data_last <= '0';
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-- determine event (if any)
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-- determine event (if any)
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if ip_rx.data.data_in_valid = '1' then
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if ip_rx.data.data_in_valid = '1' then
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rx_event <= DATA;
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rx_event <= DATA;
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dataval <= ip_rx.data.data_in;
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dataval <= ip_rx.data.data_in;
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end if;
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end if;
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-- RX FSM
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-- RX FSM
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case rx_state is
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case rx_state is
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when IDLE =>
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when IDLE =>
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rx_count_mode <= RST;
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rx_count_mode <= RST;
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case rx_event is
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case rx_event is
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when NO_EVENT => -- (nothing to do)
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when NO_EVENT => -- (nothing to do)
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when DATA =>
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when DATA =>
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if ip_rx.hdr.protocol = x"11" then
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if ip_rx.hdr.protocol = x"11" then
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-- UDP protocol
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-- UDP protocol
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rx_count_mode <= INCR;
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rx_count_mode <= INCR;
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set_hdr_valid <= CLR;
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set_hdr_valid <= CLR;
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set_src_ip <= '1';
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set_src_ip <= '1';
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set_sph <= '1';
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set_sph <= '1';
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next_rx_state <= UDP_HDR;
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next_rx_state <= UDP_HDR;
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set_rx_state <= '1';
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set_rx_state <= '1';
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else
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else
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-- non-UDP protocol - ignore this pkt
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-- non-UDP protocol - ignore this pkt
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set_hdr_valid <= CLR;
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set_hdr_valid <= CLR;
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next_rx_state <= WAIT_END;
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next_rx_state <= WAIT_END;
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set_rx_state <= '1';
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set_rx_state <= '1';
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end if;
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end if;
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end case;
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end case;
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when UDP_HDR =>
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when UDP_HDR =>
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case rx_event is
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case rx_event is
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when NO_EVENT => -- (nothing to do)
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when NO_EVENT => -- (nothing to do)
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when DATA =>
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when DATA =>
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if rx_count = x"0007" then
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if rx_count = x"0007" then
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rx_count_mode <= SET_VAL;
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rx_count_mode <= SET_VAL;
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rx_count_val <= x"0001";
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rx_count_val <= x"0001";
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next_rx_state <= USER_DATA;
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next_rx_state <= USER_DATA;
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set_rx_state <= '1';
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set_rx_state <= '1';
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else
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else
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rx_count_mode <= INCR;
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rx_count_mode <= INCR;
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end if;
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end if;
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-- handle early frame termination
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-- handle early frame termination
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if ip_rx.data.data_in_last = '1' then
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if ip_rx.data.data_in_last = '1' then
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next_rx_state <= ERR;
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next_rx_state <= ERR;
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set_rx_state <= '1';
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set_rx_state <= '1';
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else
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else
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case rx_count is
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case rx_count is
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when x"0000" => set_sph <= '1';
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when x"0000" => set_sph <= '1';
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when x"0001" => set_spl <= '1';
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when x"0001" => set_spl <= '1';
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when x"0002" => set_dph <= '1';
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when x"0002" => set_dph <= '1';
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when x"0003" => set_dpl <= '1';
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when x"0003" => set_dpl <= '1';
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|
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when x"0004" => set_len_H <= '1';
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when x"0004" => set_len_H <= '1';
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when x"0005" => set_len_L <= '1'; set_hdr_valid <= SET; -- header values are now valid, although the pkt may not be for us
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when x"0005" => set_len_L <= '1'; set_hdr_valid <= SET; -- header values are now valid, although the pkt may not be for us
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|
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when x"0006" => -- ignore checksum values
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when x"0006" => -- ignore checksum values
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when x"0007" => set_udp_rx_start <= SET; -- indicate frame received
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when x"0007" => set_udp_rx_start <= SET; -- indicate frame received
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|
|
|
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when others => -- ignore other bytes in udp header
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when others => -- ignore other bytes in udp header
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end case;
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end case;
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end if;
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end if;
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end case;
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end case;
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|
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when USER_DATA =>
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when USER_DATA =>
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case rx_event is
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case rx_event is
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when NO_EVENT => -- (nothing to do)
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when NO_EVENT => -- (nothing to do)
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when DATA =>
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when DATA =>
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-- note: data gets transfered upstream as part of "output followers" processing
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-- note: data gets transfered upstream as part of "output followers" processing
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if rx_count = unsigned(data_len) then
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if rx_count = unsigned(data_len) then
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set_udp_rx_start <= CLR;
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set_udp_rx_start <= CLR;
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rx_count_mode <= RST;
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rx_count_mode <= RST;
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set_data_last <= '1';
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set_data_last <= '1';
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if ip_rx.data.data_in_last = '1' then
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if ip_rx.data.data_in_last = '1' then
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next_rx_state <= IDLE;
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next_rx_state <= IDLE;
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set_udp_rx_start <= CLR;
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set_udp_rx_start <= CLR;
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else
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else
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next_rx_state <= WAIT_END;
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next_rx_state <= WAIT_END;
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end if;
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end if;
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set_rx_state <= '1';
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set_rx_state <= '1';
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else
|
else
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rx_count_mode <= INCR;
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rx_count_mode <= INCR;
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-- check for early frame termination
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-- check for early frame termination
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-- TODO need to mark frame as errored
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-- TODO need to mark frame as errored
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if ip_rx.data.data_in_last = '1' then
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if ip_rx.data.data_in_last = '1' then
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next_rx_state <= IDLE;
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next_rx_state <= IDLE;
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set_rx_state <= '1';
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set_rx_state <= '1';
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set_data_last <= '1';
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set_data_last <= '1';
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end if;
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end if;
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end if;
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end if;
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end case;
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end case;
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|
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when ERR =>
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when ERR =>
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if ip_rx.data.data_in_last = '0' then
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if ip_rx.data.data_in_last = '0' then
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next_rx_state <= WAIT_END;
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next_rx_state <= WAIT_END;
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set_rx_state <= '1';
|
set_rx_state <= '1';
|
else
|
else
|
next_rx_state <= IDLE;
|
next_rx_state <= IDLE;
|
set_rx_state <= '1';
|
set_rx_state <= '1';
|
end if;
|
end if;
|
|
|
|
|
when WAIT_END =>
|
when WAIT_END =>
|
case rx_event is
|
case rx_event is
|
when NO_EVENT => -- (nothing to do)
|
when NO_EVENT => -- (nothing to do)
|
when DATA =>
|
when DATA =>
|
if ip_rx.data.data_in_last = '1' then
|
if ip_rx.data.data_in_last = '1' then
|
next_rx_state <= IDLE;
|
next_rx_state <= IDLE;
|
set_rx_state <= '1';
|
set_rx_state <= '1';
|
end if;
|
end if;
|
end case;
|
end case;
|
|
|
end case;
|
end case;
|
|
|
end process;
|
end process;
|
|
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- sequential process to action control signals and change states and outputs
|
-- sequential process to action control signals and change states and outputs
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
rx_sequential : process (clk,reset)
|
rx_sequential : process (clk,reset)
|
begin
|
begin
|
if rising_edge(clk) then
|
if rising_edge(clk) then
|
if reset = '1' then
|
if reset = '1' then
|
-- reset state variables
|
-- reset state variables
|
rx_state <= IDLE;
|
rx_state <= IDLE;
|
rx_count <= x"0000";
|
rx_count <= x"0000";
|
src_port <= (others => '0');
|
src_port <= (others => '0');
|
dst_port <= (others => '0');
|
dst_port <= (others => '0');
|
data_len <= (others => '0');
|
data_len <= (others => '0');
|
udp_rx_start_reg <= '0';
|
udp_rx_start_reg <= '0';
|
hdr_valid_reg <= '0';
|
hdr_valid_reg <= '0';
|
src_ip_addr <= (others => '0');
|
src_ip_addr <= (others => '0');
|
else
|
else
|
-- Next rx_state processing
|
-- Next rx_state processing
|
if set_rx_state = '1' then
|
if set_rx_state = '1' then
|
rx_state <= next_rx_state;
|
rx_state <= next_rx_state;
|
else
|
else
|
rx_state <= rx_state;
|
rx_state <= rx_state;
|
end if;
|
end if;
|
|
|
-- rx_count processing
|
-- rx_count processing
|
case rx_count_mode is
|
case rx_count_mode is
|
when RST => rx_count <= x"0000";
|
when RST => rx_count <= x"0000";
|
when INCR => rx_count <= rx_count + 1;
|
when INCR => rx_count <= rx_count + 1;
|
when SET_VAL => rx_count <= rx_count_val;
|
when SET_VAL => rx_count <= rx_count_val;
|
when HOLD => rx_count <= rx_count;
|
when HOLD => rx_count <= rx_count;
|
end case;
|
end case;
|
|
|
-- port number capture
|
-- port number capture
|
if (set_sph = '1') then src_port(15 downto 8) <= dataval; end if;
|
if (set_sph = '1') then src_port(15 downto 8) <= dataval; end if;
|
if (set_spl = '1') then src_port(7 downto 0) <= dataval; end if;
|
if (set_spl = '1') then src_port(7 downto 0) <= dataval; end if;
|
if (set_dph = '1') then dst_port(15 downto 8) <= dataval; end if;
|
if (set_dph = '1') then dst_port(15 downto 8) <= dataval; end if;
|
if (set_dpl = '1') then dst_port(7 downto 0) <= dataval; end if;
|
if (set_dpl = '1') then dst_port(7 downto 0) <= dataval; end if;
|
|
|
if (set_len_H = '1') then
|
if (set_len_H = '1') then
|
data_len (15 downto 8) <= dataval;
|
data_len (15 downto 8) <= dataval;
|
data_len (7 downto 0) <= x"00";
|
data_len (7 downto 0) <= x"00";
|
elsif (set_len_L = '1') then
|
elsif (set_len_L = '1') then
|
-- compute data length, taking into account that we need to subtract the header length
|
-- compute data length, taking into account that we need to subtract the header length
|
data_len <= std_logic_vector(unsigned(data_len(15 downto 8) & dataval) - 8);
|
data_len <= std_logic_vector(unsigned(data_len(15 downto 8) & dataval) - 8);
|
else
|
else
|
data_len <= data_len;
|
data_len <= data_len;
|
end if;
|
end if;
|
|
|
case set_udp_rx_start is
|
case set_udp_rx_start is
|
when SET => udp_rx_start_reg <= '1';
|
when SET => udp_rx_start_reg <= '1';
|
when CLR => udp_rx_start_reg <= '0';
|
when CLR => udp_rx_start_reg <= '0';
|
when HOLD => udp_rx_start_reg <= udp_rx_start_reg;
|
when HOLD => udp_rx_start_reg <= udp_rx_start_reg;
|
end case;
|
end case;
|
|
|
-- capture src IP address
|
-- capture src IP address
|
if set_src_ip = '1' then
|
if set_src_ip = '1' then
|
src_ip_addr <= ip_rx.hdr.src_ip_addr;
|
src_ip_addr <= ip_rx.hdr.src_ip_addr;
|
else
|
else
|
src_ip_addr <= src_ip_addr;
|
src_ip_addr <= src_ip_addr;
|
end if;
|
end if;
|
|
|
case set_hdr_valid is
|
case set_hdr_valid is
|
when SET => hdr_valid_reg <= '1';
|
when SET => hdr_valid_reg <= '1';
|
when CLR => hdr_valid_reg <= '0';
|
when CLR => hdr_valid_reg <= '0';
|
when HOLD => hdr_valid_reg <= hdr_valid_reg;
|
when HOLD => hdr_valid_reg <= hdr_valid_reg;
|
end case;
|
end case;
|
|
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
end Behavioral;
|
end Behavioral;
|
|
|
|
|
