----------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
|
-- Company:
|
-- Company:
|
-- Engineer:
|
-- Engineer:
|
--
|
--
|
-- Create Date: 14:09:01 02/20/2012
|
-- Create Date: 14:09:01 02/20/2012
|
-- Design Name:
|
-- Design Name:
|
-- Module Name: arp_SYNC - Behavioral - synchronises between rx and tx clock domains
|
-- Module Name: arp_SYNC - Behavioral - synchronises between rx and tx clock domains
|
-- Project Name:
|
-- Project Name:
|
-- Target Devices:
|
-- Target Devices:
|
-- Tool versions:
|
-- Tool versions:
|
-- Description:
|
-- Description:
|
--
|
--
|
-- Dependencies:
|
-- Dependencies:
|
--
|
--
|
-- Revision:
|
-- Revision:
|
-- Revision 0.01 - File Created
|
-- Revision 0.01 - File Created
|
-- Additional Comments:
|
-- Additional Comments:
|
--
|
--
|
----------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
|
library IEEE;
|
library IEEE;
|
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.NUMERIC_STD.ALL;
|
use IEEE.NUMERIC_STD.ALL;
|
use work.arp_types.all;
|
use work.arp_types.all;
|
|
|
entity arp_SYNC is
|
entity arp_SYNC is
|
Port (
|
Port (
|
-- REQ to TX
|
-- REQ to TX
|
arp_nwk_req : in arp_nwk_request_t; -- request for a translation from IP to MAC
|
arp_nwk_req : in arp_nwk_request_t; -- request for a translation from IP to MAC
|
send_who_has : out std_logic;
|
send_who_has : out std_logic;
|
ip_entry : out STD_LOGIC_VECTOR (31 downto 0);
|
ip_entry : out STD_LOGIC_VECTOR (31 downto 0);
|
-- RX to TX
|
-- RX to TX
|
recv_who_has : in std_logic; -- this is for us, we will respond
|
recv_who_has : in std_logic; -- this is for us, we will respond
|
arp_entry_for_who_has : in arp_entry_t;
|
arp_entry_for_who_has : in arp_entry_t;
|
send_I_have : out std_logic;
|
send_I_have : out std_logic;
|
arp_entry : out arp_entry_t;
|
arp_entry : out arp_entry_t;
|
-- RX to REQ
|
-- RX to REQ
|
I_have_received : in std_logic;
|
I_have_received : in std_logic;
|
nwk_result_status : out arp_nwk_rslt_t;
|
nwk_result_status : out arp_nwk_rslt_t;
|
-- System Signals
|
-- System Signals
|
rx_clk : in std_logic;
|
rx_clk : in std_logic;
|
tx_clk : in std_logic;
|
tx_clk : in std_logic;
|
reset : in std_logic
|
reset : in std_logic
|
);
|
);
|
end arp_SYNC;
|
end arp_SYNC;
|
|
|
architecture Behavioral of arp_SYNC is
|
architecture Behavioral of arp_SYNC is
|
|
|
type sync_state_t is (IDLE,HOLD1, HOLD2);
|
type sync_state_t is (IDLE,HOLD1, HOLD2);
|
|
|
-- state registers
|
-- state registers
|
signal ip_entry_state : sync_state_t;
|
signal ip_entry_state : sync_state_t;
|
signal arp_entry_state : sync_state_t;
|
signal arp_entry_state : sync_state_t;
|
signal ip_entry_reg : STD_LOGIC_VECTOR (31 downto 0);
|
signal ip_entry_reg : STD_LOGIC_VECTOR (31 downto 0);
|
signal arp_entry_reg : arp_entry_t;
|
signal arp_entry_reg : arp_entry_t;
|
|
|
-- synchronisation registers
|
-- synchronisation registers
|
signal send_who_has_r1 : std_logic;
|
signal send_who_has_r1 : std_logic;
|
signal send_who_has_r2 : std_logic;
|
signal send_who_has_r2 : std_logic;
|
signal send_I_have_r1 : std_logic;
|
signal send_I_have_r1 : std_logic;
|
signal send_I_have_r2 : std_logic;
|
signal send_I_have_r2 : std_logic;
|
|
|
begin
|
begin
|
|
|
combinatorial : process (
|
combinatorial : process (
|
-- input signals
|
-- input signals
|
arp_nwk_req, recv_who_has, arp_entry_for_who_has, I_have_received, reset,
|
arp_nwk_req, recv_who_has, arp_entry_for_who_has, I_have_received, reset,
|
-- state
|
-- state
|
ip_entry_state, ip_entry_reg, arp_entry_state, arp_entry_reg,
|
ip_entry_state, ip_entry_reg, arp_entry_state, arp_entry_reg,
|
-- synchronisation registers
|
-- synchronisation registers
|
send_who_has_r1, send_who_has_r2,
|
send_who_has_r1, send_who_has_r2,
|
send_I_have_r1, send_I_have_r2
|
send_I_have_r1, send_I_have_r2
|
)
|
)
|
begin
|
begin
|
-- set output followers
|
-- set output followers
|
send_who_has <= send_who_has_r2;
|
send_who_has <= send_who_has_r2;
|
ip_entry <= ip_entry_reg;
|
ip_entry <= ip_entry_reg;
|
send_I_have <= send_I_have_r2;
|
send_I_have <= send_I_have_r2;
|
arp_entry <= arp_entry_reg;
|
arp_entry <= arp_entry_reg;
|
|
|
-- combinaltorial outputs
|
-- combinaltorial outputs
|
if I_have_received = '1' then
|
if I_have_received = '1' then
|
nwk_result_status <= RECEIVED;
|
nwk_result_status <= RECEIVED;
|
else
|
else
|
nwk_result_status <= IDLE;
|
nwk_result_status <= IDLE;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- process for stablisising RX clock domain data registers
|
-- process for stablisising RX clock domain data registers
|
-- essentially holds data registers ip_entry and arp_entry static for 2 rx clk cycles
|
-- essentially holds data registers ip_entry and arp_entry static for 2 rx clk cycles
|
-- during transfer to TX clk domain
|
-- during transfer to TX clk domain
|
rx_sequential : process (tx_clk)
|
rx_sequential : process (tx_clk)
|
begin
|
begin
|
if rising_edge(tx_clk) then
|
if rising_edge(tx_clk) then
|
if reset = '1' then
|
if reset = '1' then
|
-- reset state variables
|
-- reset state variables
|
ip_entry_reg <= (others => '0');
|
ip_entry_reg <= (others => '0');
|
arp_entry_reg.ip <= (others => '0');
|
arp_entry_reg.ip <= (others => '0');
|
arp_entry_reg.mac <= (others => '0');
|
arp_entry_reg.mac <= (others => '0');
|
else
|
else
|
-- normal (non reset) processing
|
-- normal (non reset) processing
|
case ip_entry_state is
|
case ip_entry_state is
|
when IDLE =>
|
when IDLE =>
|
if arp_nwk_req.req = '1' then
|
if arp_nwk_req.req = '1' then
|
ip_entry_reg <= arp_nwk_req.ip;
|
ip_entry_reg <= arp_nwk_req.ip;
|
ip_entry_state <= HOLD1;
|
ip_entry_state <= HOLD1;
|
else
|
else
|
ip_entry_reg <= ip_entry_reg;
|
ip_entry_reg <= ip_entry_reg;
|
ip_entry_state <= IDLE;
|
ip_entry_state <= IDLE;
|
end if;
|
end if;
|
when HOLD1 =>
|
when HOLD1 =>
|
ip_entry_reg <= ip_entry_reg;
|
ip_entry_reg <= ip_entry_reg;
|
ip_entry_state <= HOLD2;
|
ip_entry_state <= HOLD2;
|
when HOLD2 =>
|
when HOLD2 =>
|
ip_entry_reg <= ip_entry_reg;
|
ip_entry_reg <= ip_entry_reg;
|
ip_entry_state <= IDLE;
|
ip_entry_state <= IDLE;
|
end case;
|
end case;
|
|
|
case arp_entry_state is
|
case arp_entry_state is
|
when IDLE =>
|
when IDLE =>
|
if recv_who_has = '1' then
|
if recv_who_has = '1' then
|
arp_entry_reg <= arp_entry_for_who_has;
|
arp_entry_reg <= arp_entry_for_who_has;
|
arp_entry_state <= HOLD1;
|
arp_entry_state <= HOLD1;
|
else
|
else
|
arp_entry_reg <= arp_entry_reg;
|
arp_entry_reg <= arp_entry_reg;
|
arp_entry_state <= IDLE;
|
arp_entry_state <= IDLE;
|
end if;
|
end if;
|
when HOLD1 =>
|
when HOLD1 =>
|
arp_entry_reg <= arp_entry_reg;
|
arp_entry_reg <= arp_entry_reg;
|
arp_entry_state <= HOLD2;
|
arp_entry_state <= HOLD2;
|
when HOLD2 =>
|
when HOLD2 =>
|
arp_entry_reg <= arp_entry_reg;
|
arp_entry_reg <= arp_entry_reg;
|
arp_entry_state <= IDLE;
|
arp_entry_state <= IDLE;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- process for syncing to the TX clock domain
|
-- process for syncing to the TX clock domain
|
-- clocks control signals through 2 layers of tx clocking
|
-- clocks control signals through 2 layers of tx clocking
|
tx_sequential : process (tx_clk)
|
tx_sequential : process (tx_clk)
|
begin
|
begin
|
if rising_edge(tx_clk) then
|
if rising_edge(tx_clk) then
|
if reset = '1' then
|
if reset = '1' then
|
-- reset state variables
|
-- reset state variables
|
send_who_has_r1 <= '0';
|
send_who_has_r1 <= '0';
|
send_who_has_r2 <= '0';
|
send_who_has_r2 <= '0';
|
send_I_have_r1 <= '0';
|
send_I_have_r1 <= '0';
|
send_I_have_r2 <= '0';
|
send_I_have_r2 <= '0';
|
else
|
else
|
-- normal (non reset) processing
|
-- normal (non reset) processing
|
|
|
send_who_has_r1 <= arp_nwk_req.req;
|
send_who_has_r1 <= arp_nwk_req.req;
|
send_who_has_r2 <= send_who_has_r1;
|
send_who_has_r2 <= send_who_has_r1;
|
|
|
send_I_have_r1 <= recv_who_has;
|
send_I_have_r1 <= recv_who_has;
|
send_I_have_r2 <= send_I_have_r1;
|
send_I_have_r2 <= send_I_have_r1;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
end Behavioral;
|
end Behavioral;
|
|
|
|
|
