--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Project : low latency UDP
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-- Project : low latency UDP
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-- File : xv6mac_straight
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-- File : xv6mac_straight
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-- Version : 0.0
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-- Version : 0.0
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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--
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--
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-- Description: This is an adaptation of the Xilinx V6 MAC layer, but without the FIFOs
|
-- Description: This is an adaptation of the Xilinx V6 MAC layer, but without the FIFOs
|
--
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--
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--
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--
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--
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--
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-- ---------------------------------------------------------------------
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-- ---------------------------------------------------------------------
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-- | EXAMPLE DESIGN WRAPPER |
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-- | EXAMPLE DESIGN WRAPPER |
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-- | --------------------------------------------------------|
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-- | --------------------------------------------------------|
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-- | |FIFO BLOCK WRAPPER |
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-- | |FIFO BLOCK WRAPPER |
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-- | | |
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-- | | |
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-- | | |
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-- | | |
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-- | | -----------------------------------------|
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-- | | -----------------------------------------|
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-- | | | BLOCK LEVEL WRAPPER |
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-- | | | BLOCK LEVEL WRAPPER |
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-- | | | --------------------- |
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-- | | | --------------------- |
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-- | | | | V6 EMAC CORE | |
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-- | | | | V6 EMAC CORE | |
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-- | | | | | |
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-- | | | | | |
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-- | | | | | |
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-- | | | | | |
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-- | | | | | |
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-- | | | | | |
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-- | | | | | |
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-- | | | | | |
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-- | | | | | |
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-- | | | | | |
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-- | | | | | | | --------- |
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-- | | | | | | | --------- |
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-- | | |->|->----------->|--|--->| Tx Tx |--| |--->|
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-- | | |->|->----------->|--|--->| Tx Tx |--| |--->|
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-- | | | | | | AXI-S PHY | | | |
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-- | | | | | | AXI-S PHY | | | |
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-- | | | | | | I/F I/F | | | |
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-- | | | | | | I/F I/F | | | |
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-- | | | | | | | | PHY | |
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-- | | | | | | | | PHY | |
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-- | | | | | | | | I/F | |
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-- | | | | | | | | I/F | |
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-- | | | | | | | | | |
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-- | | | | | | | | | |
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-- | | | | | | Rx Rx | | | |
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-- | | | | | | Rx Rx | | | |
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-- | | | | | | AX)-S PHY | | | |
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-- | | | | | | AX)-S PHY | | | |
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-- | | |<-|<-------------|----| I/F I/F |<-| |<---|
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-- | | |<-|<-------------|----| I/F I/F |<-| |<---|
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-- | | | | | | | --------- |
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-- | | | | | | | --------- |
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-- | -------- | | --------------------- |
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-- | -------- | | --------------------- |
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-- | | | |
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-- | | | |
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-- | | -----------------------------------------|
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-- | | -----------------------------------------|
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-- | --------------------------------------------------------|
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-- | --------------------------------------------------------|
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-- ---------------------------------------------------------------------
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-- ---------------------------------------------------------------------
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--
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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|
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library unisim;
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library unisim;
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use unisim.vcomponents.all;
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use unisim.vcomponents.all;
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|
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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|
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entity xv6mac_straight is
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entity xv6mac_straight is
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port (
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port (
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-- System controls
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-- System controls
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------------------
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------------------
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glbl_rst : in std_logic; -- asynchronous reset
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glbl_rst : in std_logic; -- asynchronous reset
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mac_reset : in std_logic; -- reset mac layer
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mac_reset : in std_logic; -- reset mac layer
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clk_in_p : in std_logic; -- 200MHz clock input from board
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clk_in_p : in std_logic; -- 200MHz clock input from board
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clk_in_n : in std_logic;
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clk_in_n : in std_logic;
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|
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-- MAC Transmitter (AXI-S) Interface
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-- MAC Transmitter (AXI-S) Interface
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---------------------------------------------
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---------------------------------------------
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mac_tx_clock : out std_logic; -- data sampled on rising edge
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mac_tx_clock : out std_logic; -- data sampled on rising edge
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mac_tx_tdata : in std_logic_vector(7 downto 0); -- data byte to tx
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mac_tx_tdata : in std_logic_vector(7 downto 0); -- data byte to tx
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mac_tx_tvalid : in std_logic; -- tdata is valid
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mac_tx_tvalid : in std_logic; -- tdata is valid
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mac_tx_tready : out std_logic; -- mac is ready to accept data
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mac_tx_tready : out std_logic; -- mac is ready to accept data
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mac_tx_tlast : in std_logic; -- indicates last byte of frame
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mac_tx_tlast : in std_logic; -- indicates last byte of frame
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|
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-- MAC Receiver (AXI-S) Interface
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-- MAC Receiver (AXI-S) Interface
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------------------------------------------
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------------------------------------------
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mac_rx_clock : out std_logic; -- data valid on rising edge
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mac_rx_clock : out std_logic; -- data valid on rising edge
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mac_rx_tdata : out std_logic_vector(7 downto 0); -- data byte received
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mac_rx_tdata : out std_logic_vector(7 downto 0); -- data byte received
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mac_rx_tvalid : out std_logic; -- indicates tdata is valid
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mac_rx_tvalid : out std_logic; -- indicates tdata is valid
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mac_rx_tready : in std_logic; -- tells mac that we are ready to take data
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mac_rx_tready : in std_logic; -- tells mac that we are ready to take data
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mac_rx_tlast : out std_logic; -- indicates last byte of the trame
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mac_rx_tlast : out std_logic; -- indicates last byte of the trame
|
|
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-- GMII Interface
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-- GMII Interface
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-----------------
|
-----------------
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phy_resetn : out std_logic;
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phy_resetn : out std_logic;
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gmii_txd : out std_logic_vector(7 downto 0);
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gmii_txd : out std_logic_vector(7 downto 0);
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gmii_tx_en : out std_logic;
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gmii_tx_en : out std_logic;
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gmii_tx_er : out std_logic;
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gmii_tx_er : out std_logic;
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gmii_tx_clk : out std_logic;
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gmii_tx_clk : out std_logic;
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gmii_rxd : in std_logic_vector(7 downto 0);
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gmii_rxd : in std_logic_vector(7 downto 0);
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gmii_rx_dv : in std_logic;
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gmii_rx_dv : in std_logic;
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gmii_rx_er : in std_logic;
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gmii_rx_er : in std_logic;
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gmii_rx_clk : in std_logic;
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gmii_rx_clk : in std_logic;
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gmii_col : in std_logic;
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gmii_col : in std_logic;
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gmii_crs : in std_logic;
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gmii_crs : in std_logic;
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mii_tx_clk : in std_logic
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mii_tx_clk : in std_logic
|
);
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);
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end xv6mac_straight;
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end xv6mac_straight;
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|
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architecture wrapper of xv6mac_straight is
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architecture wrapper of xv6mac_straight is
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|
|
------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Component declaration for the internal mac layer
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-- Component declaration for the internal mac layer
|
------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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component mac_layer_v2_2_block
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component mac_layer_v2_2_block
|
port(
|
port(
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gtx_clk : in std_logic;
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gtx_clk : in std_logic;
|
|
|
-- Receiver Interface
|
-- Receiver Interface
|
----------------------------
|
----------------------------
|
rx_statistics_vector : out std_logic_vector(27 downto 0);
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rx_statistics_vector : out std_logic_vector(27 downto 0);
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rx_statistics_valid : out std_logic;
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rx_statistics_valid : out std_logic;
|
|
|
rx_mac_aclk : out std_logic;
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rx_mac_aclk : out std_logic;
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rx_reset : out std_logic;
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rx_reset : out std_logic;
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rx_axis_mac_tdata : out std_logic_vector(7 downto 0);
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rx_axis_mac_tdata : out std_logic_vector(7 downto 0);
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rx_axis_mac_tvalid : out std_logic;
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rx_axis_mac_tvalid : out std_logic;
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rx_axis_mac_tlast : out std_logic;
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rx_axis_mac_tlast : out std_logic;
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rx_axis_mac_tuser : out std_logic;
|
rx_axis_mac_tuser : out std_logic;
|
|
|
-- Transmitter Interface
|
-- Transmitter Interface
|
-------------------------------
|
-------------------------------
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tx_ifg_delay : in std_logic_vector(7 downto 0);
|
tx_ifg_delay : in std_logic_vector(7 downto 0);
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tx_statistics_vector : out std_logic_vector(31 downto 0);
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tx_statistics_vector : out std_logic_vector(31 downto 0);
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tx_statistics_valid : out std_logic;
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tx_statistics_valid : out std_logic;
|
|
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tx_reset : out std_logic;
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tx_reset : out std_logic;
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tx_axis_mac_tdata : in std_logic_vector(7 downto 0);
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tx_axis_mac_tdata : in std_logic_vector(7 downto 0);
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tx_axis_mac_tvalid : in std_logic;
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tx_axis_mac_tvalid : in std_logic;
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tx_axis_mac_tlast : in std_logic;
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tx_axis_mac_tlast : in std_logic;
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tx_axis_mac_tuser : in std_logic;
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tx_axis_mac_tuser : in std_logic;
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tx_axis_mac_tready : out std_logic;
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tx_axis_mac_tready : out std_logic;
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tx_collision : out std_logic;
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tx_collision : out std_logic;
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tx_retransmit : out std_logic;
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tx_retransmit : out std_logic;
|
|
|
-- MAC Control Interface
|
-- MAC Control Interface
|
------------------------
|
------------------------
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pause_req : in std_logic;
|
pause_req : in std_logic;
|
pause_val : in std_logic_vector(15 downto 0);
|
pause_val : in std_logic_vector(15 downto 0);
|
|
|
-- Reference clock for IDELAYCTRL's
|
-- Reference clock for IDELAYCTRL's
|
refclk : in std_logic;
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refclk : in std_logic;
|
|
|
-- GMII Interface
|
-- GMII Interface
|
-----------------
|
-----------------
|
gmii_txd : out std_logic_vector(7 downto 0);
|
gmii_txd : out std_logic_vector(7 downto 0);
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gmii_tx_en : out std_logic;
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gmii_tx_en : out std_logic;
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gmii_tx_er : out std_logic;
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gmii_tx_er : out std_logic;
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gmii_tx_clk : out std_logic;
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gmii_tx_clk : out std_logic;
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gmii_rxd : in std_logic_vector(7 downto 0);
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gmii_rxd : in std_logic_vector(7 downto 0);
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gmii_rx_dv : in std_logic;
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gmii_rx_dv : in std_logic;
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gmii_rx_er : in std_logic;
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gmii_rx_er : in std_logic;
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gmii_rx_clk : in std_logic;
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gmii_rx_clk : in std_logic;
|
|
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-- asynchronous reset
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-- asynchronous reset
|
-----------------
|
-----------------
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glbl_rstn : in std_logic;
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glbl_rstn : in std_logic;
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rx_axi_rstn : in std_logic;
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rx_axi_rstn : in std_logic;
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tx_axi_rstn : in std_logic
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tx_axi_rstn : in std_logic
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|
|
);
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);
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end component;
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end component;
|
|
|
|
|
------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Component Declaration for the Clock generator
|
-- Component Declaration for the Clock generator
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
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|
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component clk_wiz_v2_2
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component clk_wiz_v2_2
|
port (
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port (
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-- Clock in ports
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-- Clock in ports
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CLK_IN1_P : in std_logic;
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CLK_IN1_P : in std_logic;
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CLK_IN1_N : in std_logic;
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CLK_IN1_N : in std_logic;
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-- Clock out ports
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-- Clock out ports
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CLK_OUT1 : out std_logic;
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CLK_OUT1 : out std_logic;
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CLK_OUT2 : out std_logic;
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CLK_OUT2 : out std_logic;
|
CLK_OUT3 : out std_logic;
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CLK_OUT3 : out std_logic;
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-- Status and control signals
|
-- Status and control signals
|
RESET : in std_logic;
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RESET : in std_logic;
|
LOCKED : out std_logic
|
LOCKED : out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
|
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
-- Component declaration for the reset synchroniser
|
-- Component declaration for the reset synchroniser
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
component reset_sync_v2_2
|
component reset_sync_v2_2
|
port (
|
port (
|
reset_in : in std_logic; -- Active high asynchronous reset
|
reset_in : in std_logic; -- Active high asynchronous reset
|
enable : in std_logic;
|
enable : in std_logic;
|
clk : in std_logic; -- clock to be sync'ed to
|
clk : in std_logic; -- clock to be sync'ed to
|
reset_out : out std_logic -- "Synchronised" reset signal
|
reset_out : out std_logic -- "Synchronised" reset signal
|
);
|
);
|
end component;
|
end component;
|
|
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
-- Component declaration for the synchroniser
|
-- Component declaration for the synchroniser
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
component sync_block_v2_2
|
component sync_block_v2_2
|
port (
|
port (
|
clk : in std_logic;
|
clk : in std_logic;
|
data_in : in std_logic;
|
data_in : in std_logic;
|
data_out : out std_logic
|
data_out : out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
-- Constants used in this top level wrapper.
|
-- Constants used in this top level wrapper.
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
constant BOARD_PHY_ADDR : std_logic_vector(7 downto 0) := "00000111";
|
constant BOARD_PHY_ADDR : std_logic_vector(7 downto 0) := "00000111";
|
|
|
|
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
-- internal signals used in this top level wrapper.
|
-- internal signals used in this top level wrapper.
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
|
|
-- example design clocks
|
-- example design clocks
|
signal gtx_clk_bufg : std_logic;
|
signal gtx_clk_bufg : std_logic;
|
signal refclk_bufg : std_logic;
|
signal refclk_bufg : std_logic;
|
signal rx_mac_aclk : std_logic;
|
signal rx_mac_aclk : std_logic;
|
|
|
-- tx handshaking
|
-- tx handshaking
|
signal mac_tx_tready_int : std_logic;
|
signal mac_tx_tready_int : std_logic;
|
signal tx_full_reg : std_logic;
|
signal tx_full_reg : std_logic;
|
signal tx_full_val : std_logic;
|
signal tx_full_val : std_logic;
|
signal tx_data_reg : std_logic_vector(7 downto 0);
|
signal tx_data_reg : std_logic_vector(7 downto 0);
|
signal tx_last_reg : std_logic;
|
signal tx_last_reg : std_logic;
|
signal set_tx_reg : std_logic;
|
signal set_tx_reg : std_logic;
|
|
|
signal phy_resetn_int : std_logic;
|
signal phy_resetn_int : std_logic;
|
|
|
-- resets (and reset generation)
|
-- resets (and reset generation)
|
signal local_chk_reset : std_logic;
|
signal local_chk_reset : std_logic;
|
signal chk_reset_int : std_logic;
|
signal chk_reset_int : std_logic;
|
signal chk_pre_resetn : std_logic := '0';
|
signal chk_pre_resetn : std_logic := '0';
|
signal chk_resetn : std_logic := '0';
|
signal chk_resetn : std_logic := '0';
|
signal dcm_locked : std_logic;
|
signal dcm_locked : std_logic;
|
|
|
signal glbl_rst_int : std_logic;
|
signal glbl_rst_int : std_logic;
|
signal phy_reset_count : unsigned(5 downto 0);
|
signal phy_reset_count : unsigned(5 downto 0);
|
signal glbl_rst_intn : std_logic;
|
signal glbl_rst_intn : std_logic;
|
|
|
-- pipeline register for RX signals
|
-- pipeline register for RX signals
|
signal rx_data_val : std_logic_vector(7 downto 0);
|
signal rx_data_val : std_logic_vector(7 downto 0);
|
signal rx_tvalid_val : std_logic;
|
signal rx_tvalid_val : std_logic;
|
signal rx_tlast_val : std_logic;
|
signal rx_tlast_val : std_logic;
|
signal rx_data_reg : std_logic_vector(7 downto 0);
|
signal rx_data_reg : std_logic_vector(7 downto 0);
|
signal rx_tvalid_reg : std_logic;
|
signal rx_tvalid_reg : std_logic;
|
signal rx_tlast_reg : std_logic;
|
signal rx_tlast_reg : std_logic;
|
|
|
attribute keep : string;
|
attribute keep : string;
|
attribute keep of gtx_clk_bufg : signal is "true";
|
attribute keep of gtx_clk_bufg : signal is "true";
|
attribute keep of refclk_bufg : signal is "true";
|
attribute keep of refclk_bufg : signal is "true";
|
attribute keep of mac_tx_tready_int : signal is "true";
|
attribute keep of mac_tx_tready_int : signal is "true";
|
attribute keep of tx_full_reg : signal is "true";
|
attribute keep of tx_full_reg : signal is "true";
|
|
|
|
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
-- Begin architecture
|
-- Begin architecture
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
|
|
begin
|
begin
|
|
|
combinatorial: process (
|
combinatorial: process (
|
rx_data_reg, rx_tvalid_reg, rx_tlast_reg,
|
rx_data_reg, rx_tvalid_reg, rx_tlast_reg,
|
mac_tx_tvalid, mac_tx_tready_int, tx_full_reg, tx_full_val, set_tx_reg
|
mac_tx_tvalid, mac_tx_tready_int, tx_full_reg, tx_full_val, set_tx_reg
|
)
|
)
|
begin
|
begin
|
-- output followers
|
-- output followers
|
mac_rx_tdata <= rx_data_reg;
|
mac_rx_tdata <= rx_data_reg;
|
mac_rx_tvalid <= rx_tvalid_reg;
|
mac_rx_tvalid <= rx_tvalid_reg;
|
mac_rx_tlast <= rx_tlast_reg;
|
mac_rx_tlast <= rx_tlast_reg;
|
mac_tx_tready <= not (tx_full_reg and not mac_tx_tready_int); -- if not full, we are ready to accept
|
mac_tx_tready <= not (tx_full_reg and not mac_tx_tready_int); -- if not full, we are ready to accept
|
|
|
-- control defaults
|
-- control defaults
|
tx_full_val <= tx_full_reg;
|
tx_full_val <= tx_full_reg;
|
set_tx_reg <= '0';
|
set_tx_reg <= '0';
|
|
|
-- tx handshaking logic
|
-- tx handshaking logic
|
if mac_tx_tvalid = '1' then
|
if mac_tx_tvalid = '1' then
|
tx_full_val <= '1';
|
tx_full_val <= '1';
|
set_tx_reg <= '1';
|
set_tx_reg <= '1';
|
elsif mac_tx_tready_int = '1' then
|
elsif mac_tx_tready_int = '1' then
|
tx_full_val <= '0';
|
tx_full_val <= '0';
|
end if;
|
end if;
|
|
|
end process;
|
end process;
|
|
|
sequential: process(gtx_clk_bufg)
|
sequential: process(gtx_clk_bufg)
|
begin
|
begin
|
if rising_edge(gtx_clk_bufg) then
|
if rising_edge(gtx_clk_bufg) then
|
if chk_resetn = '0' then
|
if chk_resetn = '0' then
|
-- reset state variables
|
-- reset state variables
|
rx_data_reg <= (others => '0');
|
rx_data_reg <= (others => '0');
|
rx_tvalid_reg <= '0';
|
rx_tvalid_reg <= '0';
|
rx_tlast_reg <= '0';
|
rx_tlast_reg <= '0';
|
tx_full_reg <= '0';
|
tx_full_reg <= '0';
|
tx_data_reg <= (others => '0');
|
tx_data_reg <= (others => '0');
|
tx_last_reg <= '0';
|
tx_last_reg <= '0';
|
else
|
else
|
-- register rx data
|
-- register rx data
|
rx_data_reg <= rx_data_val;
|
rx_data_reg <= rx_data_val;
|
rx_tvalid_reg <= rx_tvalid_val;
|
rx_tvalid_reg <= rx_tvalid_val;
|
rx_tlast_reg <= rx_tlast_val;
|
rx_tlast_reg <= rx_tlast_val;
|
|
|
-- process tx tvalid and tready
|
-- process tx tvalid and tready
|
tx_full_reg <= tx_full_val;
|
tx_full_reg <= tx_full_val;
|
if set_tx_reg = '1' then
|
if set_tx_reg = '1' then
|
tx_data_reg <= mac_tx_tdata;
|
tx_data_reg <= mac_tx_tdata;
|
tx_last_reg <= mac_tx_tlast;
|
tx_last_reg <= mac_tx_tlast;
|
else
|
else
|
tx_data_reg <= tx_data_reg;
|
tx_data_reg <= tx_data_reg;
|
tx_last_reg <= tx_last_reg;
|
tx_last_reg <= tx_last_reg;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
-- Instantiate the Tri-Mode EMAC Block wrapper
|
-- Instantiate the Tri-Mode EMAC Block wrapper
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
v6emac_block : mac_layer_v2_2_block
|
v6emac_block : mac_layer_v2_2_block
|
port map(
|
port map(
|
gtx_clk => gtx_clk_bufg,
|
gtx_clk => gtx_clk_bufg,
|
|
|
-- Client Receiver Interface
|
-- Client Receiver Interface
|
rx_statistics_vector => open,
|
rx_statistics_vector => open,
|
rx_statistics_valid => open,
|
rx_statistics_valid => open,
|
|
|
rx_mac_aclk => open,
|
rx_mac_aclk => open,
|
rx_reset => open,
|
rx_reset => open,
|
rx_axis_mac_tdata => rx_data_val,
|
rx_axis_mac_tdata => rx_data_val,
|
rx_axis_mac_tvalid => rx_tvalid_val,
|
rx_axis_mac_tvalid => rx_tvalid_val,
|
rx_axis_mac_tlast => rx_tlast_val,
|
rx_axis_mac_tlast => rx_tlast_val,
|
rx_axis_mac_tuser => open,
|
rx_axis_mac_tuser => open,
|
|
|
-- Client Transmitter Interface
|
-- Client Transmitter Interface
|
tx_ifg_delay => x"00",
|
tx_ifg_delay => x"00",
|
tx_statistics_vector => open,
|
tx_statistics_vector => open,
|
tx_statistics_valid => open,
|
tx_statistics_valid => open,
|
|
|
tx_reset => open,
|
tx_reset => open,
|
tx_axis_mac_tdata => tx_data_reg,
|
tx_axis_mac_tdata => tx_data_reg,
|
tx_axis_mac_tvalid => tx_full_reg,
|
tx_axis_mac_tvalid => tx_full_reg,
|
tx_axis_mac_tlast => tx_last_reg,
|
tx_axis_mac_tlast => tx_last_reg,
|
tx_axis_mac_tuser => '0',
|
tx_axis_mac_tuser => '0',
|
tx_axis_mac_tready => mac_tx_tready_int,
|
tx_axis_mac_tready => mac_tx_tready_int,
|
tx_collision => open,
|
tx_collision => open,
|
tx_retransmit => open,
|
tx_retransmit => open,
|
|
|
-- Flow Control
|
-- Flow Control
|
pause_req => '0',
|
pause_req => '0',
|
pause_val => x"0000",
|
pause_val => x"0000",
|
|
|
-- Reference clock for IDELAYCTRL's
|
-- Reference clock for IDELAYCTRL's
|
refclk => refclk_bufg,
|
refclk => refclk_bufg,
|
|
|
-- GMII Interface
|
-- GMII Interface
|
gmii_txd => gmii_txd,
|
gmii_txd => gmii_txd,
|
gmii_tx_en => gmii_tx_en,
|
gmii_tx_en => gmii_tx_en,
|
gmii_tx_er => gmii_tx_er,
|
gmii_tx_er => gmii_tx_er,
|
gmii_tx_clk => gmii_tx_clk,
|
gmii_tx_clk => gmii_tx_clk,
|
gmii_rxd => gmii_rxd,
|
gmii_rxd => gmii_rxd,
|
gmii_rx_dv => gmii_rx_dv,
|
gmii_rx_dv => gmii_rx_dv,
|
gmii_rx_er => gmii_rx_er,
|
gmii_rx_er => gmii_rx_er,
|
gmii_rx_clk => gmii_rx_clk,
|
gmii_rx_clk => gmii_rx_clk,
|
|
|
-- asynchronous reset
|
-- asynchronous reset
|
glbl_rstn => chk_resetn,
|
glbl_rstn => chk_resetn,
|
rx_axi_rstn => '1',
|
rx_axi_rstn => '1',
|
tx_axi_rstn => '1'
|
tx_axi_rstn => '1'
|
);
|
);
|
|
|
|
|
|
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
-- Clock logic to generate required clocks from the 200MHz on board
|
-- Clock logic to generate required clocks from the 200MHz on board
|
-- if 125MHz is available directly this can be removed
|
-- if 125MHz is available directly this can be removed
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
clock_generator : clk_wiz_v2_2
|
clock_generator : clk_wiz_v2_2
|
port map (
|
port map (
|
-- Clock in ports
|
-- Clock in ports
|
CLK_IN1_P => clk_in_p,
|
CLK_IN1_P => clk_in_p,
|
CLK_IN1_N => clk_in_n,
|
CLK_IN1_N => clk_in_n,
|
-- Clock out ports
|
-- Clock out ports
|
CLK_OUT1 => gtx_clk_bufg,
|
CLK_OUT1 => gtx_clk_bufg,
|
CLK_OUT2 => open,
|
CLK_OUT2 => open,
|
CLK_OUT3 => refclk_bufg,
|
CLK_OUT3 => refclk_bufg,
|
-- Status and control signals
|
-- Status and control signals
|
RESET => glbl_rst,
|
RESET => glbl_rst,
|
LOCKED => dcm_locked
|
LOCKED => dcm_locked
|
);
|
);
|
|
|
-----------------
|
-----------------
|
-- global reset
|
-- global reset
|
glbl_reset_gen : reset_sync_v2_2
|
glbl_reset_gen : reset_sync_v2_2
|
port map (
|
port map (
|
clk => gtx_clk_bufg,
|
clk => gtx_clk_bufg,
|
enable => dcm_locked,
|
enable => dcm_locked,
|
reset_in => glbl_rst,
|
reset_in => glbl_rst,
|
reset_out => glbl_rst_int
|
reset_out => glbl_rst_int
|
);
|
);
|
|
|
glbl_rst_intn <= not glbl_rst_int;
|
glbl_rst_intn <= not glbl_rst_int;
|
|
|
-- generate the user side clocks
|
-- generate the user side clocks
|
mac_tx_clock <= gtx_clk_bufg;
|
mac_tx_clock <= gtx_clk_bufg;
|
mac_rx_clock <= gtx_clk_bufg;
|
mac_rx_clock <= gtx_clk_bufg;
|
|
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
-- Generate resets
|
-- Generate resets
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
-- in each case the async reset is first captured and then synchronised
|
-- in each case the async reset is first captured and then synchronised
|
|
|
|
|
local_chk_reset <= glbl_rst or mac_reset;
|
local_chk_reset <= glbl_rst or mac_reset;
|
|
|
-----------------
|
-----------------
|
-- data check reset
|
-- data check reset
|
chk_reset_gen : reset_sync_v2_2
|
chk_reset_gen : reset_sync_v2_2
|
port map (
|
port map (
|
clk => gtx_clk_bufg,
|
clk => gtx_clk_bufg,
|
enable => dcm_locked,
|
enable => dcm_locked,
|
reset_in => local_chk_reset,
|
reset_in => local_chk_reset,
|
reset_out => chk_reset_int
|
reset_out => chk_reset_int
|
);
|
);
|
|
|
-- Create fully synchronous reset in the gtx clock domain.
|
-- Create fully synchronous reset in the gtx clock domain.
|
gen_chk_reset : process (gtx_clk_bufg)
|
gen_chk_reset : process (gtx_clk_bufg)
|
begin
|
begin
|
if gtx_clk_bufg'event and gtx_clk_bufg = '1' then
|
if gtx_clk_bufg'event and gtx_clk_bufg = '1' then
|
if chk_reset_int = '1' then
|
if chk_reset_int = '1' then
|
chk_pre_resetn <= '0';
|
chk_pre_resetn <= '0';
|
chk_resetn <= '0';
|
chk_resetn <= '0';
|
else
|
else
|
chk_pre_resetn <= '1';
|
chk_pre_resetn <= '1';
|
chk_resetn <= chk_pre_resetn;
|
chk_resetn <= chk_pre_resetn;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process gen_chk_reset;
|
end process gen_chk_reset;
|
|
|
|
|
-----------------
|
-----------------
|
-- PHY reset
|
-- PHY reset
|
-- the phy reset output (active low) needs to be held for at least 10x25MHZ cycles
|
-- the phy reset output (active low) needs to be held for at least 10x25MHZ cycles
|
-- this is derived using the 125MHz available and a 6 bit counter
|
-- this is derived using the 125MHz available and a 6 bit counter
|
gen_phy_reset : process (gtx_clk_bufg)
|
gen_phy_reset : process (gtx_clk_bufg)
|
begin
|
begin
|
if gtx_clk_bufg'event and gtx_clk_bufg = '1' then
|
if gtx_clk_bufg'event and gtx_clk_bufg = '1' then
|
if glbl_rst_intn = '0' then
|
if glbl_rst_intn = '0' then
|
phy_resetn_int <= '0';
|
phy_resetn_int <= '0';
|
phy_reset_count <= (others => '0');
|
phy_reset_count <= (others => '0');
|
else
|
else
|
if phy_reset_count /= "111111" then
|
if phy_reset_count /= "111111" then
|
phy_reset_count <= phy_reset_count + "000001";
|
phy_reset_count <= phy_reset_count + "000001";
|
else
|
else
|
phy_resetn_int <= '1';
|
phy_resetn_int <= '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process gen_phy_reset;
|
end process gen_phy_reset;
|
|
|
phy_resetn <= phy_resetn_int;
|
phy_resetn <= phy_resetn_int;
|
|
|
|
|
end wrapper;
|
end wrapper;
|
|
|
