/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Test Bench Library ////
|
//// Test Bench Library ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// Author: Rudolf Usselmann ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
|
//// rudi@asics.ws ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// Downloaded from: http://www.opencores.org/cores/usb1_funct/////
|
//// Downloaded from: http://www.opencores.org/cores/usb1_funct/////
|
//// ////
|
//// ////
|
/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// www.asics.ws ////
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//// www.asics.ws ////
|
//// rudi@asics.ws ////
|
//// rudi@asics.ws ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer.////
|
//// the original copyright notice and the associated disclaimer.////
|
//// ////
|
//// ////
|
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
|
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
|
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
|
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
|
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
|
//// ////
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/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
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|
|
// CVS Log
|
// CVS Log
|
//
|
//
|
// $Id: tests_lib.v,v 1.1 2002-09-25 06:10:10 rudi Exp $
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// $Id: tests_lib.v,v 1.1 2002-09-25 06:10:10 rudi Exp $
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//
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//
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// $Date: 2002-09-25 06:10:10 $
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// $Date: 2002-09-25 06:10:10 $
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// $Revision: 1.1 $
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// $Revision: 1.1 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
|
// $Locker: $
|
// $State: Exp $
|
// $State: Exp $
|
//
|
//
|
// Change History:
|
// Change History:
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
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//
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//
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//
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//
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//
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//
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//
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//
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//
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//
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//
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//
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|
|
|
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task show_errors;
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task show_errors;
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|
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begin
|
begin
|
|
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$display("\n");
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$display("\n");
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$display(" +--------------------+");
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$display(" +--------------------+");
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$display(" | Total ERRORS: %0d |", error_cnt);
|
$display(" | Total ERRORS: %0d |", error_cnt);
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$display(" +--------------------+");
|
$display(" +--------------------+");
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|
|
end
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end
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endtask
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endtask
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|
|
task recv_packet;
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task recv_packet;
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output [3:0] pid;
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output [3:0] pid;
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output size;
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output size;
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integer del, size,n;
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integer del, size,n;
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reg [15:0] crc16r;
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reg [15:0] crc16r;
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reg [7:0] x,y;
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reg [7:0] x,y;
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|
|
begin
|
begin
|
crc16r = 16'hffff;
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crc16r = 16'hffff;
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utmi_recv_pack(size);
|
utmi_recv_pack(size);
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for(n=1;n<size-2;n=n+1)
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for(n=1;n<size-2;n=n+1)
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begin
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begin
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y = txmem[n];
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y = txmem[n];
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x[7] = y[0];
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x[7] = y[0];
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x[6] = y[1];
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x[6] = y[1];
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x[5] = y[2];
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x[5] = y[2];
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x[4] = y[3];
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x[4] = y[3];
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x[3] = y[4];
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x[3] = y[4];
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x[2] = y[5];
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x[2] = y[5];
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x[1] = y[6];
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x[1] = y[6];
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x[0] = y[7];
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x[0] = y[7];
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crc16r = crc16(crc16r, x);
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crc16r = crc16(crc16r, x);
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end
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end
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|
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y = crc16r[15:8];
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y = crc16r[15:8];
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x[7] = y[0];
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x[7] = y[0];
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x[6] = y[1];
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x[6] = y[1];
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x[5] = y[2];
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x[5] = y[2];
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x[4] = y[3];
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x[4] = y[3];
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x[3] = y[4];
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x[3] = y[4];
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x[2] = y[5];
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x[2] = y[5];
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x[1] = y[6];
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x[1] = y[6];
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x[0] = y[7];
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x[0] = y[7];
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crc16r[15:8] = ~x;
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crc16r[15:8] = ~x;
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|
|
y = crc16r[7:0];
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y = crc16r[7:0];
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x[7] = y[0];
|
x[7] = y[0];
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x[6] = y[1];
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x[6] = y[1];
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x[5] = y[2];
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x[5] = y[2];
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x[4] = y[3];
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x[4] = y[3];
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x[3] = y[4];
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x[3] = y[4];
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x[2] = y[5];
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x[2] = y[5];
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x[1] = y[6];
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x[1] = y[6];
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x[0] = y[7];
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x[0] = y[7];
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crc16r[7:0] = ~x;
|
crc16r[7:0] = ~x;
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|
|
if(crc16r !== {txmem[n], txmem[n+1]})
|
if(crc16r !== {txmem[n], txmem[n+1]})
|
$display("ERROR: CRC Mismatch: Expected: %h, Got: %h%h (%t)",
|
$display("ERROR: CRC Mismatch: Expected: %h, Got: %h%h (%t)",
|
crc16r, txmem[n], txmem[n+1], $time);
|
crc16r, txmem[n], txmem[n+1], $time);
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|
|
for(n=0;n<size-3;n=n+1)
|
for(n=0;n<size-3;n=n+1)
|
buffer1[buffer1_last+n] = txmem[n+1];
|
buffer1[buffer1_last+n] = txmem[n+1];
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buffer1_last = buffer1_last+n;
|
buffer1_last = buffer1_last+n;
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|
|
// Check PID
|
// Check PID
|
x = txmem[0];
|
x = txmem[0];
|
|
|
if(x[7:4] !== ~x[3:0])
|
if(x[7:4] !== ~x[3:0])
|
$display("ERROR: Pid Checksum mismatch: Top: %h Bottom: %h (%t)",
|
$display("ERROR: Pid Checksum mismatch: Top: %h Bottom: %h (%t)",
|
x[7:4], x[3:0], $time);
|
x[7:4], x[3:0], $time);
|
pid = x[3:0];
|
pid = x[3:0];
|
size=size-3;
|
size=size-3;
|
end
|
end
|
endtask
|
endtask
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|
|
|
|
|
|
task send_token;
|
task send_token;
|
input [6:0] fa;
|
input [6:0] fa;
|
input [3:0] ep;
|
input [3:0] ep;
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input [3:0] pid;
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input [3:0] pid;
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|
|
reg [15:0] tmp_data;
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reg [15:0] tmp_data;
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reg [10:0] x,y;
|
reg [10:0] x,y;
|
integer len;
|
integer len;
|
|
|
begin
|
begin
|
|
|
tmp_data = {fa, ep, 5'h0};
|
tmp_data = {fa, ep, 5'h0};
|
if(pid == `USBF_T_PID_ACK) len = 1;
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if(pid == `USBF_T_PID_ACK) len = 1;
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else len = 3;
|
else len = 3;
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|
|
y = {fa, ep};
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y = {fa, ep};
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x[10] = y[4];
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x[10] = y[4];
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x[9] = y[5];
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x[9] = y[5];
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x[8] = y[6];
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x[8] = y[6];
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x[7] = y[7];
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x[7] = y[7];
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x[6] = y[8];
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x[6] = y[8];
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x[5] = y[9];
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x[5] = y[9];
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x[4] = y[10];
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x[4] = y[10];
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x[3] = y[0];
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x[3] = y[0];
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x[2] = y[1];
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x[2] = y[1];
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x[1] = y[2];
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x[1] = y[2];
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x[0] = y[3];
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x[0] = y[3];
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|
|
y[4:0] = crc5( 5'h1f, x );
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y[4:0] = crc5( 5'h1f, x );
|
tmp_data[4:0] = ~y[4:0];
|
tmp_data[4:0] = ~y[4:0];
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tmp_data[15:5] = x;
|
tmp_data[15:5] = x;
|
txmem[0] = {~pid, pid}; // PID
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txmem[0] = {~pid, pid}; // PID
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txmem[1] = { tmp_data[8],tmp_data[9],tmp_data[10],tmp_data[11],
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txmem[1] = { tmp_data[8],tmp_data[9],tmp_data[10],tmp_data[11],
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tmp_data[12],tmp_data[13],tmp_data[14],tmp_data[15]};
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tmp_data[12],tmp_data[13],tmp_data[14],tmp_data[15]};
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txmem[2] = { tmp_data[0],tmp_data[1],tmp_data[2],tmp_data[3],
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txmem[2] = { tmp_data[0],tmp_data[1],tmp_data[2],tmp_data[3],
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tmp_data[4],tmp_data[5],tmp_data[6],tmp_data[7]};
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tmp_data[4],tmp_data[5],tmp_data[6],tmp_data[7]};
|
utmi_send_pack(len);
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utmi_send_pack(len);
|
end
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end
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endtask
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endtask
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|
|
|
|
task send_sof;
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task send_sof;
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input [10:0] frmn;
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input [10:0] frmn;
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|
|
reg [15:0] tmp_data;
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reg [15:0] tmp_data;
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reg [10:0] x,y;
|
reg [10:0] x,y;
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begin
|
begin
|
|
|
y = frmn;
|
y = frmn;
|
x[10] = y[0];
|
x[10] = y[0];
|
x[9] = y[1];
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x[9] = y[1];
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x[8] = y[2];
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x[8] = y[2];
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x[7] = y[3];
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x[7] = y[3];
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x[6] = y[4];
|
x[6] = y[4];
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x[5] = y[5];
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x[5] = y[5];
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x[4] = y[6];
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x[4] = y[6];
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x[3] = y[7];
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x[3] = y[7];
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x[2] = y[8];
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x[2] = y[8];
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x[1] = y[9];
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x[1] = y[9];
|
x[0] = y[10];
|
x[0] = y[10];
|
|
|
tmp_data[15:5] = x;
|
tmp_data[15:5] = x;
|
y[4:0] = crc5( 5'h1f, x );
|
y[4:0] = crc5( 5'h1f, x );
|
tmp_data[4:0] = ~y[4:0];
|
tmp_data[4:0] = ~y[4:0];
|
txmem[0] = {~`USBF_T_PID_SOF, `USBF_T_PID_SOF}; // PID
|
txmem[0] = {~`USBF_T_PID_SOF, `USBF_T_PID_SOF}; // PID
|
txmem[1] = { tmp_data[8],tmp_data[9],tmp_data[10],tmp_data[11],
|
txmem[1] = { tmp_data[8],tmp_data[9],tmp_data[10],tmp_data[11],
|
tmp_data[12],tmp_data[13],tmp_data[14],tmp_data[15]};
|
tmp_data[12],tmp_data[13],tmp_data[14],tmp_data[15]};
|
txmem[2] = { tmp_data[0],tmp_data[1],tmp_data[2],tmp_data[3],
|
txmem[2] = { tmp_data[0],tmp_data[1],tmp_data[2],tmp_data[3],
|
tmp_data[4],tmp_data[5],tmp_data[6],tmp_data[7]};
|
tmp_data[4],tmp_data[5],tmp_data[6],tmp_data[7]};
|
txmem[1] = frmn[7:0];
|
txmem[1] = frmn[7:0];
|
txmem[2] = { tmp_data[0],tmp_data[1],tmp_data[2],tmp_data[3],
|
txmem[2] = { tmp_data[0],tmp_data[1],tmp_data[2],tmp_data[3],
|
tmp_data[4], frmn[10:8] };
|
tmp_data[4], frmn[10:8] };
|
utmi_send_pack(3);
|
utmi_send_pack(3);
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
function [4:0] crc5;
|
function [4:0] crc5;
|
input [4:0] crc_in;
|
input [4:0] crc_in;
|
input [10:0] din;
|
input [10:0] din;
|
reg [4:0] crc_out;
|
reg [4:0] crc_out;
|
|
|
begin
|
begin
|
|
|
crc5[0] = din[10] ^ din[9] ^ din[6] ^ din[5] ^ din[3] ^
|
crc5[0] = din[10] ^ din[9] ^ din[6] ^ din[5] ^ din[3] ^
|
din[0] ^ crc_in[0] ^ crc_in[3] ^ crc_in[4];
|
din[0] ^ crc_in[0] ^ crc_in[3] ^ crc_in[4];
|
crc5[1] = din[10] ^ din[7] ^ din[6] ^ din[4] ^ din[1] ^
|
crc5[1] = din[10] ^ din[7] ^ din[6] ^ din[4] ^ din[1] ^
|
crc_in[0] ^ crc_in[1] ^ crc_in[4];
|
crc_in[0] ^ crc_in[1] ^ crc_in[4];
|
crc5[2] = din[10] ^ din[9] ^ din[8] ^ din[7] ^ din[6] ^
|
crc5[2] = din[10] ^ din[9] ^ din[8] ^ din[7] ^ din[6] ^
|
din[3] ^ din[2] ^ din[0] ^ crc_in[0] ^ crc_in[1] ^
|
din[3] ^ din[2] ^ din[0] ^ crc_in[0] ^ crc_in[1] ^
|
crc_in[2] ^ crc_in[3] ^ crc_in[4];
|
crc_in[2] ^ crc_in[3] ^ crc_in[4];
|
crc5[3] = din[10] ^ din[9] ^ din[8] ^ din[7] ^ din[4] ^ din[3] ^
|
crc5[3] = din[10] ^ din[9] ^ din[8] ^ din[7] ^ din[4] ^ din[3] ^
|
din[1] ^ crc_in[1] ^ crc_in[2] ^ crc_in[3] ^ crc_in[4];
|
din[1] ^ crc_in[1] ^ crc_in[2] ^ crc_in[3] ^ crc_in[4];
|
crc5[4] = din[10] ^ din[9] ^ din[8] ^ din[5] ^ din[4] ^ din[2] ^
|
crc5[4] = din[10] ^ din[9] ^ din[8] ^ din[5] ^ din[4] ^ din[2] ^
|
crc_in[2] ^ crc_in[3] ^ crc_in[4];
|
crc_in[2] ^ crc_in[3] ^ crc_in[4];
|
end
|
end
|
endfunction
|
endfunction
|
|
|
|
|
task send_data;
|
task send_data;
|
input [3:0] pid;
|
input [3:0] pid;
|
input len;
|
input len;
|
input mode;
|
input mode;
|
integer n, len, mode, delay;
|
integer n, len, mode, delay;
|
reg [15:0] crc16r;
|
reg [15:0] crc16r;
|
reg [7:0] x,y;
|
reg [7:0] x,y;
|
|
|
begin
|
begin
|
txmem[0] = {~pid, pid}; // PID
|
txmem[0] = {~pid, pid}; // PID
|
crc16r = 16'hffff;
|
crc16r = 16'hffff;
|
for(n=0;n<len;n=n+1)
|
for(n=0;n<len;n=n+1)
|
begin
|
begin
|
if(mode==1) y = buffer1[buffer1_last+n];
|
if(mode==1) y = buffer1[buffer1_last+n];
|
else y = n;
|
else y = n;
|
x[7] = y[0];
|
x[7] = y[0];
|
x[6] = y[1];
|
x[6] = y[1];
|
x[5] = y[2];
|
x[5] = y[2];
|
x[4] = y[3];
|
x[4] = y[3];
|
x[3] = y[4];
|
x[3] = y[4];
|
x[2] = y[5];
|
x[2] = y[5];
|
x[1] = y[6];
|
x[1] = y[6];
|
x[0] = y[7];
|
x[0] = y[7];
|
txmem[n+1] = y;
|
txmem[n+1] = y;
|
crc16r = crc16(crc16r, x);
|
crc16r = crc16(crc16r, x);
|
end
|
end
|
|
|
buffer1_last = buffer1_last + n;
|
buffer1_last = buffer1_last + n;
|
y = crc16r[15:8];
|
y = crc16r[15:8];
|
x[7] = y[0];
|
x[7] = y[0];
|
x[6] = y[1];
|
x[6] = y[1];
|
x[5] = y[2];
|
x[5] = y[2];
|
x[4] = y[3];
|
x[4] = y[3];
|
x[3] = y[4];
|
x[3] = y[4];
|
x[2] = y[5];
|
x[2] = y[5];
|
x[1] = y[6];
|
x[1] = y[6];
|
x[0] = y[7];
|
x[0] = y[7];
|
txmem[n+1] = ~x;
|
txmem[n+1] = ~x;
|
|
|
y = crc16r[7:0];
|
y = crc16r[7:0];
|
x[7] = y[0];
|
x[7] = y[0];
|
x[6] = y[1];
|
x[6] = y[1];
|
x[5] = y[2];
|
x[5] = y[2];
|
x[4] = y[3];
|
x[4] = y[3];
|
x[3] = y[4];
|
x[3] = y[4];
|
x[2] = y[5];
|
x[2] = y[5];
|
x[1] = y[6];
|
x[1] = y[6];
|
x[0] = y[7];
|
x[0] = y[7];
|
txmem[n+2] = ~x;
|
txmem[n+2] = ~x;
|
utmi_send_pack(len+3);
|
utmi_send_pack(len+3);
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
function [15:0] crc16;
|
function [15:0] crc16;
|
input [15:0] crc_in;
|
input [15:0] crc_in;
|
input [7:0] din;
|
input [7:0] din;
|
reg [15:0] crc_out;
|
reg [15:0] crc_out;
|
|
|
begin
|
begin
|
crc_out[0] = din[7] ^ din[6] ^ din[5] ^ din[4] ^ din[3] ^
|
crc_out[0] = din[7] ^ din[6] ^ din[5] ^ din[4] ^ din[3] ^
|
din[2] ^ din[1] ^ din[0] ^ crc_in[8] ^ crc_in[9] ^
|
din[2] ^ din[1] ^ din[0] ^ crc_in[8] ^ crc_in[9] ^
|
crc_in[10] ^ crc_in[11] ^ crc_in[12] ^ crc_in[13] ^
|
crc_in[10] ^ crc_in[11] ^ crc_in[12] ^ crc_in[13] ^
|
crc_in[14] ^ crc_in[15];
|
crc_in[14] ^ crc_in[15];
|
crc_out[1] = din[7] ^ din[6] ^ din[5] ^ din[4] ^ din[3] ^ din[2] ^
|
crc_out[1] = din[7] ^ din[6] ^ din[5] ^ din[4] ^ din[3] ^ din[2] ^
|
din[1] ^ crc_in[9] ^ crc_in[10] ^ crc_in[11] ^
|
din[1] ^ crc_in[9] ^ crc_in[10] ^ crc_in[11] ^
|
crc_in[12] ^ crc_in[13] ^ crc_in[14] ^ crc_in[15];
|
crc_in[12] ^ crc_in[13] ^ crc_in[14] ^ crc_in[15];
|
crc_out[2] = din[1] ^ din[0] ^ crc_in[8] ^ crc_in[9];
|
crc_out[2] = din[1] ^ din[0] ^ crc_in[8] ^ crc_in[9];
|
crc_out[3] = din[2] ^ din[1] ^ crc_in[9] ^ crc_in[10];
|
crc_out[3] = din[2] ^ din[1] ^ crc_in[9] ^ crc_in[10];
|
crc_out[4] = din[3] ^ din[2] ^ crc_in[10] ^ crc_in[11];
|
crc_out[4] = din[3] ^ din[2] ^ crc_in[10] ^ crc_in[11];
|
crc_out[5] = din[4] ^ din[3] ^ crc_in[11] ^ crc_in[12];
|
crc_out[5] = din[4] ^ din[3] ^ crc_in[11] ^ crc_in[12];
|
crc_out[6] = din[5] ^ din[4] ^ crc_in[12] ^ crc_in[13];
|
crc_out[6] = din[5] ^ din[4] ^ crc_in[12] ^ crc_in[13];
|
crc_out[7] = din[6] ^ din[5] ^ crc_in[13] ^ crc_in[14];
|
crc_out[7] = din[6] ^ din[5] ^ crc_in[13] ^ crc_in[14];
|
crc_out[8] = din[7] ^ din[6] ^ crc_in[0] ^ crc_in[14] ^ crc_in[15];
|
crc_out[8] = din[7] ^ din[6] ^ crc_in[0] ^ crc_in[14] ^ crc_in[15];
|
crc_out[9] = din[7] ^ crc_in[1] ^ crc_in[15];
|
crc_out[9] = din[7] ^ crc_in[1] ^ crc_in[15];
|
crc_out[10] = crc_in[2];
|
crc_out[10] = crc_in[2];
|
crc_out[11] = crc_in[3];
|
crc_out[11] = crc_in[3];
|
crc_out[12] = crc_in[4];
|
crc_out[12] = crc_in[4];
|
crc_out[13] = crc_in[5];
|
crc_out[13] = crc_in[5];
|
crc_out[14] = crc_in[6];
|
crc_out[14] = crc_in[6];
|
crc_out[15] = din[7] ^ din[6] ^ din[5] ^ din[4] ^ din[3] ^ din[2] ^
|
crc_out[15] = din[7] ^ din[6] ^ din[5] ^ din[4] ^ din[3] ^ din[2] ^
|
din[1] ^ din[0] ^ crc_in[7] ^ crc_in[8] ^ crc_in[9] ^
|
din[1] ^ din[0] ^ crc_in[7] ^ crc_in[8] ^ crc_in[9] ^
|
crc_in[10] ^ crc_in[11] ^ crc_in[12] ^ crc_in[13] ^
|
crc_in[10] ^ crc_in[11] ^ crc_in[12] ^ crc_in[13] ^
|
crc_in[14] ^ crc_in[15];
|
crc_in[14] ^ crc_in[15];
|
crc16 = crc_out;
|
crc16 = crc_out;
|
end
|
end
|
endfunction
|
endfunction
|
|
|
///////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////
|
//
|
//
|
// UTMI Low level Tasks
|
// UTMI Low level Tasks
|
//
|
//
|
|
|
task utmi_send_pack;
|
task utmi_send_pack;
|
input size;
|
input size;
|
integer n,size;
|
integer n,size;
|
|
|
begin
|
begin
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
tb_tx_valid = 1'b1;
|
tb_tx_valid = 1'b1;
|
for(n=0;n<size;n=n+1)
|
for(n=0;n<size;n=n+1)
|
begin
|
begin
|
tb_txdata = txmem[n];
|
tb_txdata = txmem[n];
|
@(posedge clk);
|
@(posedge clk);
|
#2;
|
#2;
|
while(!tb_tx_ready) @(posedge clk);
|
while(!tb_tx_ready) @(posedge clk);
|
#1;
|
#1;
|
end
|
end
|
tb_tx_valid = 1'b0;
|
tb_tx_valid = 1'b0;
|
@(posedge clk);
|
@(posedge clk);
|
end
|
end
|
endtask
|
endtask
|
|
|
task utmi_recv_pack;
|
task utmi_recv_pack;
|
output size;
|
output size;
|
integer size;
|
integer size;
|
|
|
begin
|
begin
|
size = 0;
|
size = 0;
|
while(!tb_rx_active) @(posedge clk);
|
while(!tb_rx_active) @(posedge clk);
|
while(tb_rx_active)
|
while(tb_rx_active)
|
begin
|
begin
|
#1;
|
#1;
|
while(!tb_rx_valid & tb_rx_active) @(posedge clk);
|
while(!tb_rx_valid & tb_rx_active) @(posedge clk);
|
|
|
if(tb_rx_valid & tb_rx_active)
|
if(tb_rx_valid & tb_rx_active)
|
begin
|
begin
|
txmem[size] = tb_rxdata;
|
txmem[size] = tb_rxdata;
|
size = size + 1;
|
size = size + 1;
|
end
|
end
|
@(posedge clk);
|
@(posedge clk);
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
