------------------------------------------------------------------
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------------------------------------------------------------------
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-- Universal dongle board source code
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-- Universal dongle board source code
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--
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--
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-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>
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-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>
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--
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--
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-- This source code is free hardware; you can redistribute it and/or
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-- This source code is free hardware; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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-- version 2.1 of the License, or (at your option) any later version.
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--
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--
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-- This source code is distributed in the hope that it will be useful,
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-- This source code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Lesser General Public License for more details.
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-- Lesser General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU Lesser General Public
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-- You should have received a copy of the GNU Lesser General Public
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-- License along with this library; if not, write to the Free Software
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-- License along with this library; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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--
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--
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-- The complete text of the GNU Lesser General Public License can be found in
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-- The complete text of the GNU Lesser General Public License can be found in
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-- the file 'lesser.txt'.
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-- the file 'lesser.txt'.
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-- bit 0,A
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-- bit 0,A
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-- ----------
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-- ----------
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-- | |
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-- | |
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-- | |
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-- | |
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-- 5,F| | 1,B
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-- 5,F| | 1,B
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-- | 6,G |
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-- | 6,G |
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-- ----------
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-- ----------
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-- | |
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-- | |
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-- | |
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-- | |
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-- 4,E| | 2,C
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-- 4,E| | 2,C
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-- | 3,D |
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-- | 3,D |
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-- ----------
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-- ----------
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-- # 7,H
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-- # 7,H
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-- Select signal order
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-- Select signal order
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-- --- --- --- ---
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-- --- --- --- ---
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-- | | | | | | | |
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-- | | | | | | | |
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-- | | | | | | | |
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-- | | | | | | | |
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-- --- --- --- ---
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-- --- --- --- ---
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-- | | | | | | | |
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-- | | | | | | | |
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-- | | | | | | | |
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-- | | | | | | | |
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-- --- --- --- ---
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-- --- --- --- ---
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-- sel(3) sel(2) sel(1) sel(0)
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-- sel(3) sel(2) sel(1) sel(0)
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_arith.all;
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entity byte_scan is
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entity byte_scan is
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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hi_seg_1 : in std_logic_vector(7 downto 0);
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hi_seg_1 : in std_logic_vector(7 downto 0);
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lo_seg_1 : in std_logic_vector(7 downto 0);
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lo_seg_1 : in std_logic_vector(7 downto 0);
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hi_seg_0 : in std_logic_vector(7 downto 0);
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hi_seg_0 : in std_logic_vector(7 downto 0);
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lo_seg_0 : in std_logic_vector(7 downto 0);
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lo_seg_0 : in std_logic_vector(7 downto 0);
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seg_out : out std_logic_vector(7 downto 0);
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seg_out : out std_logic_vector(7 downto 0);
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sel_out : out std_logic_vector(3 downto 0)
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sel_out : out std_logic_vector(3 downto 0)
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);
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);
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end byte_scan;
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end byte_scan;
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architecture rtl of byte_scan is
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architecture rtl of byte_scan is
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signal sel_p : std_logic_vector(3 downto 0);
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signal sel_p : std_logic_vector(3 downto 0);
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signal count : std_logic_vector(1 downto 0):="00";
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signal count : std_logic_vector(1 downto 0):="00";
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signal hi_seg_1_3 : std_logic_vector(7 downto 0);
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signal hi_seg_1_3 : std_logic_vector(7 downto 0);
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signal lo_seg_1_3 : std_logic_vector(7 downto 0);
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signal lo_seg_1_3 : std_logic_vector(7 downto 0);
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signal hi_seg_0_2 : std_logic_vector(7 downto 0);
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signal hi_seg_0_2 : std_logic_vector(7 downto 0);
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signal lo_seg_0_2 : std_logic_vector(7 downto 0);
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signal lo_seg_0_2 : std_logic_vector(7 downto 0);
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begin -- rtl
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begin -- rtl
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hi_seg_1_3 <= hi_seg_1; -- when sel_hib_n ='1' else hi_seg_3;
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hi_seg_1_3 <= hi_seg_1; -- when sel_hib_n ='1' else hi_seg_3;
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lo_seg_1_3 <= lo_seg_1; --when sel_hib_n ='1' else lo_seg_3;
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lo_seg_1_3 <= lo_seg_1; --when sel_hib_n ='1' else lo_seg_3;
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hi_seg_0_2 <= hi_seg_0; --when sel_hib_n ='1' else hi_seg_2;
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hi_seg_0_2 <= hi_seg_0; --when sel_hib_n ='1' else hi_seg_2;
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lo_seg_0_2 <= lo_seg_0; --when sel_hib_n ='1' else lo_seg_2;
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lo_seg_0_2 <= lo_seg_0; --when sel_hib_n ='1' else lo_seg_2;
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seg_out <=hi_seg_1_3 when count="01" else
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seg_out <=hi_seg_1_3 when count="01" else
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lo_seg_1_3 when count="10" else
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lo_seg_1_3 when count="10" else
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hi_seg_0_2 when count="11" else
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hi_seg_0_2 when count="11" else
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lo_seg_0_2 when count="00";
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lo_seg_0_2 when count="00";
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sel_out <= sel_p;
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sel_out <= sel_p;
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sel_p <= "1110" when count="00" else
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sel_p <= "1110" when count="00" else
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"0111" when count="01" else
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"0111" when count="01" else
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"1011" when count="10" else
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"1011" when count="10" else
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"1101" when count="11";
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"1101" when count="11";
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process (clk) --enable the scanning while in reset (simulation will be incorrect)
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process (clk) --enable the scanning while in reset (simulation will be incorrect)
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begin -- process
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begin -- process
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if clk'event and clk = '1' then -- rising clock edge
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if clk'event and clk = '1' then -- rising clock edge
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count <= count + 1;
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count <= count + 1;
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end if;
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end if;
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end process;
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end process;
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end rtl;
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end rtl;
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