------------------------------------------------------------------
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------------------------------------------------------------------
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-- Universal dongle board source code
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-- Universal dongle board source code
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--
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--
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-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>
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-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>
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--
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--
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-- This source code is free hardware; you can redistribute it and/or
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-- This source code is free hardware; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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-- version 2.1 of the License, or (at your option) any later version.
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--
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--
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-- This source code is distributed in the hope that it will be useful,
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-- This source code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Lesser General Public License for more details.
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-- Lesser General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU Lesser General Public
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-- You should have received a copy of the GNU Lesser General Public
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-- License along with this library; if not, write to the Free Software
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-- License along with this library; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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--
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--
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-- The complete text of the GNU Lesser General Public License can be found in
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-- The complete text of the GNU Lesser General Public License can be found in
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-- the file 'lesser.txt'.
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-- the file 'lesser.txt'.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Company:
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-- Company:
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-- Engineer:
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-- Engineer:
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--
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--
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-- Create Date: 17:35:11 10/09/2006
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-- Create Date: 17:35:11 10/09/2006
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-- Design Name: lpc_iow
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-- Design Name: lpc_iow
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-- Module Name: C:/projects/USB_dongle/beh/lpc_byte_test.vhd
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-- Module Name: C:/projects/USB_dongle/beh/lpc_byte_test.vhd
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-- Project Name: simulation
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-- Project Name: simulation
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-- Target Device:
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-- Target Device:
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-- Tool versions:
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-- Tool versions:
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-- Description:
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-- Description:
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--
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--
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-- VHDL Test Bench Created by ISE for module: lpc_iow
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-- VHDL Test Bench Created by ISE for module: lpc_iow
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--
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--
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-- Dependencies:
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-- Dependencies:
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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-- Additional Comments:
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-- Additional Comments:
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--
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--
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-- Notes:
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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-- simulation model.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_unsigned.all;
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USE ieee.std_logic_unsigned.all;
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USE ieee.numeric_std.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY lpc_byte_test_vhd IS
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ENTITY lpc_byte_test_vhd IS
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END lpc_byte_test_vhd;
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END lpc_byte_test_vhd;
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ARCHITECTURE behavior OF lpc_byte_test_vhd IS
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ARCHITECTURE behavior OF lpc_byte_test_vhd IS
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-- Component Declaration for the Unit Under Test (UUT)
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT lpc_iow
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COMPONENT lpc_iow
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PORT(
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PORT(
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lreset_n : IN std_logic;
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lreset_n : IN std_logic;
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lclk : IN std_logic;
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lclk : IN std_logic;
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lena_mem_r : in std_logic; --enable lpc regular memory read cycles also (default is only LPC firmware read)
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lena_mem_r : in std_logic; --enable lpc regular memory read cycles also (default is only LPC firmware read)
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lena_reads : in std_logic; --enable read capabilities
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lena_reads : in std_logic; --enable read capabilities
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lad_i : IN std_logic_vector(3 downto 0);
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lad_i : IN std_logic_vector(3 downto 0);
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lframe_n : IN std_logic;
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lframe_n : IN std_logic;
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lpc_data_i : IN std_logic_vector(7 downto 0);
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lpc_data_i : IN std_logic_vector(7 downto 0);
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lpc_ack : IN std_logic;
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lpc_ack : IN std_logic;
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lad_o : OUT std_logic_vector(3 downto 0);
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lad_o : OUT std_logic_vector(3 downto 0);
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lad_oe : OUT std_logic;
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lad_oe : OUT std_logic;
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lpc_addr : OUT std_logic_vector(23 downto 0);
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lpc_addr : OUT std_logic_vector(23 downto 0);
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lpc_wr : OUT std_logic;
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lpc_wr : OUT std_logic;
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lpc_data_o : OUT std_logic_vector(7 downto 0);
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lpc_data_o : OUT std_logic_vector(7 downto 0);
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lpc_val : OUT std_logic
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lpc_val : OUT std_logic
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);
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);
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END COMPONENT;
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END COMPONENT;
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--Inputs
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--Inputs
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SIGNAL lreset_n : std_logic := '0';
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SIGNAL lreset_n : std_logic := '0';
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SIGNAL lclk : std_logic := '0';
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SIGNAL lclk : std_logic := '0';
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SIGNAL lena_mem_r : std_logic:='1'; --enable lpc regular memory read cycles also (default is only LPC firmware read)
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SIGNAL lena_mem_r : std_logic:='1'; --enable lpc regular memory read cycles also (default is only LPC firmware read)
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SIGNAL lena_reads : std_logic:='1'; --enable read capabilities
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SIGNAL lena_reads : std_logic:='1'; --enable read capabilities
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SIGNAL lframe_n : std_logic := '1';
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SIGNAL lframe_n : std_logic := '1';
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SIGNAL lpc_ack : std_logic := '0';
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SIGNAL lpc_ack : std_logic := '0';
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SIGNAL lad_i : std_logic_vector(3 downto 0) := (others=>'0');
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SIGNAL lad_i : std_logic_vector(3 downto 0) := (others=>'0');
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SIGNAL lpc_data_i : std_logic_vector(7 downto 0) := (others=>'0');
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SIGNAL lpc_data_i : std_logic_vector(7 downto 0) := (others=>'0');
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--Outputs
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--Outputs
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SIGNAL lad_o : std_logic_vector(3 downto 0);
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SIGNAL lad_o : std_logic_vector(3 downto 0);
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SIGNAL lad_oe : std_logic;
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SIGNAL lad_oe : std_logic;
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SIGNAL lpc_addr : std_logic_vector(23 downto 0);
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SIGNAL lpc_addr : std_logic_vector(23 downto 0);
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SIGNAL lpc_wr : std_logic;
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SIGNAL lpc_wr : std_logic;
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SIGNAL lpc_data_o : std_logic_vector(7 downto 0);
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SIGNAL lpc_data_o : std_logic_vector(7 downto 0);
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SIGNAL lpc_val : std_logic;
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SIGNAL lpc_val : std_logic;
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BEGIN
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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-- Instantiate the Unit Under Test (UUT)
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uut: lpc_iow PORT MAP(
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uut: lpc_iow PORT MAP(
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lreset_n => lreset_n,
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lreset_n => lreset_n,
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lclk => lclk,
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lclk => lclk,
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lena_mem_r=> lena_mem_r,
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lena_mem_r=> lena_mem_r,
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lena_reads => lena_reads,
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lena_reads => lena_reads,
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lad_i => lad_i,
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lad_i => lad_i,
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lad_o => lad_o,
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lad_o => lad_o,
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lad_oe => lad_oe,
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lad_oe => lad_oe,
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lframe_n => lframe_n,
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lframe_n => lframe_n,
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lpc_addr => lpc_addr,
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lpc_addr => lpc_addr,
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lpc_wr => lpc_wr,
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lpc_wr => lpc_wr,
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lpc_data_i => lpc_data_i,
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lpc_data_i => lpc_data_i,
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lpc_data_o => lpc_data_o,
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lpc_data_o => lpc_data_o,
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lpc_val => lpc_val,
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lpc_val => lpc_val,
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lpc_ack => lpc_ack
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lpc_ack => lpc_ack
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);
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);
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clocker : process is
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clocker : process is
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begin
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begin
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wait for 15 ns;
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wait for 15 ns;
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lclk <=not (lclk);
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lclk <=not (lclk);
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end process clocker;
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end process clocker;
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VCI_ACK : process is
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VCI_ACK : process is
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begin
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begin
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wait until lpc_val='1';
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wait until lpc_val='1';
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wait for 100 ns;
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wait for 100 ns;
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lpc_ack <='1';
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lpc_ack <='1';
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wait until lpc_val='0';
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wait until lpc_val='0';
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lpc_ack <='0';
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lpc_ack <='0';
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end process VCI_ACK;
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end process VCI_ACK;
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tb : PROCESS
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tb : PROCESS
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BEGIN
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BEGIN
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-- Wait 100 ns for global reset to finish
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-- Wait 100 ns for global reset to finish
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wait for 500 ns;
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wait for 500 ns;
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lreset_n <='1';
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lreset_n <='1';
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-- Place stimulus here
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-- Place stimulus here
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wait until lclk='0'; --cycle 1
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wait until lclk='0'; --cycle 1
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wait until lclk='1';
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wait until lclk='1';
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lad_i <="0000";
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lad_i <="0000";
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lframe_n <='0';
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lframe_n <='0';
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wait until lclk='0'; --cycle 2
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wait until lclk='0'; --cycle 2
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wait until lclk='1';
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wait until lclk='1';
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lad_i <="0010"; --LPC IO write
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lad_i <="0010"; --LPC IO write
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lframe_n <='1';
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lframe_n <='1';
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wait until lclk='0'; --cycle 3
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wait until lclk='0'; --cycle 3
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wait until lclk='1';
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wait until lclk='1';
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lad_i <=x"0"; --address nibble 1
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lad_i <=x"0"; --address nibble 1
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wait until lclk='0'; --cycle 4
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wait until lclk='0'; --cycle 4
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wait until lclk='1';
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wait until lclk='1';
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lad_i <=x"0"; --address nibble 2
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lad_i <=x"0"; --address nibble 2
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wait until lclk='0'; --cycle 5
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wait until lclk='0'; --cycle 5
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wait until lclk='1';
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wait until lclk='1';
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lad_i <=x"8"; --address nibble 3
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lad_i <=x"8"; --address nibble 3
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wait until lclk='0'; --cycle 6
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wait until lclk='0'; --cycle 6
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wait until lclk='1';
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wait until lclk='1';
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lad_i <=x"0"; --address nibble 4
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lad_i <=x"0"; --address nibble 4
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wait until lclk='0'; --cycle 7
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wait until lclk='0'; --cycle 7
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wait until lclk='1';
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wait until lclk='1';
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lad_i <=x"A"; --data nibble 1
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lad_i <=x"A"; --data nibble 1
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wait until lclk='0'; --cycle 8
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wait until lclk='0'; --cycle 8
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wait until lclk='1';
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wait until lclk='1';
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lad_i <=x"5"; --data nibble 2
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lad_i <=x"5"; --data nibble 2
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wait until lclk='0'; --cycle 9
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wait until lclk='0'; --cycle 9
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wait until lclk='1';
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wait until lclk='1';
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lad_i <=x"F"; --TAR 1
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lad_i <=x"F"; --TAR 1
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wait until lclk='0'; --cycle 10
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wait until lclk='0'; --cycle 10
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wait until lclk='1';
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wait until lclk='1';
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if lad_oe='0' then --TAR 2
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if lad_oe='0' then --TAR 2
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else
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else
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report "LPC error found on TAR cycle no 0xF on lad_o";
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report "LPC error found on TAR cycle no 0xF on lad_o";
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lframe_n <='0';
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lframe_n <='0';
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end if;
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end if;
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wait until lclk='0'; --cycle 11
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wait until lclk='0'; --cycle 11
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wait until lclk='1';
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wait until lclk='1';
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wait until lad_o=x"6";
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wait until lad_o=x"6";
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while(lad_o=x"6") loop
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while(lad_o=x"6") loop
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wait until lclk='0'; --cycle 11
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wait until lclk='0'; --cycle 11
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wait until lclk='1';
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wait until lclk='1';
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end loop;
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end loop;
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if (lad_o=x"0") and lad_oe='1' then --SYNC
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if (lad_o=x"0") and lad_oe='1' then --SYNC
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else
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else
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report "LPC error found on SYNC cycle no 0x0 on lad_o";
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report "LPC error found on SYNC cycle no 0x0 on lad_o";
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lframe_n <='0';
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lframe_n <='0';
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end if;
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end if;
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wait until lclk='0'; --cycle 12
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wait until lclk='0'; --cycle 12
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wait until lclk='1';
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wait until lclk='1';
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if (lad_o=x"F") and lad_oe='1' then --TARL 1
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if (lad_o=x"F") and lad_oe='1' then --TARL 1
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else
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else
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report "LPC error found on TAR_L cycle no 0xF on lad_o";
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report "LPC error found on TAR_L cycle no 0xF on lad_o";
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lframe_n <='0';
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lframe_n <='0';
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end if;
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end if;
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wait until lclk='0'; --cycle 13
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wait until lclk='0'; --cycle 13
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wait until lclk='1';
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wait until lclk='1';
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lad_i <=x"F"; --TARL 2
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lad_i <=x"F"; --TARL 2
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lframe_n <='1';
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lframe_n <='1';
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wait; -- will wait forever
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wait; -- will wait forever
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END PROCESS;
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END PROCESS;
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END;
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END;
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