------------------------------------------------------------------
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------------------------------------------------------------------
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-- Universal dongle board source code
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-- Universal dongle board source code
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--
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--
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-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>
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-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>
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--
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--
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-- This source code is free hardware; you can redistribute it and/or
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-- This source code is free hardware; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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-- version 2.1 of the License, or (at your option) any later version.
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--
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--
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-- This source code is distributed in the hope that it will be useful,
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-- This source code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Lesser General Public License for more details.
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-- Lesser General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU Lesser General Public
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-- You should have received a copy of the GNU Lesser General Public
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-- License along with this library; if not, write to the Free Software
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-- License along with this library; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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--
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--
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-- The complete text of the GNU Lesser General Public License can be found in
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-- The complete text of the GNU Lesser General Public License can be found in
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-- the file 'lesser.txt'.
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-- the file 'lesser.txt'.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Company:
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-- Company:
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-- Engineer:
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-- Engineer:
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--
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--
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-- Create Date: 18:17:32 09/28/2006
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-- Create Date: 18:17:32 09/28/2006
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-- Design Name: design_top
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-- Design Name: design_top
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-- Module Name: C:/projects/USB_dongle/beh/toplevel_usb_test.vhd
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-- Module Name: C:/projects/USB_dongle/beh/toplevel_usb_test.vhd
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-- Project Name: simulation
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-- Project Name: simulation
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-- Target Device:
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-- Target Device:
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-- Tool versions:
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-- Tool versions:
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-- Description:
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-- Description:
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--
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--
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-- VHDL Test Bench Created by ISE for module: design_top
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-- VHDL Test Bench Created by ISE for module: design_top
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--
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--
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-- Dependencies:
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-- Dependencies:
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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-- Additional Comments:
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-- Additional Comments:
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--
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--
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-- Notes:
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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-- simulation model.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_unsigned.all;
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USE ieee.std_logic_unsigned.all;
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USE ieee.numeric_std.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY toplevel_usb_test_vhd IS
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ENTITY toplevel_usb_test_vhd IS
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END toplevel_usb_test_vhd;
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END toplevel_usb_test_vhd;
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|
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ARCHITECTURE behavior OF toplevel_usb_test_vhd IS
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ARCHITECTURE behavior OF toplevel_usb_test_vhd IS
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-- Component Declaration for the Unit Under Test (UUT)
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT design_top
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COMPONENT design_top
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PORT(
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PORT(
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sys_clk : IN std_logic;
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sys_clk : IN std_logic;
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resetn : IN std_logic;
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resetn : IN std_logic;
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hdr : OUT std_logic_vector(10 downto 0);
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hdr : OUT std_logic_vector(10 downto 0);
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alt_clk : IN std_logic;
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alt_clk : IN std_logic;
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mode : IN std_logic_vector(1 downto 0);
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mode : IN std_logic_vector(1 downto 0);
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lreset_n : IN std_logic;
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lreset_n : IN std_logic;
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lclk : IN std_logic;
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lclk : IN std_logic;
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fl_sts : IN std_logic;
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fl_sts : IN std_logic;
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usb_txe_n : IN std_logic;
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usb_txe_n : IN std_logic;
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usb_rxf_n : IN std_logic;
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usb_rxf_n : IN std_logic;
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lad : INOUT std_logic_vector(3 downto 0);
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lad : INOUT std_logic_vector(3 downto 0);
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lframe_n : INOUT std_logic;
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lframe_n : INOUT std_logic;
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fl_data : INOUT std_logic_vector(15 downto 0);
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fl_data : INOUT std_logic_vector(15 downto 0);
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usb_bd : INOUT std_logic_vector(7 downto 0);
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usb_bd : INOUT std_logic_vector(7 downto 0);
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seg_out : OUT std_logic_vector(7 downto 0);
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seg_out : OUT std_logic_vector(7 downto 0);
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scn_seg : OUT std_logic_vector(3 downto 0);
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scn_seg : OUT std_logic_vector(3 downto 0);
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led_green : OUT std_logic;
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led_green : OUT std_logic;
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led_red : OUT std_logic;
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led_red : OUT std_logic;
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fl_addr : OUT std_logic_vector(23 downto 0);
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fl_addr : OUT std_logic_vector(23 downto 0);
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fl_ce_n : OUT std_logic;
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fl_ce_n : OUT std_logic;
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fl_oe_n : OUT std_logic;
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fl_oe_n : OUT std_logic;
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fl_we_n : OUT std_logic;
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fl_we_n : OUT std_logic;
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fl_rp_n : OUT std_logic;
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fl_rp_n : OUT std_logic;
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usb_rd_n : OUT std_logic;
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usb_rd_n : OUT std_logic;
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usb_wr : OUT std_logic
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usb_wr : OUT std_logic
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);
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);
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END COMPONENT;
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END COMPONENT;
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--Inputs
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--Inputs
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SIGNAL sys_clk : std_logic := '0';
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SIGNAL sys_clk : std_logic := '0';
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SIGNAL resetn : std_logic := '0';
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SIGNAL resetn : std_logic := '0';
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SIGNAL alt_clk : std_logic := '0';
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SIGNAL alt_clk : std_logic := '0';
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SIGNAL lreset_n : std_logic := '0';
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SIGNAL lreset_n : std_logic := '0';
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SIGNAL lclk : std_logic := '0';
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SIGNAL lclk : std_logic := '0';
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SIGNAL fl_sts : std_logic := '0';
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SIGNAL fl_sts : std_logic := '0';
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SIGNAL usb_txe_n : std_logic := '0';
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SIGNAL usb_txe_n : std_logic := '0';
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SIGNAL usb_rxf_n : std_logic := '0';
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SIGNAL usb_rxf_n : std_logic := '0';
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SIGNAL hdr : std_logic_vector(10 downto 0);
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SIGNAL hdr : std_logic_vector(10 downto 0);
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SIGNAL mode : std_logic_vector(1 downto 0) := (others=>'0');
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SIGNAL mode : std_logic_vector(1 downto 0) := (others=>'0');
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--BiDirs
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--BiDirs
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SIGNAL lad : std_logic_vector(3 downto 0);
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SIGNAL lad : std_logic_vector(3 downto 0);
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SIGNAL lframe_n : std_logic;
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SIGNAL lframe_n : std_logic;
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SIGNAL fl_data : std_logic_vector(15 downto 0);
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SIGNAL fl_data : std_logic_vector(15 downto 0);
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SIGNAL usb_bd : std_logic_vector(7 downto 0);
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SIGNAL usb_bd : std_logic_vector(7 downto 0);
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--Outputs
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--Outputs
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SIGNAL seg_out : std_logic_vector(7 downto 0);
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SIGNAL seg_out : std_logic_vector(7 downto 0);
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SIGNAL scn_seg : std_logic_vector(3 downto 0);
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SIGNAL scn_seg : std_logic_vector(3 downto 0);
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SIGNAL led_green : std_logic;
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SIGNAL led_green : std_logic;
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SIGNAL led_red : std_logic;
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SIGNAL led_red : std_logic;
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SIGNAL fl_addr : std_logic_vector(23 downto 0);
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SIGNAL fl_addr : std_logic_vector(23 downto 0);
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SIGNAL fl_ce_n : std_logic;
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SIGNAL fl_ce_n : std_logic;
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SIGNAL fl_oe_n : std_logic;
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SIGNAL fl_oe_n : std_logic;
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SIGNAL fl_we_n : std_logic;
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SIGNAL fl_we_n : std_logic;
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SIGNAL fl_rp_n : std_logic;
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SIGNAL fl_rp_n : std_logic;
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SIGNAL usb_rd_n : std_logic;
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SIGNAL usb_rd_n : std_logic;
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SIGNAL usb_wr : std_logic;
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SIGNAL usb_wr : std_logic;
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BEGIN
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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-- Instantiate the Unit Under Test (UUT)
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uut: design_top PORT MAP(
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uut: design_top PORT MAP(
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sys_clk => sys_clk,
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sys_clk => sys_clk,
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resetn => resetn,
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resetn => resetn,
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hdr => hdr,
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hdr => hdr,
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alt_clk => alt_clk,
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alt_clk => alt_clk,
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mode => mode,
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mode => mode,
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lad => lad,
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lad => lad,
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lframe_n => lframe_n,
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lframe_n => lframe_n,
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lreset_n => lreset_n,
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lreset_n => lreset_n,
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lclk => lclk,
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lclk => lclk,
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seg_out => seg_out,
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seg_out => seg_out,
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scn_seg => scn_seg,
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scn_seg => scn_seg,
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led_green => led_green,
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led_green => led_green,
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led_red => led_red,
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led_red => led_red,
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fl_addr => fl_addr,
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fl_addr => fl_addr,
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fl_ce_n => fl_ce_n,
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fl_ce_n => fl_ce_n,
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fl_oe_n => fl_oe_n,
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fl_oe_n => fl_oe_n,
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fl_we_n => fl_we_n,
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fl_we_n => fl_we_n,
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fl_data => fl_data,
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fl_data => fl_data,
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fl_rp_n => fl_rp_n,
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fl_rp_n => fl_rp_n,
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fl_sts => fl_sts,
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fl_sts => fl_sts,
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usb_rd_n => usb_rd_n,
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usb_rd_n => usb_rd_n,
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usb_wr => usb_wr,
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usb_wr => usb_wr,
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usb_txe_n => usb_txe_n,
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usb_txe_n => usb_txe_n,
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usb_rxf_n => usb_rxf_n,
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usb_rxf_n => usb_rxf_n,
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usb_bd => usb_bd
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usb_bd => usb_bd
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);
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);
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clocker : process is
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clocker : process is
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begin
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begin
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wait for 17 ns;
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wait for 17 ns;
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lclk <=not (lclk);
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lclk <=not (lclk);
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end process clocker;
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end process clocker;
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clocker2 : process is
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clocker2 : process is
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begin
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begin
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wait for 20 ns;
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wait for 20 ns;
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sys_clk <=not (sys_clk);
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sys_clk <=not (sys_clk);
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end process clocker2;
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end process clocker2;
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tb : PROCESS
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tb : PROCESS
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BEGIN
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BEGIN
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-- Wait 100 ns for global reset to finish
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-- Wait 100 ns for global reset to finish
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wait for 100 ns;
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wait for 100 ns;
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resetn <='1';
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resetn <='1';
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lreset_n <='1';
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lreset_n <='1';
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-- Status check COMMAND
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-- Status check COMMAND
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usb_rxf_n <='0';
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usb_rxf_n <='0';
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usb_bd <=x"00";
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usb_bd <=x"00";
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wait until usb_rd_n='0'; --wait to go low --first read
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wait until usb_rd_n='0'; --wait to go low --first read
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wait until usb_rd_n='1'; --wait to go low
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wait until usb_rd_n='1'; --wait to go low
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wait for 20 ns;
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wait for 20 ns;
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usb_bd <=x"C5";
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usb_bd <=x"C5";
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wait until usb_rd_n='0'; --wait to go low --second read
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wait until usb_rd_n='0'; --wait to go low --second read
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wait until usb_rd_n='1'; --wait to go low
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wait until usb_rd_n='1'; --wait to go low
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usb_bd <=(others=>'Z');
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usb_bd <=(others=>'Z');
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usb_rxf_n <='1';
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usb_rxf_n <='1';
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-- END A1 COMMAND
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-- END A1 COMMAND
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wait for 800 ns;
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wait for 800 ns;
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-- A0 COMMAND
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-- A0 COMMAND
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usb_rxf_n <='0';
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usb_rxf_n <='0';
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usb_bd <=x"02";
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usb_bd <=x"02";
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wait until usb_rd_n='0'; --wait to go low --first read
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wait until usb_rd_n='0'; --wait to go low --first read
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wait until usb_rd_n='1'; --wait to go low
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wait until usb_rd_n='1'; --wait to go low
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wait for 20 ns;
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wait for 20 ns;
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usb_bd <=x"A0";
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usb_bd <=x"A0";
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wait until usb_rd_n='0'; --wait to go low --second read
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wait until usb_rd_n='0'; --wait to go low --second read
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wait until usb_rd_n='1'; --wait to go low
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wait until usb_rd_n='1'; --wait to go low
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usb_bd <=(others=>'Z');
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usb_bd <=(others=>'Z');
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usb_rxf_n <='1';
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usb_rxf_n <='1';
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-- END A0 COMMAND
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-- END A0 COMMAND
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wait for 800 ns;
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wait for 800 ns;
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-- A1 COMMAND
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-- A1 COMMAND
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usb_rxf_n <='0';
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usb_rxf_n <='0';
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usb_bd <=x"00";
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usb_bd <=x"00";
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wait until usb_rd_n='0'; --wait to go low --first read
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wait until usb_rd_n='0'; --wait to go low --first read
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wait until usb_rd_n='1'; --wait to go low
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wait until usb_rd_n='1'; --wait to go low
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wait for 20 ns;
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wait for 20 ns;
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usb_bd <=x"A1";
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usb_bd <=x"A1";
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wait until usb_rd_n='0'; --wait to go low --second read
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wait until usb_rd_n='0'; --wait to go low --second read
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wait until usb_rd_n='1'; --wait to go low
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wait until usb_rd_n='1'; --wait to go low
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usb_bd <=(others=>'Z');
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usb_bd <=(others=>'Z');
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usb_rxf_n <='1';
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usb_rxf_n <='1';
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-- END A1 COMMAND
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-- END A1 COMMAND
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wait for 800 ns;
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wait for 800 ns;
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-- A2 COMMAND
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-- A2 COMMAND
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usb_rxf_n <='0';
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usb_rxf_n <='0';
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usb_bd <=x"00";
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usb_bd <=x"00";
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wait until usb_rd_n='0'; --wait to go low --first read
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wait until usb_rd_n='0'; --wait to go low --first read
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wait until usb_rd_n='1'; --wait to go low
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wait until usb_rd_n='1'; --wait to go low
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wait for 20 ns;
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wait for 20 ns;
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usb_bd <=x"A2";
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usb_bd <=x"A2";
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wait until usb_rd_n='0'; --wait to go low --second read
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wait until usb_rd_n='0'; --wait to go low --second read
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wait until usb_rd_n='1'; --wait to go low
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wait until usb_rd_n='1'; --wait to go low
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usb_bd <=(others=>'Z');
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usb_bd <=(others=>'Z');
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usb_rxf_n <='1';
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usb_rxf_n <='1';
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-- END A2 COMMAND
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-- END A2 COMMAND
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wait for 800 ns;
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wait for 800 ns;
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-- 98 COMMAND
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-- 98 COMMAND
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usb_rxf_n <='0';
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usb_rxf_n <='0';
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usb_bd <=x"00";
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usb_bd <=x"00";
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wait until usb_rd_n='0'; --wait to go low --first read
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wait until usb_rd_n='0'; --wait to go low --first read
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wait until usb_rd_n='1'; --wait to go low
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wait until usb_rd_n='1'; --wait to go low
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wait for 20 ns;
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wait for 20 ns;
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usb_bd <=x"98";
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usb_bd <=x"98";
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wait until usb_rd_n='0'; --wait to go low --second read
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wait until usb_rd_n='0'; --wait to go low --second read
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wait until usb_rd_n='1'; --wait to go low
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wait until usb_rd_n='1'; --wait to go low
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usb_bd <=(others=>'Z');
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usb_bd <=(others=>'Z');
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usb_rxf_n <='1';
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usb_rxf_n <='1';
|
-- END A2 COMMAND
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-- END A2 COMMAND
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wait for 800 ns;
|
wait for 800 ns;
|
|
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-- CD COMMAND
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-- CD COMMAND
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usb_rxf_n <='0';
|
usb_rxf_n <='0';
|
usb_bd <=x"01";
|
usb_bd <=x"01";
|
wait until usb_rd_n='0'; --wait to go low --first read
|
wait until usb_rd_n='0'; --wait to go low --first read
|
wait until usb_rd_n='1'; --wait to go low
|
wait until usb_rd_n='1'; --wait to go low
|
wait for 20 ns;
|
wait for 20 ns;
|
usb_bd <=x"CD";
|
usb_bd <=x"CD";
|
wait until usb_rd_n='0'; --wait to go low --second read
|
wait until usb_rd_n='0'; --wait to go low --second read
|
wait until usb_rd_n='1'; --wait to go low
|
wait until usb_rd_n='1'; --wait to go low
|
usb_bd <=(others=>'Z');
|
usb_bd <=(others=>'Z');
|
usb_rxf_n <='1';
|
usb_rxf_n <='1';
|
-- END CD COMMAND
|
-- END CD COMMAND
|
wait for 800 ns;
|
wait for 800 ns;
|
|
|
-- E8 COMMAND
|
-- E8 COMMAND
|
usb_rxf_n <='0';
|
usb_rxf_n <='0';
|
usb_bd <=x"01"; --this should mean 2 word to write
|
usb_bd <=x"01"; --this should mean 2 word to write
|
wait until usb_rd_n='0'; --wait to go low --first read
|
wait until usb_rd_n='0'; --wait to go low --first read
|
wait until usb_rd_n='1'; --wait to go low
|
wait until usb_rd_n='1'; --wait to go low
|
wait for 20 ns;
|
wait for 20 ns;
|
usb_bd <=x"E8";
|
usb_bd <=x"E8";
|
wait until usb_rd_n='0'; --wait to go low --second read
|
wait until usb_rd_n='0'; --wait to go low --second read
|
wait until usb_rd_n='1'; --wait to go low
|
wait until usb_rd_n='1'; --wait to go low
|
usb_bd <=(others=>'Z');
|
usb_bd <=(others=>'Z');
|
usb_rxf_n <='1';
|
usb_rxf_n <='1';
|
-- END E8 COMMAND
|
-- END E8 COMMAND
|
wait for 2000 ns;
|
wait for 2000 ns;
|
|
|
-- SEND Data count to flash COMMAND
|
-- SEND Data count to flash COMMAND
|
usb_rxf_n <='0';
|
usb_rxf_n <='0';
|
usb_bd <=x"01"; --this should mean 2 word to write
|
usb_bd <=x"01"; --this should mean 2 word to write
|
wait until usb_rd_n='0'; --wait to go low --first read
|
wait until usb_rd_n='0'; --wait to go low --first read
|
wait until usb_rd_n='1'; --wait to go low
|
wait until usb_rd_n='1'; --wait to go low
|
wait for 20 ns;
|
wait for 20 ns;
|
usb_bd <=x"00"; --count 00 means 1 word
|
usb_bd <=x"00"; --count 00 means 1 word
|
wait until usb_rd_n='0'; --wait to go low --second read
|
wait until usb_rd_n='0'; --wait to go low --second read
|
wait until usb_rd_n='1'; --wait to go low
|
wait until usb_rd_n='1'; --wait to go low
|
usb_bd <=(others=>'Z');
|
usb_bd <=(others=>'Z');
|
usb_rxf_n <='1';
|
usb_rxf_n <='1';
|
-- END COMMAND
|
-- END COMMAND
|
wait for 800 ns;
|
wait for 800 ns;
|
|
|
-- SEND raw Data
|
-- SEND raw Data
|
usb_rxf_n <='0';
|
usb_rxf_n <='0';
|
usb_bd <=x"CA"; --this should mean 1 word to write
|
usb_bd <=x"CA"; --this should mean 1 word to write
|
wait until usb_rd_n='0'; --wait to go low --first read
|
wait until usb_rd_n='0'; --wait to go low --first read
|
wait until usb_rd_n='1'; --wait to go low
|
wait until usb_rd_n='1'; --wait to go low
|
wait for 20 ns;
|
wait for 20 ns;
|
usb_bd <=x"FE"; --count 00 means 1 word
|
usb_bd <=x"FE"; --count 00 means 1 word
|
wait until usb_rd_n='0'; --wait to go low --second read
|
wait until usb_rd_n='0'; --wait to go low --second read
|
wait until usb_rd_n='1'; --wait to go low
|
wait until usb_rd_n='1'; --wait to go low
|
usb_bd <=(others=>'Z');
|
usb_bd <=(others=>'Z');
|
usb_rxf_n <='1';
|
usb_rxf_n <='1';
|
-- END send data
|
-- END send data
|
wait for 800 ns;
|
wait for 800 ns;
|
|
|
-- SEND raw Data
|
-- SEND raw Data
|
usb_rxf_n <='0';
|
usb_rxf_n <='0';
|
usb_bd <=x"BE"; --this should mean 1 word to write
|
usb_bd <=x"BE"; --this should mean 1 word to write
|
wait until usb_rd_n='0'; --wait to go low --first read
|
wait until usb_rd_n='0'; --wait to go low --first read
|
wait until usb_rd_n='1'; --wait to go low
|
wait until usb_rd_n='1'; --wait to go low
|
wait for 20 ns;
|
wait for 20 ns;
|
usb_bd <=x"CD"; --count 00 means 1 word
|
usb_bd <=x"CD"; --count 00 means 1 word
|
wait until usb_rd_n='0'; --wait to go low --second read
|
wait until usb_rd_n='0'; --wait to go low --second read
|
wait until usb_rd_n='1'; --wait to go low
|
wait until usb_rd_n='1'; --wait to go low
|
usb_bd <=(others=>'Z');
|
usb_bd <=(others=>'Z');
|
usb_rxf_n <='1';
|
usb_rxf_n <='1';
|
-- END send data
|
-- END send data
|
wait for 800 ns;
|
wait for 800 ns;
|
|
|
wait; -- will wait forever
|
wait; -- will wait forever
|
END PROCESS;
|
END PROCESS;
|
|
|
END;
|
END;
|
|
|
