------------------------------------------------------------------
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------------------------------------------------------------------
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-- Universal dongle board source code
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-- Universal dongle board source code
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--
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--
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-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>
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-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>
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--
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--
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-- This source code is free hardware; you can redistribute it and/or
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-- This source code is free hardware; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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-- version 2.1 of the License, or (at your option) any later version.
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--
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--
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-- This source code is distributed in the hope that it will be useful,
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-- This source code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Lesser General Public License for more details.
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-- Lesser General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU Lesser General Public
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-- You should have received a copy of the GNU Lesser General Public
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-- License along with this library; if not, write to the Free Software
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-- License along with this library; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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--
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--
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-- The complete text of the GNU Lesser General Public License can be found in
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-- The complete text of the GNU Lesser General Public License can be found in
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-- the file 'lesser.txt'.
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-- the file 'lesser.txt'.
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-- Coding for seg_out(7:0)
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-- Coding for seg_out(7:0)
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--
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--
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-- bit 0,A
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-- bit 0,A
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-- ----------
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-- ----------
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-- | |
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-- | |
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-- | |
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-- | |
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-- 5,F| | 1,B
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-- 5,F| | 1,B
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-- | 6,G |
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-- | 6,G |
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-- ----------
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-- ----------
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-- | |
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-- | |
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-- | |
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-- | |
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-- 4,E| | 2,C
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-- 4,E| | 2,C
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-- | 3,D |
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-- | 3,D |
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-- ----------
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-- ----------
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-- # 7,H
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-- # 7,H
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-- Revision history
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-- Revision history
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--
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--
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-- Version 1.01
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-- Version 1.01
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-- 15 oct 2006 version code 86 01 jyrit
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-- 15 oct 2006 version code 86 01 jyrit
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-- Added IO write to address 0x0088 with commands F1 and F4 to
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-- Added IO write to address 0x0088 with commands F1 and F4 to
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-- enable switching dongle to 4Meg mode for external reads
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-- enable switching dongle to 4Meg mode for external reads
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-- Changed USB interface to address all 4 Meg on any mode jumper configuration
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-- Changed USB interface to address all 4 Meg on any mode jumper configuration
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--
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--
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-- Version 1.02
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-- Version 1.02
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-- 04 dec 2006 version code 86 02 jyrit
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-- 04 dec 2006 version code 86 02 jyrit
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-- Added listen only mode for mode pin configuration "00" to enable post code
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-- Added listen only mode for mode pin configuration "00" to enable post code
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-- spy mode (does not respond to external reads).
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-- spy mode (does not respond to external reads).
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_arith.all;
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entity design_top is
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entity design_top is
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port (
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port (
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--system signals
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--system signals
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sys_clk : in std_logic; --25 MHz clk
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sys_clk : in std_logic; --25 MHz clk
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resetn : in std_logic;
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resetn : in std_logic;
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hdr : out std_logic_vector(10 downto 0);
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hdr : out std_logic_vector(10 downto 0);
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--alt_clk : out std_logic; --alternative clock from extention header
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--alt_clk : out std_logic; --alternative clock from extention header
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mode : in std_logic_vector(1 downto 0); --sel upper addr bits
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mode : in std_logic_vector(1 downto 0); --sel upper addr bits
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--lpc slave interf
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--lpc slave interf
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lad : inout std_logic_vector(3 downto 0);
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lad : inout std_logic_vector(3 downto 0);
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lframe_n : in std_logic;
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lframe_n : in std_logic;
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lreset_n : in std_logic;
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lreset_n : in std_logic;
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lclk : in std_logic;
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lclk : in std_logic;
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--led system
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--led system
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seg_out : out std_logic_vector(7 downto 0);
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seg_out : out std_logic_vector(7 downto 0);
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scn_seg : out std_logic_vector(3 downto 0);
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scn_seg : out std_logic_vector(3 downto 0);
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led_green : out std_logic;
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led_green : out std_logic;
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led_red : out std_logic;
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led_red : out std_logic;
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--flash interface
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--flash interface
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fl_addr : out std_logic_vector(23 downto 0);
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fl_addr : out std_logic_vector(23 downto 0);
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fl_ce_n : out std_logic; --chip select
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fl_ce_n : out std_logic; --chip select
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fl_oe_n : out std_logic; --output enable for flash
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fl_oe_n : out std_logic; --output enable for flash
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fl_we_n : out std_logic; --write enable
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fl_we_n : out std_logic; --write enable
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fl_data : inout std_logic_vector(15 downto 0);
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fl_data : inout std_logic_vector(15 downto 0);
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fl_rp_n : out std_logic; --reset signal
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fl_rp_n : out std_logic; --reset signal
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fl_sts : in std_logic; --status signal
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fl_sts : in std_logic; --status signal
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--USB parallel interface
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--USB parallel interface
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usb_rd_n : inout std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
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usb_rd_n : inout std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
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usb_wr : inout std_logic; -- write performed on edge \ of signal
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usb_wr : inout std_logic; -- write performed on edge \ of signal
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usb_txe_n : in std_logic; -- transmit enable (redy for new data if low)
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usb_txe_n : in std_logic; -- transmit enable (redy for new data if low)
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usb_rxf_n : in std_logic; -- rx fifo has data if low
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usb_rxf_n : in std_logic; -- rx fifo has data if low
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usb_bd : inout std_logic_vector(7 downto 0) --bus data
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usb_bd : inout std_logic_vector(7 downto 0) --bus data
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);
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);
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end design_top;
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end design_top;
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architecture rtl of design_top is
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architecture rtl of design_top is
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component led_sys --toplevel for led system
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component led_sys --toplevel for led system
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generic(
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generic(
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msn_hib : std_logic_vector(7 downto 0); --Most signif. of hi byte
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msn_hib : std_logic_vector(7 downto 0); --Most signif. of hi byte
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lsn_hib : std_logic_vector(7 downto 0); --Least signif. of hi byte
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lsn_hib : std_logic_vector(7 downto 0); --Least signif. of hi byte
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msn_lob : std_logic_vector(7 downto 0); --Most signif. of hi byte
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msn_lob : std_logic_vector(7 downto 0); --Most signif. of hi byte
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lsn_lob : std_logic_vector(7 downto 0) --Least signif. of hi byte
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lsn_lob : std_logic_vector(7 downto 0) --Least signif. of hi byte
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);
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);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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reset_n : in std_logic;
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reset_n : in std_logic;
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led_data_i : in std_logic_vector(15 downto 0); --binary data in
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led_data_i : in std_logic_vector(15 downto 0); --binary data in
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seg_out : out std_logic_vector(7 downto 0); --one segment out
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seg_out : out std_logic_vector(7 downto 0); --one segment out
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sel_out : out std_logic_vector(3 downto 0) --segment scanner with one bit low
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sel_out : out std_logic_vector(3 downto 0) --segment scanner with one bit low
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);
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);
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end component;
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end component;
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component lpc_iow
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component lpc_iow
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port (
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port (
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--system signals
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--system signals
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lreset_n : in std_logic;
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lreset_n : in std_logic;
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lclk : in std_logic;
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lclk : in std_logic;
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--LPC bus from host
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--LPC bus from host
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lad_i : in std_logic_vector(3 downto 0);
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lad_i : in std_logic_vector(3 downto 0);
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lad_o : out std_logic_vector(3 downto 0);
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lad_o : out std_logic_vector(3 downto 0);
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lad_oe : out std_logic;
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lad_oe : out std_logic;
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lframe_n : in std_logic;
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lframe_n : in std_logic;
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--memory interface
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--memory interface
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lpc_addr : out std_logic_vector(23 downto 0); --shared address
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lpc_addr : out std_logic_vector(23 downto 0); --shared address
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lpc_wr : out std_logic; --shared write not read
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lpc_wr : out std_logic; --shared write not read
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lpc_data_i : in std_logic_vector(7 downto 0);
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lpc_data_i : in std_logic_vector(7 downto 0);
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lpc_data_o : out std_logic_vector(7 downto 0);
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lpc_data_o : out std_logic_vector(7 downto 0);
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lpc_val : out std_logic;
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lpc_val : out std_logic;
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lpc_ack : in std_logic
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lpc_ack : in std_logic
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);
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);
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end component;
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end component;
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component flash_if
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component flash_if
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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reset_n : in std_logic;
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reset_n : in std_logic;
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--flash Bus
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--flash Bus
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fl_addr : out std_logic_vector(23 downto 0);
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fl_addr : out std_logic_vector(23 downto 0);
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fl_ce_n : out std_logic; --chip select
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fl_ce_n : out std_logic; --chip select
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fl_oe_n : out std_logic; --output enable for flash
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fl_oe_n : out std_logic; --output enable for flash
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fl_we_n : out std_logic; --write enable
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fl_we_n : out std_logic; --write enable
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fl_data : inout std_logic_vector(15 downto 0);
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fl_data : inout std_logic_vector(15 downto 0);
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fl_rp_n : out std_logic; --reset signal
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fl_rp_n : out std_logic; --reset signal
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fl_byte_n : out std_logic; --hold in byte mode
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fl_byte_n : out std_logic; --hold in byte mode
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fl_sts : in std_logic; --status signal
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fl_sts : in std_logic; --status signal
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-- mem Bus
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-- mem Bus
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mem_addr : in std_logic_vector(23 downto 0);
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mem_addr : in std_logic_vector(23 downto 0);
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mem_do : out std_logic_vector(15 downto 0);
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mem_do : out std_logic_vector(15 downto 0);
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mem_di : in std_logic_vector(15 downto 0);
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mem_di : in std_logic_vector(15 downto 0);
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mem_wr : in std_logic; --write not read signal
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mem_wr : in std_logic; --write not read signal
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mem_val : in std_logic;
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mem_val : in std_logic;
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mem_ack : out std_logic
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mem_ack : out std_logic
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);
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);
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end component;
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end component;
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component usb2mem
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component usb2mem
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port (
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port (
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clk25 : in std_logic;
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clk25 : in std_logic;
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reset_n : in std_logic;
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reset_n : in std_logic;
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-- mem Bus
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-- mem Bus
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mem_addr : out std_logic_vector(23 downto 0);
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mem_addr : out std_logic_vector(23 downto 0);
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mem_do : out std_logic_vector(15 downto 0);
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mem_do : out std_logic_vector(15 downto 0);
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mem_di : in std_logic_vector(15 downto 0);
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mem_di : in std_logic_vector(15 downto 0);
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mem_wr : out std_logic;
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mem_wr : out std_logic;
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mem_val : out std_logic;
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mem_val : out std_logic;
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mem_ack : in std_logic;
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mem_ack : in std_logic;
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mem_cmd : out std_logic;
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mem_cmd : out std_logic;
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-- USB port
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-- USB port
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usb_rd_n : out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
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usb_rd_n : out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
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usb_wr : out std_logic; -- write performed on edge \ of signal
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usb_wr : out std_logic; -- write performed on edge \ of signal
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usb_txe_n : in std_logic; -- tx fifo empty (redy for new data if low)
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usb_txe_n : in std_logic; -- tx fifo empty (redy for new data if low)
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usb_rxf_n : in std_logic; -- rx fifo empty (data redy if low)
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usb_rxf_n : in std_logic; -- rx fifo empty (data redy if low)
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usb_bd : inout std_logic_vector(7 downto 0) --bus data
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usb_bd : inout std_logic_vector(7 downto 0) --bus data
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);
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);
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end component;
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end component;
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--LED signals
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--LED signals
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signal data_to_disp : std_logic_vector(15 downto 0);
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signal data_to_disp : std_logic_vector(15 downto 0);
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--END LED SIGNALS
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--END LED SIGNALS
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--lpc signals
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--lpc signals
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signal lad_i : std_logic_vector(3 downto 0);
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signal lad_i : std_logic_vector(3 downto 0);
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signal lad_o : std_logic_vector(3 downto 0);
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signal lad_o : std_logic_vector(3 downto 0);
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signal lad_oe : std_logic;
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signal lad_oe : std_logic;
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signal lpc_debug : std_logic_vector(31 downto 0);
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signal lpc_debug : std_logic_vector(31 downto 0);
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signal lpc_addr : std_logic_vector(23 downto 0); --shared address
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signal lpc_addr : std_logic_vector(23 downto 0); --shared address
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signal lpc_data_o : std_logic_vector(7 downto 0);
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signal lpc_data_o : std_logic_vector(7 downto 0);
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signal lpc_data_i : std_logic_vector(7 downto 0);
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signal lpc_data_i : std_logic_vector(7 downto 0);
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signal lpc_wr : std_logic; --shared write not read
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signal lpc_wr : std_logic; --shared write not read
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signal lpc_ack : std_logic;
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signal lpc_ack : std_logic;
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signal lpc_val : std_logic;
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signal lpc_val : std_logic;
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signal c25_lpc_val : std_logic;
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signal c25_lpc_val : std_logic;
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signal c25_lpc_wr : std_logic; --shared write not read
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signal c25_lpc_wr : std_logic; --shared write not read
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signal c33_lpc_wr : std_logic; --for led debug data latching
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signal c33_lpc_wr : std_logic; --for led debug data latching
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--End lpc signals
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--End lpc signals
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--Flash signals
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--Flash signals
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signal mem_addr : std_logic_vector(23 downto 0);
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signal mem_addr : std_logic_vector(23 downto 0);
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signal mem_do : std_logic_vector(15 downto 0);
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signal mem_do : std_logic_vector(15 downto 0);
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signal mem_di : std_logic_vector(15 downto 0);
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signal mem_di : std_logic_vector(15 downto 0);
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signal mem_wr : std_logic; --write not read signal
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signal mem_wr : std_logic; --write not read signal
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signal mem_val : std_logic;
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signal mem_val : std_logic;
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signal mem_ack : std_logic;
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signal mem_ack : std_logic;
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signal c33_mem_ack : std_logic; --sync signal
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signal c33_mem_ack : std_logic; --sync signal
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signal fl_ce_n_w : std_logic; --chip select
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signal fl_ce_n_w : std_logic; --chip select
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signal fl_oe_n_w : std_logic; --output enable for flash
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signal fl_oe_n_w : std_logic; --output enable for flash
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--END flash signals
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--END flash signals
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--USB signals
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--USB signals
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signal umem_addr : std_logic_vector(23 downto 0);
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signal umem_addr : std_logic_vector(23 downto 0);
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signal umem_do : std_logic_vector(15 downto 0);
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signal umem_do : std_logic_vector(15 downto 0);
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signal umem_wr : std_logic;
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signal umem_wr : std_logic;
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signal umem_val : std_logic;
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signal umem_val : std_logic;
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signal umem_ack : std_logic;
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signal umem_ack : std_logic;
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signal umem_cmd : std_logic;
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signal umem_cmd : std_logic;
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signal enable_4meg: std_logic;
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signal enable_4meg: std_logic;
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--END USB signals
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--END USB signals
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begin
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begin
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--LED SUBSYSTEM START
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--LED SUBSYSTEM START
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data_to_disp <= x"86"&lpc_debug(7 downto 0); --x"C0DE"; -- ASSIGN data to be displayed (should be regitered)
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data_to_disp <= x"86"&lpc_debug(7 downto 0); --x"C0DE"; -- ASSIGN data to be displayed (should be regitered)
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--########################################--
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--########################################--
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--VERSION CONSTATNS
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--VERSION CONSTATNS
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--########################################--
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--########################################--
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led_red <= enable_4meg;
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led_red <= enable_4meg;
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LEDS: led_sys --toplevel for led system
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LEDS: led_sys --toplevel for led system
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generic map(
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generic map(
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msn_hib => "01111111",--8 --Most signif. of hi byte
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msn_hib => "01111111",--8 --Most signif. of hi byte
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lsn_hib => "01111101",--6 --Least signif. of hi byte
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lsn_hib => "01111101",--6 --Least signif. of hi byte
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msn_lob => "10111111",--0 --Most signif. of hi byte This is version code
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msn_lob => "10111111",--0 --Most signif. of hi byte This is version code
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lsn_lob => "01011011" --2 --Least signif. of hi byte This is version code
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lsn_lob => "01001111" --3 --Least signif. of hi byte This is version code
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)
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)
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port map(
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port map(
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clk => sys_clk , -- in std_logic;
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clk => sys_clk , -- in std_logic;
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reset_n => resetn, -- in std_logic;
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reset_n => resetn, -- in std_logic;
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led_data_i => data_to_disp, -- in std_logic_vector(15 downto 0); --binary data in
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led_data_i => data_to_disp, -- in std_logic_vector(15 downto 0); --binary data in
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seg_out => seg_out, -- out std_logic_vector(7 downto 0); --one segment out
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seg_out => seg_out, -- out std_logic_vector(7 downto 0); --one segment out
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sel_out => scn_seg -- out std_logic_vector(3 downto 0) --segment scanner with one bit low
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sel_out => scn_seg -- out std_logic_vector(3 downto 0) --segment scanner with one bit low
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);
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);
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--LED SUBSYSTEM END
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--LED SUBSYSTEM END
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--MAIN DATAPATH CONNECTIONS
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--MAIN DATAPATH CONNECTIONS
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--LPC bus logic
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--LPC bus logic
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lad_i <= lad;
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lad_i <= lad;
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lad <= lad_o when lad_oe='1' and mode/="00" else --mode "00" is post code spy mode
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lad <= lad_o when lad_oe='1' else
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(others=>'Z');
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(others=>'Z');
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--END LPC bus logic
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--END LPC bus logic
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LPCBUS : lpc_iow
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LPCBUS : lpc_iow
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port map(
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port map(
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--system signals
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--system signals
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lreset_n => lreset_n, -- in std_logic;
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lreset_n => lreset_n, -- in std_logic;
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lclk => lclk, -- in std_logic;
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lclk => lclk, -- in std_logic;
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--LPC bus from host
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--LPC bus from host
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lad_i => lad_i, -- in std_logic_vector(3 downto 0);
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lad_i => lad_i, -- in std_logic_vector(3 downto 0);
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lad_o => lad_o, -- out std_logic_vector(3 downto 0);
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lad_o => lad_o, -- out std_logic_vector(3 downto 0);
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lad_oe => lad_oe, -- out std_logic;
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lad_oe => lad_oe, -- out std_logic;
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lframe_n => lframe_n, -- in std_logic;
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lframe_n => lframe_n, -- in std_logic;
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--memory interface
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--memory interface
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lpc_addr => lpc_addr, -- out std_logic_vector(23 downto 0); --shared address
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lpc_addr => lpc_addr, -- out std_logic_vector(23 downto 0); --shared address
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lpc_wr => lpc_wr, -- out std_logic; --shared write not read
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lpc_wr => lpc_wr, -- out std_logic; --shared write not read
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lpc_data_i => lpc_data_i, -- in std_logic_vector(7 downto 0);
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lpc_data_i => lpc_data_i, -- in std_logic_vector(7 downto 0);
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lpc_data_o => lpc_data_o, -- out std_logic_vector(7 downto 0);
|
lpc_data_o => lpc_data_o, -- out std_logic_vector(7 downto 0);
|
lpc_val => lpc_val, -- out std_logic;
|
lpc_val => lpc_val, -- out std_logic;
|
lpc_ack => lpc_ack -- in std_logic
|
lpc_ack => lpc_ack -- in std_logic
|
);
|
);
|
|
|
|
|
--memory data bus logic
|
--memory data bus logic
|
mem_addr <= mode&"11"&lpc_addr(19 downto 0) when c25_lpc_val='1' and enable_4meg='0' else --use mode bist
|
mem_addr <= mode&"11"&lpc_addr(19 downto 0) when c25_lpc_val='1' and enable_4meg='0' else --use mode bist
|
mode&lpc_addr(21 downto 0) when c25_lpc_val='1' and enable_4meg='1' else --use mode bist
|
mode&lpc_addr(21 downto 0) when c25_lpc_val='1' and enable_4meg='1' else --use mode bist
|
mode&umem_addr(21 downto 0) when umem_val='1' else --use mode bist
|
mode&umem_addr(21 downto 0) when umem_val='1' else --use mode bist
|
(others=>'Z');
|
(others=>'Z');
|
|
|
mem_di <= (others=>'Z') when c25_lpc_val='1' else
|
mem_di <= (others=>'Z') when c25_lpc_val='1' else
|
umem_do when umem_val='1' else
|
umem_do when umem_val='1' else
|
(others=>'Z');
|
(others=>'Z');
|
|
|
|
|
mem_wr <= c25_lpc_wr when c25_lpc_val='1' and c25_lpc_wr='0' else --pass read olny
|
mem_wr <= c25_lpc_wr when c25_lpc_val='1' and c25_lpc_wr='0' else --pass read olny
|
umem_wr when umem_val='1' else
|
umem_wr when umem_val='1' else
|
'0';
|
'0';
|
|
|
mem_val <= c25_lpc_val or umem_val;
|
mem_val <= c25_lpc_val or umem_val;
|
|
|
|
|
|
|
umem_ack <= mem_ack when umem_val='1' else
|
umem_ack <= mem_ack when umem_val='1' else
|
'0';
|
'0';
|
|
|
|
|
lpc_data_i <= mem_do(7 downto 0) when lpc_addr(0)='0' else
|
lpc_data_i <= mem_do(7 downto 0) when lpc_addr(0)='0' else
|
mem_do(15 downto 8);
|
mem_do(15 downto 8);
|
|
|
lpc_ack <= c33_mem_ack when lpc_val='1' and lpc_wr='0' else
|
lpc_ack <= c33_mem_ack when lpc_val='1' and lpc_wr='0' else
|
'1' when lpc_val='1' and lpc_wr='1' else
|
'1' when lpc_val='1' and lpc_wr='1' else
|
'0';
|
'0';
|
|
|
|
|
|
|
SYNC1: process (lclk, lreset_n) --c33
|
SYNC1: process (lclk, lreset_n) --c33
|
begin
|
begin
|
if lclk'event and lclk = '1' then -- rising clock edge
|
if lclk'event and lclk = '1' then -- rising clock edge
|
c33_mem_ack <= mem_ack;
|
c33_mem_ack <= mem_ack;
|
|
|
end if;
|
end if;
|
end process SYNC1;
|
end process SYNC1;
|
|
|
|
|
SYNC2: process (sys_clk, resetn) --c25
|
SYNC2: process (sys_clk, resetn) --c25
|
begin
|
begin
|
if sys_clk'event and sys_clk = '1' then -- rising clock edge
|
if sys_clk'event and sys_clk = '1' then -- rising clock edge
|
c25_lpc_val <= lpc_val;
|
c25_lpc_val <= lpc_val;
|
c25_lpc_wr <= lpc_wr;
|
c25_lpc_wr <= lpc_wr;
|
end if;
|
end if;
|
end process SYNC2;
|
end process SYNC2;
|
|
|
|
|
|
|
LATCHled: process (lclk,lreset_n) --c33
|
LATCHled: process (lclk,lreset_n) --c33
|
begin
|
begin
|
if lreset_n='0' then
|
if lreset_n='0' then
|
lpc_debug(7 downto 0)<=(others=>'0');
|
lpc_debug(7 downto 0)<=(others=>'0');
|
enable_4meg <='0';
|
enable_4meg <='0';
|
c33_lpc_wr <='0';
|
c33_lpc_wr <='0';
|
elsif lclk'event and lclk = '1' then -- rising clock edge
|
elsif lclk'event and lclk = '1' then -- rising clock edge
|
c33_lpc_wr <= lpc_wr; --just for debug delay
|
c33_lpc_wr <= lpc_wr; --just for debug delay
|
if c33_lpc_wr='0' and lpc_wr='1' then
|
if c33_lpc_wr='0' and lpc_wr='1' then
|
lpc_debug(7 downto 0)<= lpc_data_o;
|
lpc_debug(7 downto 0)<= lpc_data_o;
|
if lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"4F" then --Flash 4 Mega enable (LSN is first MSN is second)
|
if lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"4F" then --Flash 4 Mega enable (LSN is first MSN is second)
|
enable_4meg <='1';
|
enable_4meg <='1';
|
elsif lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"1F" then --Flash 1 Mega enalbe
|
elsif lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"1F" then --Flash 1 Mega enalbe
|
enable_4meg <='0';
|
enable_4meg <='0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process LATCHled;
|
end process LATCHled;
|
|
|
|
|
|
|
|
|
|
|
|
|
--END memory data bus logic
|
--END memory data bus logic
|
fl_ce_n<= fl_ce_n_w;
|
fl_ce_n<= fl_ce_n_w;
|
fl_oe_n<= fl_oe_n_w;
|
fl_oe_n<= fl_oe_n_w;
|
|
|
FLASH : flash_if
|
FLASH : flash_if
|
port map(
|
port map(
|
clk => sys_clk, -- in std_logic;
|
clk => sys_clk, -- in std_logic;
|
reset_n => resetn, -- in std_logic;
|
reset_n => resetn, -- in std_logic;
|
--flash Bus
|
--flash Bus
|
fl_addr => fl_addr, -- out std_logic_vector(23 downto 0);
|
fl_addr => fl_addr, -- out std_logic_vector(23 downto 0);
|
fl_ce_n => fl_ce_n_w, -- out std_logic; --chip select
|
fl_ce_n => fl_ce_n_w, -- out std_logic; --chip select
|
fl_oe_n => fl_oe_n_w, -- buffer std_logic; --output enable for flash
|
fl_oe_n => fl_oe_n_w, -- buffer std_logic; --output enable for flash
|
fl_we_n => fl_we_n, -- out std_logic; --write enable
|
fl_we_n => fl_we_n, -- out std_logic; --write enable
|
fl_data => fl_data, -- inout std_logic_vector(15 downto 0);
|
fl_data => fl_data, -- inout std_logic_vector(15 downto 0);
|
fl_rp_n => fl_rp_n, -- out std_logic; --reset signal
|
fl_rp_n => fl_rp_n, -- out std_logic; --reset signal
|
--fl_byte_n => fl_byte_n, -- out std_logic; --hold in byte mode
|
--fl_byte_n => fl_byte_n, -- out std_logic; --hold in byte mode
|
fl_sts => fl_sts, -- in std_logic; --status signal
|
fl_sts => fl_sts, -- in std_logic; --status signal
|
-- mem Bus
|
-- mem Bus
|
mem_addr => mem_addr, -- in std_logic_vector(23 downto 0);
|
mem_addr => mem_addr, -- in std_logic_vector(23 downto 0);
|
mem_do => mem_do, -- out std_logic_vector(15 downto 0);
|
mem_do => mem_do, -- out std_logic_vector(15 downto 0);
|
mem_di => mem_di, -- in std_logic_vector(15 downto 0);
|
mem_di => mem_di, -- in std_logic_vector(15 downto 0);
|
|
|
mem_wr => mem_wr, -- in std_logic; --write not read signal
|
mem_wr => mem_wr, -- in std_logic; --write not read signal
|
mem_val => mem_val, -- in std_logic;
|
mem_val => mem_val, -- in std_logic;
|
mem_ack => mem_ack -- out std_logic
|
mem_ack => mem_ack -- out std_logic
|
);
|
);
|
|
|
--hdr(7 downto 0) <= umem_do(7 downto 0) when umem_ack='0' and umem_wr='1' else
|
--hdr(7 downto 0) <= umem_do(7 downto 0) when umem_ack='0' and umem_wr='1' else
|
-- umem_do(15 downto 8) when umem_ack='1' and umem_wr='1' else
|
-- umem_do(15 downto 8) when umem_ack='1' and umem_wr='1' else
|
-- mem_do(7 downto 0) when umem_wr='0' else
|
-- mem_do(7 downto 0) when umem_wr='0' else
|
-- mem_do(15 downto 8);
|
-- mem_do(15 downto 8);
|
--hdr(8)<= umem_wr;
|
--hdr(8)<= umem_wr;
|
--hdr(9)<= umem_val;
|
--hdr(9)<= umem_val;
|
--hdr(10)<= umem_ack;
|
--hdr(10)<= umem_ack;
|
-- usb_rd_n : out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
|
-- usb_rd_n : out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
|
-- usb_wr : out std_logic; -- write performed on edge \ of signal
|
-- usb_wr : out std_logic; -- write performed on edge \ of signal
|
-- usb_txe_n : in std_logic; -- transmit enable (redy for new data if low)
|
-- usb_txe_n : in std_logic; -- transmit enable (redy for new data if low)
|
-- usb_rxf_n : in std_logic; -- rx fifo has data if low
|
-- usb_rxf_n : in std_logic; -- rx fifo has data if low
|
|
|
hdr(3 downto 0) <= lad_o when lad_oe='1' else
|
hdr(3 downto 0) <= lad_o when lad_oe='1' else
|
lad;
|
lad;
|
hdr(4)<= lframe_n;
|
hdr(4)<= lframe_n;
|
hdr(5)<= lreset_n;
|
hdr(5)<= lreset_n;
|
hdr(6)<= lclk;
|
hdr(6)<= lclk;
|
hdr(7)<= lpc_ack;
|
hdr(7)<= lpc_ack;
|
|
|
--hdr(7 downto 0) <= lpc_data_o(7 downto 0);
|
--hdr(7 downto 0) <= lpc_data_o(7 downto 0);
|
|
|
hdr(8)<= lpc_val;
|
hdr(8)<= lpc_val;
|
hdr(9)<= '1' when lpc_wr='1' and lpc_addr(7 downto 0)=x"88" else
|
hdr(9)<= '1' when lpc_wr='1' and lpc_addr(7 downto 0)=x"88" else
|
'0';
|
'0';
|
hdr(10)<= resetn;
|
hdr(10)<= resetn;
|
|
|
|
|
USB: usb2mem
|
USB: usb2mem
|
port map(
|
port map(
|
clk25 => sys_clk, -- in std_logic;
|
clk25 => sys_clk, -- in std_logic;
|
reset_n => resetn, -- in std_logic;
|
reset_n => resetn, -- in std_logic;
|
-- mem Bus
|
-- mem Bus
|
mem_addr => umem_addr, -- out std_logic_vector(23 downto 0);
|
mem_addr => umem_addr, -- out std_logic_vector(23 downto 0);
|
mem_do => umem_do, -- out std_logic_vector(15 downto 0);
|
mem_do => umem_do, -- out std_logic_vector(15 downto 0);
|
mem_di => mem_do, -- in std_logic_vector(15 downto 0); --from flash
|
mem_di => mem_do, -- in std_logic_vector(15 downto 0); --from flash
|
mem_wr => umem_wr, -- out std_logic;
|
mem_wr => umem_wr, -- out std_logic;
|
mem_val => umem_val, -- out std_logic;
|
mem_val => umem_val, -- out std_logic;
|
mem_ack => umem_ack, -- in std_logic; --from flash
|
mem_ack => umem_ack, -- in std_logic; --from flash
|
mem_cmd => umem_cmd, -- out std_logic;
|
mem_cmd => umem_cmd, -- out std_logic;
|
-- USB port
|
-- USB port
|
usb_rd_n => usb_rd_n, -- out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
|
usb_rd_n => usb_rd_n, -- out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
|
usb_wr => usb_wr, -- out std_logic; -- write performed on edge \ of signal
|
usb_wr => usb_wr, -- out std_logic; -- write performed on edge \ of signal
|
usb_txe_n => usb_txe_n, -- in std_logic; -- tx fifo empty (redy for new data if low)
|
usb_txe_n => usb_txe_n, -- in std_logic; -- tx fifo empty (redy for new data if low)
|
usb_rxf_n => usb_rxf_n, -- in std_logic; -- rx fifo empty (data redy if low)
|
usb_rxf_n => usb_rxf_n, -- in std_logic; -- rx fifo empty (data redy if low)
|
usb_bd => usb_bd -- inout std_logic_vector(7 downto 0) --bus data
|
usb_bd => usb_bd -- inout std_logic_vector(7 downto 0) --bus data
|
);
|
);
|
|
|
|
|
--END MAIN DATAPATH CONNECTIONS
|
--END MAIN DATAPATH CONNECTIONS
|
|
|
end rtl;
|
end rtl;
|
|
|
|
|
|
|
|
|
