------------------------------------------------------------------
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------------------------------------------------------------------
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-- Universal dongle board source code
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-- Universal dongle board source code
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--
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--
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-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>
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-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>
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--
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--
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-- This source code is free hardware; you can redistribute it and/or
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-- This source code is free hardware; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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-- version 2.1 of the License, or (at your option) any later version.
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--
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--
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-- This source code is distributed in the hope that it will be useful,
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-- This source code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Lesser General Public License for more details.
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-- Lesser General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU Lesser General Public
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-- You should have received a copy of the GNU Lesser General Public
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-- License along with this library; if not, write to the Free Software
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-- License along with this library; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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--
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--
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-- The complete text of the GNU Lesser General Public License can be found in
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-- The complete text of the GNU Lesser General Public License can be found in
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-- the file 'lesser.txt'.
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-- the file 'lesser.txt'.
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-- Coding for seg_out(7:0)
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-- Coding for seg_out(7:0)
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--
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--
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-- bit 0,A
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-- bit 0,A
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-- ----------
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-- ----------
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-- | |
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-- | |
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-- | |
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-- | |
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-- 5,F| | 1,B
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-- 5,F| | 1,B
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-- | 6,G |
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-- | 6,G |
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-- ----------
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-- ----------
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-- | |
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-- | |
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-- | |
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-- | |
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-- 4,E| | 2,C
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-- 4,E| | 2,C
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-- | 3,D |
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-- | 3,D |
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-- ----------
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-- ----------
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-- # 7,H
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-- # 7,H
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-- Revision history
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-- Revision history
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--
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--
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-- Version 1.01
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-- Version 1.01
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-- 15 oct 2006 version code 86 01 jyrit
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-- 15 oct 2006 version code 86 01 jyrit
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-- Added IO write to address 0x0088 with commands F1 and F4 to
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-- Added IO write to address 0x0088 with commands F1 and F4 to
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-- enable switching dongle to 4Meg mode for external reads
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-- enable switching dongle to 4Meg mode for external reads
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-- Changed USB interface to address all 4 Meg on any mode jumper configuration
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-- Changed USB interface to address all 4 Meg on any mode jumper configuration
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--
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--
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-- Version 1.02
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-- Version 1.02
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-- 04 dec 2006 version code 86 02 jyrit
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-- 04 dec 2006 version code 86 02 jyrit
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-- Added listen only mode for mode pin configuration "00" to enable post code
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-- Added listen only mode for mode pin configuration "00" to enable post code
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-- spy mode (does not respond to external reads).
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-- spy mode (does not respond to external reads).
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_arith.all;
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entity design_top_thincandbg is
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entity design_top_thincandbg is
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port (
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port (
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--system signals
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--system signals
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sys_clk : in std_logic; --25 MHz clk
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sys_clk : in std_logic; --25 MHz clk
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resetn : in std_logic;
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resetn : in std_logic;
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hdr : inout std_logic_vector(9 downto 0);
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hdr : inout std_logic_vector(9 downto 0);
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--alt_clk : out std_logic;
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--alt_clk : out std_logic;
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mode : in std_logic_vector(1 downto 0); --sel upper addr bits
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mode : in std_logic_vector(1 downto 0); --sel upper addr bits
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--lpc slave interf
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--lpc slave interf
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lad : inout std_logic_vector(3 downto 0);
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lad : inout std_logic_vector(3 downto 0);
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lframe_n : in std_logic;
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lframe_n : in std_logic;
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lreset_n : in std_logic;
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lreset_n : in std_logic;
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lclk : in std_logic;
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lclk : in std_logic;
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--led system
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--led system
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seg_out : out std_logic_vector(7 downto 0);
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seg_out : out std_logic_vector(7 downto 0);
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scn_seg : out std_logic_vector(3 downto 0);
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scn_seg : out std_logic_vector(3 downto 0);
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led_green : out std_logic;
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led_green : out std_logic;
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led_red : out std_logic;
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led_red : out std_logic;
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--flash interface
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--flash interface
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fl_addr : out std_logic_vector(23 downto 0);
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fl_addr : out std_logic_vector(23 downto 0);
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fl_ce_n : out std_logic; --chip select
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fl_ce_n : out std_logic; --chip select
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fl_oe_n : out std_logic; --output enable for flash
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fl_oe_n : out std_logic; --output enable for flash
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fl_we_n : out std_logic; --write enable
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fl_we_n : out std_logic; --write enable
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fl_data : inout std_logic_vector(15 downto 0);
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fl_data : inout std_logic_vector(15 downto 0);
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fl_rp_n : out std_logic; --reset signal
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fl_rp_n : out std_logic; --reset signal
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fl_sts : in std_logic; --status signal
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fl_sts : in std_logic; --status signal
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fl_sts_en : out std_logic; --enable status signal wiht highZ out
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fl_sts_en : out std_logic; --enable status signal wiht highZ out
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--USB parallel interface
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--USB parallel interface
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usb_rd_n : inout std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
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usb_rd_n : inout std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
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usb_wr : inout std_logic; -- write performed on edge \ of signal
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usb_wr : inout std_logic; -- write performed on edge \ of signal
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usb_txe_n : in std_logic; -- transmit enable (redy for new data if low)
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usb_txe_n : in std_logic; -- transmit enable (redy for new data if low)
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usb_rxf_n : in std_logic; -- rx fifo has data if low
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usb_rxf_n : in std_logic; -- rx fifo has data if low
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usb_bd : inout std_logic_vector(7 downto 0) --bus data
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usb_bd : inout std_logic_vector(7 downto 0) --bus data
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);
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);
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end design_top_thincandbg;
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end design_top_thincandbg;
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architecture rtl of design_top_thincandbg is
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architecture rtl of design_top_thincandbg is
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component led_sys --toplevel for led system
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component led_sys --toplevel for led system
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generic(
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generic(
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msn_hib : std_logic_vector(7 downto 0); --Most signif. of hi byte
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msn_hib : std_logic_vector(7 downto 0); --Most signif. of hi byte
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lsn_hib : std_logic_vector(7 downto 0); --Least signif. of hi byte
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lsn_hib : std_logic_vector(7 downto 0); --Least signif. of hi byte
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msn_lob : std_logic_vector(7 downto 0); --Most signif. of hi byte
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msn_lob : std_logic_vector(7 downto 0); --Most signif. of hi byte
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lsn_lob : std_logic_vector(7 downto 0) --Least signif. of hi byte
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lsn_lob : std_logic_vector(7 downto 0) --Least signif. of hi byte
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);
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);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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reset_n : in std_logic;
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reset_n : in std_logic;
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led_data_i : in std_logic_vector(15 downto 0); --binary data in
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led_data_i : in std_logic_vector(15 downto 0); --binary data in
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seg_out : out std_logic_vector(7 downto 0); --one segment out
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seg_out : out std_logic_vector(7 downto 0); --one segment out
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sel_out : out std_logic_vector(3 downto 0) --segment scanner with one bit low
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sel_out : out std_logic_vector(3 downto 0) --segment scanner with one bit low
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);
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);
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end component;
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end component;
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component lpc_iow
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component lpc_iow
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port (
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port (
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--system signals
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--system signals
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lreset_n : in std_logic;
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lreset_n : in std_logic;
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lclk : in std_logic;
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lclk : in std_logic;
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lena_mem_r : in std_logic; --enable full adress range covering memory read block
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lena_mem_r : in std_logic; --enable full adress range covering memory read block
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lena_reads : in std_logic; --enable read capabilities
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lena_reads : in std_logic; --enable read capabilities
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--LPC bus from host
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--LPC bus from host
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lad_i : in std_logic_vector(3 downto 0);
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lad_i : in std_logic_vector(3 downto 0);
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lad_o : out std_logic_vector(3 downto 0);
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lad_o : out std_logic_vector(3 downto 0);
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lad_oe : out std_logic;
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lad_oe : out std_logic;
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lframe_n : in std_logic;
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lframe_n : in std_logic;
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--memory interface
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--memory interface
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lpc_addr : out std_logic_vector(23 downto 0); --shared address
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lpc_addr : out std_logic_vector(23 downto 0); --shared address
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lpc_wr : out std_logic; --shared write not read
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lpc_wr : out std_logic; --shared write not read
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lpc_data_i : in std_logic_vector(7 downto 0);
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lpc_data_i : in std_logic_vector(7 downto 0);
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lpc_data_o : out std_logic_vector(7 downto 0);
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lpc_data_o : out std_logic_vector(7 downto 0);
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lpc_val : out std_logic;
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lpc_val : out std_logic;
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lpc_ack : in std_logic
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lpc_ack : in std_logic
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);
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);
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end component;
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end component;
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component flash_if
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component flash_if
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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reset_n : in std_logic;
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reset_n : in std_logic;
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--flash Bus
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--flash Bus
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fl_addr : out std_logic_vector(23 downto 0);
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fl_addr : out std_logic_vector(23 downto 0);
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fl_ce_n : out std_logic; --chip select
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fl_ce_n : out std_logic; --chip select
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fl_oe_n : out std_logic; --output enable for flash
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fl_oe_n : out std_logic; --output enable for flash
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fl_we_n : out std_logic; --write enable
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fl_we_n : out std_logic; --write enable
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fl_data : inout std_logic_vector(15 downto 0);
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fl_data : inout std_logic_vector(15 downto 0);
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fl_rp_n : out std_logic; --reset signal
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fl_rp_n : out std_logic; --reset signal
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fl_byte_n : out std_logic; --hold in byte mode
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fl_byte_n : out std_logic; --hold in byte mode
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fl_sts : in std_logic; --status signal
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fl_sts : in std_logic; --status signal
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-- mem Bus
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-- mem Bus
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mem_addr : in std_logic_vector(23 downto 0);
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mem_addr : in std_logic_vector(23 downto 0);
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mem_do : out std_logic_vector(15 downto 0);
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mem_do : out std_logic_vector(15 downto 0);
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mem_di : in std_logic_vector(15 downto 0);
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mem_di : in std_logic_vector(15 downto 0);
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mem_wr : in std_logic; --write not read signal
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mem_wr : in std_logic; --write not read signal
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mem_val : in std_logic;
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mem_val : in std_logic;
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mem_ack : out std_logic
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mem_ack : out std_logic
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);
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);
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end component;
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end component;
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component usb2mem
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component usb2mem
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port (
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port (
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clk25 : in std_logic;
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clk25 : in std_logic;
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reset_n : in std_logic;
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reset_n : in std_logic;
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dongle_ver: in std_logic_vector(15 downto 0);
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dongle_ver: in std_logic_vector(15 downto 0);
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-- mem Bus
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-- mem Bus
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mem_busy_n: in std_logic;
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mem_busy_n: in std_logic;
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mem_idle : out std_logic; -- '1' if controller is idle (flash is safe for LPC reads)
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mem_idle : out std_logic; -- '1' if controller is idle (flash is safe for LPC reads)
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mem_addr : out std_logic_vector(23 downto 0);
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mem_addr : out std_logic_vector(23 downto 0);
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mem_do : out std_logic_vector(15 downto 0);
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mem_do : out std_logic_vector(15 downto 0);
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mem_di : in std_logic_vector(15 downto 0);
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mem_di : in std_logic_vector(15 downto 0);
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mem_wr : out std_logic;
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mem_wr : out std_logic;
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mem_val : out std_logic;
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mem_val : out std_logic;
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mem_ack : in std_logic;
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mem_ack : in std_logic;
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mem_cmd : out std_logic;
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mem_cmd : out std_logic;
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-- USB port
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-- USB port
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usb_mode_en: in std_logic; -- enable this block
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usb_mode_en: in std_logic; -- enable this block
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usb_rd_n : out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
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usb_rd_n : out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
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usb_wr : out std_logic; -- write performed on edge \ of signal
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usb_wr : out std_logic; -- write performed on edge \ of signal
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usb_txe_n : in std_logic; -- tx fifo empty (redy for new data if low)
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usb_txe_n : in std_logic; -- tx fifo empty (redy for new data if low)
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usb_rxf_n : in std_logic; -- rx fifo empty (data redy if low)
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usb_rxf_n : in std_logic; -- rx fifo empty (data redy if low)
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usb_bd : inout std_logic_vector(7 downto 0) --bus data
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usb_bd : inout std_logic_vector(7 downto 0) --bus data
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);
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);
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end component;
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end component;
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component pc_serializer
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component pc_serializer
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Port ( --system signals
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Port ( --system signals
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sys_clk : in STD_LOGIC;
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sys_clk : in STD_LOGIC;
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resetn : in STD_LOGIC;
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resetn : in STD_LOGIC;
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--postcode data port
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--postcode data port
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dbg_data : in STD_LOGIC_VECTOR (7 downto 0);
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dbg_data : in STD_LOGIC_VECTOR (7 downto 0);
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dbg_wr : in STD_LOGIC; --write not read
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dbg_wr : in STD_LOGIC; --write not read
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dbg_full : out STD_LOGIC; --write not read
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dbg_full : out STD_LOGIC; --write not read
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dbg_almost_full : out STD_LOGIC;
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dbg_almost_full : out STD_LOGIC;
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dbg_usedw : out STD_LOGIC_VECTOR (12 DOWNTO 0);
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dbg_usedw : out STD_LOGIC_VECTOR (12 DOWNTO 0);
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--debug USB port
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--debug USB port
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dbg_usb_mode_en: in std_logic; -- enable this debug mode
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dbg_usb_mode_en: in std_logic; -- enable this debug mode
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dbg_usb_wr : out std_logic; -- write performed on edge \ of signal
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dbg_usb_wr : out std_logic; -- write performed on edge \ of signal
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dbg_usb_txe_n : in std_logic; -- tx fifo not full (redy for new data if low)
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dbg_usb_txe_n : in std_logic; -- tx fifo not full (redy for new data if low)
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dbg_usb_bd : inout std_logic_vector(7 downto 0) --bus data
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dbg_usb_bd : inout std_logic_vector(7 downto 0) --bus data
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);
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);
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end component;
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end component;
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--LED signals
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--LED signals
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signal data_to_disp : std_logic_vector(15 downto 0);
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signal data_to_disp : std_logic_vector(15 downto 0);
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--END LED SIGNALS
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--END LED SIGNALS
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--lpc signals
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--lpc signals
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signal lad_i : std_logic_vector(3 downto 0);
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signal lad_i : std_logic_vector(3 downto 0);
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signal lad_o : std_logic_vector(3 downto 0);
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signal lad_o : std_logic_vector(3 downto 0);
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signal lad_oe : std_logic;
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signal lad_oe : std_logic;
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signal lpc_debug : std_logic_vector(31 downto 0);
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signal lpc_debug : std_logic_vector(31 downto 0);
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signal lpc_debug_cnt : std_logic_vector(15 downto 0);
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signal lpc_debug_cnt : std_logic_vector(15 downto 0);
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signal lpc_addr : std_logic_vector(23 downto 0); --shared address
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signal lpc_addr : std_logic_vector(23 downto 0); --shared address
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signal lpc_data_o : std_logic_vector(7 downto 0);
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signal lpc_data_o : std_logic_vector(7 downto 0);
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signal lpc_data_i : std_logic_vector(7 downto 0);
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signal lpc_data_i : std_logic_vector(7 downto 0);
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signal lpc_wr : std_logic; --shared write not read
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signal lpc_wr : std_logic; --shared write not read
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signal lpc_ack : std_logic;
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signal lpc_ack : std_logic;
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signal lpc_val : std_logic;
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signal lpc_val : std_logic;
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signal lena_mem_r : std_logic; --enable full adress range covering memory read block
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signal lena_mem_r : std_logic; --enable full adress range covering memory read block
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signal lena_reads : std_logic; --enable/disables all read capabilty to make the device post code capturer
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signal lena_reads : std_logic; --enable/disables all read capabilty to make the device post code capturer
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signal c25_lpc_val : std_logic;
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signal c25_lpc_val : std_logic;
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signal c25_lpc_wr : std_logic; --shared write not read
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signal c25_lpc_wr : std_logic; --shared write not read
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signal c25_lpc_wr_long : std_logic; --for led debug data latching
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signal c25_lpc_wr_long : std_logic; --for led debug data latching
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signal c33_lpc_wr_long : std_logic; --for led debug data latching
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signal c33_lpc_wr_long : std_logic; --for led debug data latching
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signal c33_lpc_wr : std_logic; --for led debug data latching
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signal c33_lpc_wr : std_logic; --for led debug data latching
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signal c33_lpc_wr_wait: std_logic; --for led debug data latching
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signal c33_lpc_wr_wait: std_logic; --for led debug data latching
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signal c33_lpc_wr_waitd: std_logic; --for led debug data latching
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signal c33_lpc_wr_waitd: std_logic; --for led debug data latching
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signal c33_wr_cnt : std_logic_vector(23 downto 0); --for led debug data latching
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signal c33_wr_cnt : std_logic_vector(23 downto 0); --for led debug data latching
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--End lpc signals
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--End lpc signals
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--Flash signals
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--Flash signals
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signal mem_addr : std_logic_vector(23 downto 0);
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signal mem_addr : std_logic_vector(23 downto 0);
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signal mem_do : std_logic_vector(15 downto 0);
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signal mem_do : std_logic_vector(15 downto 0);
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signal mem_di : std_logic_vector(15 downto 0);
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signal mem_di : std_logic_vector(15 downto 0);
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signal mem_wr : std_logic; --write not read signal
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signal mem_wr : std_logic; --write not read signal
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signal mem_val : std_logic;
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signal mem_val : std_logic;
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signal mem_ack : std_logic;
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signal mem_ack : std_logic;
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signal c33_mem_ack : std_logic; --sync signal
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signal c33_mem_ack : std_logic; --sync signal
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signal fl_ce_n_w : std_logic; --chip select
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signal fl_ce_n_w : std_logic; --chip select
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signal fl_oe_n_w : std_logic; --output enable for flash
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signal fl_oe_n_w : std_logic; --output enable for flash
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--END flash signals
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--END flash signals
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--USB signals
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--USB signals
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signal dbg_data : STD_LOGIC_VECTOR (7 downto 0);
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signal dbg_data : STD_LOGIC_VECTOR (7 downto 0);
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signal c25_dbg_addr_d : STD_LOGIC_VECTOR (7 downto 0);
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signal c25_dbg_addr_d : STD_LOGIC_VECTOR (7 downto 0);
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signal c33_dbg_addr_d : STD_LOGIC_VECTOR (7 downto 0);
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signal c33_dbg_addr_d : STD_LOGIC_VECTOR (7 downto 0);
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signal dbg_wr : STD_LOGIC; --write not read
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signal dbg_wr : STD_LOGIC; --write not read
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signal dbg_full : STD_LOGIC; --write not read
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signal dbg_full : STD_LOGIC; --write not read
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signal dbg_almost_full : STD_LOGIC;
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signal dbg_almost_full : STD_LOGIC;
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signal dbg_usedw : STD_LOGIC_VECTOR (12 DOWNTO 0);
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signal dbg_usedw : STD_LOGIC_VECTOR (12 DOWNTO 0);
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signal force_4meg_n : std_logic;
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signal force_4meg_n : std_logic;
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signal dbg_usb_mode_en : std_logic;
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signal dbg_usb_mode_en : std_logic;
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signal usb_mode_en : std_logic;
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signal usb_mode_en : std_logic;
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signal mem_idle : std_logic;
|
signal mem_idle : std_logic;
|
signal umem_addr : std_logic_vector(23 downto 0);
|
signal umem_addr : std_logic_vector(23 downto 0);
|
signal umem_do : std_logic_vector(15 downto 0);
|
signal umem_do : std_logic_vector(15 downto 0);
|
signal umem_wr : std_logic;
|
signal umem_wr : std_logic;
|
signal umem_val : std_logic;
|
signal umem_val : std_logic;
|
signal umem_ack : std_logic;
|
signal umem_ack : std_logic;
|
signal umem_cmd : std_logic;
|
signal umem_cmd : std_logic;
|
signal enable_4meg: std_logic;
|
signal enable_4meg: std_logic;
|
signal dongle_con_n : std_logic;
|
signal dongle_con_n : std_logic;
|
|
|
constant dongle_ver : std_logic_vector(15 downto 0):=x"8606";
|
constant dongle_ver : std_logic_vector(15 downto 0):=x"8606";
|
--END USB signals
|
--END USB signals
|
|
|
begin
|
begin
|
|
|
--GPIO PINS START
|
--GPIO PINS START
|
fl_sts_en <='Z';
|
fl_sts_en <='Z';
|
|
|
hdr(1) <= dongle_con_n;
|
hdr(1) <= dongle_con_n;
|
--hdr(1) <= fl_sts when resetn='1' else
|
--hdr(1) <= fl_sts when resetn='1' else
|
-- '0';
|
-- '0';
|
|
|
--when jumper on then mem read and firmware read enabled else only firmware read
|
--when jumper on then mem read and firmware read enabled else only firmware read
|
hdr(0) <= 'Z';
|
hdr(0) <= 'Z';
|
lena_mem_r <= not hdr(0); -- disabled if jumper is not on header pins 1-2
|
lena_mem_r <= not hdr(0); -- disabled if jumper is not on header pins 1-2
|
|
|
-- jumper on pins 5,6 then postcode only mode (no mem device)
|
-- jumper on pins 5,6 then postcode only mode (no mem device)
|
hdr(2) <= '0'; --create low pin for jumper pair 5-6 (this pin is 6 on J1 header)
|
hdr(2) <= '0'; --create low pin for jumper pair 5-6 (this pin is 6 on J1 header)
|
lena_reads <= hdr(3) and mem_idle and (not dongle_con_n); -- disabled if jumper is on (jumper makes it a postcode only device) paired with hdr(2) pins 5,6 and when usb control is not accessing flash
|
lena_reads <= hdr(3) and mem_idle and (not dongle_con_n); -- disabled if jumper is on (jumper makes it a postcode only device) paired with hdr(2) pins 5,6 and when usb control is not accessing flash
|
|
|
|
|
-- when jumper on pins 7,8 then post code capture mode enabled
|
-- when jumper on pins 7,8 then post code capture mode enabled
|
hdr(4)<= '0';
|
hdr(4)<= '0';
|
dbg_usb_mode_en <= not hdr(5); --weak pullup on hdr(5) paired with hdr(4)
|
dbg_usb_mode_en <= not hdr(5); --weak pullup on hdr(5) paired with hdr(4)
|
usb_mode_en <= not dbg_usb_mode_en;
|
usb_mode_en <= not dbg_usb_mode_en;
|
|
|
-- when jumper on pins 9,10 then 4M window is forced
|
-- when jumper on pins 9,10 then 4M window is forced
|
hdr(6)<= '0';
|
hdr(6)<= '0';
|
force_4meg_n <= hdr(7); --weak pullup on hdr(7) paired with hdr(6)
|
force_4meg_n <= hdr(7); --weak pullup on hdr(7) paired with hdr(6)
|
|
|
--GPIO PINS END
|
--GPIO PINS END
|
|
|
--LED SUBSYSTEM START
|
--LED SUBSYSTEM START
|
data_to_disp <= x"86"&lpc_debug(7 downto 0) when usb_mode_en='1' else --x"C0DE"; -- ASSIGN data to be displayed (should be regitered)
|
data_to_disp <= x"86"&lpc_debug(7 downto 0) when usb_mode_en='1' else --x"C0DE"; -- ASSIGN data to be displayed (should be regitered)
|
"000"&dbg_usedw; --show tx fifo state on leds when postcode capture mode
|
"000"&dbg_usedw; --show tx fifo state on leds when postcode capture mode
|
--########################################--
|
--########################################--
|
--VERSION CONSTATNS
|
--VERSION CONSTATNS
|
--########################################--
|
--########################################--
|
led_red <= enable_4meg;
|
led_red <= enable_4meg;
|
|
|
LEDS: led_sys --toplevel for led system
|
LEDS: led_sys --toplevel for led system
|
generic map(
|
generic map(
|
msn_hib => "01111111",--8 --Most signif. of hi byte
|
msn_hib => "01111111",--8 --Most signif. of hi byte
|
lsn_hib => "01111101",--6 --Least signif. of hi byte
|
lsn_hib => "01111101",--6 --Least signif. of hi byte
|
msn_lob => "10111111",--0 --Most signif. of hi byte This is version code
|
msn_lob => "10111111",--0 --Most signif. of hi byte This is version code
|
--lsn_lob => "01001111" --3 --Least signif. of hi byte This is version code
|
--lsn_lob => "01001111" --3 --Least signif. of hi byte This is version code
|
--lsn_lob => "01100110" --4 --Least signif. of hi byte This is version code
|
--lsn_lob => "01100110" --4 --Least signif. of hi byte This is version code
|
--lsn_lob => "01101101" --5 --sync with dongle version const. Least signif. of hi byte This is version code
|
--lsn_lob => "01101101" --5 --sync with dongle version const. Least signif. of hi byte This is version code
|
lsn_lob => "01111101" --6 --sync with dongle version const. Least signif. of hi byte This is version code
|
lsn_lob => "01111101" --6 --sync with dongle version const. Least signif. of hi byte This is version code
|
|
|
)
|
)
|
port map(
|
port map(
|
clk => sys_clk , -- in std_logic;
|
clk => sys_clk , -- in std_logic;
|
reset_n => resetn, -- in std_logic;
|
reset_n => resetn, -- in std_logic;
|
led_data_i => data_to_disp, -- in std_logic_vector(15 downto 0); --binary data in
|
led_data_i => data_to_disp, -- in std_logic_vector(15 downto 0); --binary data in
|
seg_out => seg_out, -- out std_logic_vector(7 downto 0); --one segment out
|
seg_out => seg_out, -- out std_logic_vector(7 downto 0); --one segment out
|
sel_out => scn_seg -- out std_logic_vector(3 downto 0) --segment scanner with one bit low
|
sel_out => scn_seg -- out std_logic_vector(3 downto 0) --segment scanner with one bit low
|
);
|
);
|
|
|
--LED SUBSYSTEM END
|
--LED SUBSYSTEM END
|
|
|
|
|
--MAIN DATAPATH CONNECTIONS
|
--MAIN DATAPATH CONNECTIONS
|
--LPC bus logic
|
--LPC bus logic
|
lad_i <= lad;
|
lad_i <= lad;
|
lad <= lad_o when lad_oe='1' else
|
lad <= lad_o when lad_oe='1' else
|
(others=>'Z');
|
(others=>'Z');
|
|
|
--END LPC bus logic
|
--END LPC bus logic
|
|
|
LPCBUS : lpc_iow
|
LPCBUS : lpc_iow
|
port map(
|
port map(
|
--system signals
|
--system signals
|
lreset_n => lreset_n, -- in std_logic;
|
lreset_n => lreset_n, -- in std_logic;
|
lclk => lclk, -- in std_logic;
|
lclk => lclk, -- in std_logic;
|
lena_mem_r => lena_mem_r, --: in std_logic; --enable full adress range covering memory read block
|
lena_mem_r => lena_mem_r, --: in std_logic; --enable full adress range covering memory read block
|
lena_reads => lena_reads, -- : in std_logic; --enable read capabilities, : in std_logic; --enable read capabilities
|
lena_reads => lena_reads, -- : in std_logic; --enable read capabilities, : in std_logic; --enable read capabilities
|
--LPC bus from host
|
--LPC bus from host
|
lad_i => lad_i, -- in std_logic_vector(3 downto 0);
|
lad_i => lad_i, -- in std_logic_vector(3 downto 0);
|
lad_o => lad_o, -- out std_logic_vector(3 downto 0);
|
lad_o => lad_o, -- out std_logic_vector(3 downto 0);
|
lad_oe => lad_oe, -- out std_logic;
|
lad_oe => lad_oe, -- out std_logic;
|
lframe_n => lframe_n, -- in std_logic;
|
lframe_n => lframe_n, -- in std_logic;
|
--memory interface
|
--memory interface
|
lpc_addr => lpc_addr, -- out std_logic_vector(23 downto 0); --shared address
|
lpc_addr => lpc_addr, -- out std_logic_vector(23 downto 0); --shared address
|
lpc_wr => lpc_wr, -- out std_logic; --shared write not read
|
lpc_wr => lpc_wr, -- out std_logic; --shared write not read
|
lpc_data_i => lpc_data_i, -- in std_logic_vector(7 downto 0);
|
lpc_data_i => lpc_data_i, -- in std_logic_vector(7 downto 0);
|
lpc_data_o => lpc_data_o, -- out std_logic_vector(7 downto 0);
|
lpc_data_o => lpc_data_o, -- out std_logic_vector(7 downto 0);
|
lpc_val => lpc_val, -- out std_logic;
|
lpc_val => lpc_val, -- out std_logic;
|
lpc_ack => lpc_ack -- in std_logic
|
lpc_ack => lpc_ack -- in std_logic
|
);
|
);
|
|
|
|
|
--memory data bus logic
|
--memory data bus logic
|
mem_addr <= mode&"11"&lpc_addr(19 downto 0) when c25_lpc_val='1' and enable_4meg='0' else --use mode bist
|
mem_addr <= mode&"11"&lpc_addr(19 downto 0) when c25_lpc_val='1' and enable_4meg='0' else --use mode bist
|
mode&lpc_addr(21 downto 0) when c25_lpc_val='1' and enable_4meg='1' else --use mode bist
|
mode&lpc_addr(21 downto 0) when c25_lpc_val='1' and enable_4meg='1' else --use mode bist
|
mode&umem_addr(21 downto 0) when umem_val='1' else --use mode bist
|
mode&umem_addr(21 downto 0) when umem_val='1' else --use mode bist
|
(others=>'Z');
|
(others=>'Z');
|
|
|
mem_di <= (others=>'Z') when c25_lpc_val='1' else
|
mem_di <= (others=>'Z') when c25_lpc_val='1' else
|
umem_do when umem_val='1' else
|
umem_do when umem_val='1' else
|
(others=>'Z');
|
(others=>'Z');
|
|
|
|
|
mem_wr <= c25_lpc_wr when c25_lpc_val='1' and c25_lpc_wr='0' else --pass read olny
|
mem_wr <= c25_lpc_wr when c25_lpc_val='1' and c25_lpc_wr='0' else --pass read olny
|
umem_wr when umem_val='1' else
|
umem_wr when umem_val='1' else
|
'0';
|
'0';
|
|
|
mem_val <= c25_lpc_val or umem_val;
|
mem_val <= c25_lpc_val or umem_val;
|
|
|
|
|
|
|
umem_ack <= mem_ack when umem_val='1' else
|
umem_ack <= mem_ack when umem_val='1' else
|
'0';
|
'0';
|
|
|
|
|
lpc_data_i <= mem_do(7 downto 0) when lpc_addr(0)='0' else
|
lpc_data_i <= mem_do(7 downto 0) when lpc_addr(0)='0' else
|
mem_do(15 downto 8);
|
mem_do(15 downto 8);
|
|
|
lpc_ack <= c33_mem_ack when lpc_val='1' and lpc_wr='0' else
|
lpc_ack <= c33_mem_ack when lpc_val='1' and lpc_wr='0' else
|
(not dbg_almost_full) when lpc_val='1' and lpc_wr='1' else
|
(not dbg_almost_full) when lpc_val='1' and lpc_wr='1' else
|
'0';
|
'0';
|
|
|
|
|
|
|
SYNC1: process (lclk, lreset_n) --c33
|
SYNC1: process (lclk, lreset_n) --c33
|
begin
|
begin
|
if lclk'event and lclk = '1' then -- rising clock edge
|
if lclk'event and lclk = '1' then -- rising clock edge
|
c33_mem_ack <= mem_ack;
|
c33_mem_ack <= mem_ack;
|
|
|
end if;
|
end if;
|
end process SYNC1;
|
end process SYNC1;
|
|
|
|
|
dbg_data <= lpc_debug(7 downto 0);
|
dbg_data <= lpc_debug(7 downto 0);
|
SYNC2: process (sys_clk) --c25
|
SYNC2: process (sys_clk) --c25
|
begin
|
begin
|
if sys_clk'event and sys_clk = '1' then -- rising clock edge
|
if sys_clk'event and sys_clk = '1' then -- rising clock edge
|
c25_lpc_val <= lpc_val; --syncro two clock domains
|
c25_lpc_val <= lpc_val; --syncro two clock domains
|
c25_lpc_wr <= c33_lpc_wr; --syncro two clock domains
|
c25_lpc_wr <= c33_lpc_wr; --syncro two clock domains
|
c25_dbg_addr_d <= c33_dbg_addr_d; --syncro two clock domains
|
c25_dbg_addr_d <= c33_dbg_addr_d; --syncro two clock domains
|
if usb_mode_en ='0' and c25_dbg_addr_d=x"80" then --don't fill fifo in regular mode
|
if usb_mode_en ='0' and c25_dbg_addr_d=x"80" then --don't fill fifo in regular mode
|
dbg_wr<= c25_lpc_wr; --c33_lpc_wr_wait;--c33_lpc_wr_wait;
|
dbg_wr<= c25_lpc_wr; --c33_lpc_wr_wait;--c33_lpc_wr_wait;
|
else
|
else
|
dbg_wr<='0'; --write never rises when usb_mode_en = 1
|
dbg_wr<='0'; --write never rises when usb_mode_en = 1
|
end if;
|
end if;
|
end if;
|
end if;
|
end process SYNC2;
|
end process SYNC2;
|
|
|
|
|
|
|
LATCHled: process (lclk,lreset_n) --c33
|
LATCHled: process (lclk,lreset_n) --c33
|
begin
|
begin
|
if lreset_n='0' then
|
if lreset_n='0' then
|
lpc_debug(7 downto 0)<=(others=>'0');
|
lpc_debug(7 downto 0)<=(others=>'0');
|
c33_dbg_addr_d <=(others=>'0');
|
c33_dbg_addr_d <=(others=>'0');
|
enable_4meg <='0';
|
enable_4meg <='0';
|
c33_lpc_wr <='0';
|
c33_lpc_wr <='0';
|
dongle_con_n <='0'; -- pin 3 in GPIO make it toggleable
|
dongle_con_n <='0'; -- pin 3 in GPIO make it toggleable
|
elsif lclk'event and lclk = '1' then -- rising clock edge
|
elsif lclk'event and lclk = '1' then -- rising clock edge
|
c33_lpc_wr <= lpc_wr;
|
c33_lpc_wr <= lpc_wr;
|
if c33_lpc_wr='0' and lpc_wr='1' then
|
if c33_lpc_wr='0' and lpc_wr='1' then
|
c33_dbg_addr_d <= lpc_addr(7 downto 0);
|
c33_dbg_addr_d <= lpc_addr(7 downto 0);
|
lpc_debug(7 downto 0)<= lpc_data_o;
|
lpc_debug(7 downto 0)<= lpc_data_o;
|
if lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"F4" then --Flash 4 Mega enable (LSN is first MSN is second)
|
if lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"F4" then --Flash 4 Mega enable (LSN is first MSN is second)
|
enable_4meg <='1';
|
enable_4meg <='1';
|
elsif lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"F1" then --Flash 1 Mega enalbe
|
elsif lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"F1" then --Flash 1 Mega enalbe
|
enable_4meg <='0';
|
enable_4meg <='0';
|
elsif lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"D1" then --Set Dongle not attached signal
|
elsif lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"D1" then --Set Dongle not attached signal
|
dongle_con_n <='1'; -- pin 3 in GPIO make it 1
|
dongle_con_n <='1'; -- pin 3 in GPIO make it 1
|
elsif lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"D0" then --Set Dongle attached signal
|
elsif lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"D0" then --Set Dongle attached signal
|
dongle_con_n <='0'; -- pin 3 in GPIO make it 1
|
dongle_con_n <='0'; -- pin 3 in GPIO make it 1
|
end if;
|
end if;
|
else
|
else
|
if force_4meg_n='0' then -- active low (always force when jumper on)
|
if force_4meg_n='0' then -- active low (always force when jumper on)
|
enable_4meg <='1';
|
enable_4meg <='1';
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process LATCHled;
|
end process LATCHled;
|
|
|
|
|
|
|
|
|
|
|
|
|
--END memory data bus logic
|
--END memory data bus logic
|
fl_ce_n<= fl_ce_n_w;
|
fl_ce_n<= fl_ce_n_w;
|
fl_oe_n<= fl_oe_n_w;
|
fl_oe_n<= fl_oe_n_w;
|
|
|
FLASH : flash_if
|
FLASH : flash_if
|
port map(
|
port map(
|
clk => sys_clk, -- in std_logic;
|
clk => sys_clk, -- in std_logic;
|
reset_n => resetn, -- in std_logic;
|
reset_n => resetn, -- in std_logic;
|
--flash Bus
|
--flash Bus
|
fl_addr => fl_addr, -- out std_logic_vector(23 downto 0);
|
fl_addr => fl_addr, -- out std_logic_vector(23 downto 0);
|
fl_ce_n => fl_ce_n_w, -- out std_logic; --chip select
|
fl_ce_n => fl_ce_n_w, -- out std_logic; --chip select
|
fl_oe_n => fl_oe_n_w, -- buffer std_logic; --output enable for flash
|
fl_oe_n => fl_oe_n_w, -- buffer std_logic; --output enable for flash
|
fl_we_n => fl_we_n, -- out std_logic; --write enable
|
fl_we_n => fl_we_n, -- out std_logic; --write enable
|
fl_data => fl_data, -- inout std_logic_vector(15 downto 0);
|
fl_data => fl_data, -- inout std_logic_vector(15 downto 0);
|
fl_rp_n => fl_rp_n, -- out std_logic; --reset signal
|
fl_rp_n => fl_rp_n, -- out std_logic; --reset signal
|
--fl_byte_n => fl_byte_n, -- out std_logic; --hold in byte mode
|
--fl_byte_n => fl_byte_n, -- out std_logic; --hold in byte mode
|
fl_sts => fl_sts, -- in std_logic; --status signal
|
fl_sts => fl_sts, -- in std_logic; --status signal
|
-- mem Bus
|
-- mem Bus
|
mem_addr => mem_addr, -- in std_logic_vector(23 downto 0);
|
mem_addr => mem_addr, -- in std_logic_vector(23 downto 0);
|
mem_do => mem_do, -- out std_logic_vector(15 downto 0);
|
mem_do => mem_do, -- out std_logic_vector(15 downto 0);
|
mem_di => mem_di, -- in std_logic_vector(15 downto 0);
|
mem_di => mem_di, -- in std_logic_vector(15 downto 0);
|
|
|
mem_wr => mem_wr, -- in std_logic; --write not read signal
|
mem_wr => mem_wr, -- in std_logic; --write not read signal
|
mem_val => mem_val, -- in std_logic;
|
mem_val => mem_val, -- in std_logic;
|
mem_ack => mem_ack -- out std_logic
|
mem_ack => mem_ack -- out std_logic
|
);
|
);
|
|
|
|
|
|
|
USB: usb2mem
|
USB: usb2mem
|
port map(
|
port map(
|
clk25 => sys_clk, -- in std_logic;
|
clk25 => sys_clk, -- in std_logic;
|
reset_n => resetn, -- in std_logic;
|
reset_n => resetn, -- in std_logic;
|
dongle_ver => dongle_ver,
|
dongle_ver => dongle_ver,
|
-- mem Bus
|
-- mem Bus
|
mem_busy_n=> fl_sts, --check flash status before starting new command on flash
|
mem_busy_n=> fl_sts, --check flash status before starting new command on flash
|
mem_idle => mem_idle,
|
mem_idle => mem_idle,
|
mem_addr => umem_addr, -- out std_logic_vector(23 downto 0);
|
mem_addr => umem_addr, -- out std_logic_vector(23 downto 0);
|
mem_do => umem_do, -- out std_logic_vector(15 downto 0);
|
mem_do => umem_do, -- out std_logic_vector(15 downto 0);
|
mem_di => mem_do, -- in std_logic_vector(15 downto 0); --from flash
|
mem_di => mem_do, -- in std_logic_vector(15 downto 0); --from flash
|
mem_wr => umem_wr, -- out std_logic;
|
mem_wr => umem_wr, -- out std_logic;
|
mem_val => umem_val, -- out std_logic;
|
mem_val => umem_val, -- out std_logic;
|
mem_ack => umem_ack, -- in std_logic; --from flash
|
mem_ack => umem_ack, -- in std_logic; --from flash
|
mem_cmd => umem_cmd, -- out std_logic;
|
mem_cmd => umem_cmd, -- out std_logic;
|
-- USB port
|
-- USB port
|
usb_mode_en => usb_mode_en,
|
usb_mode_en => usb_mode_en,
|
usb_rd_n => usb_rd_n, -- out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
|
usb_rd_n => usb_rd_n, -- out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
|
usb_wr => usb_wr, -- out std_logic; -- write performed on edge \ of signal
|
usb_wr => usb_wr, -- out std_logic; -- write performed on edge \ of signal
|
usb_txe_n => usb_txe_n, -- in std_logic; -- tx fifo empty (redy for new data if low)
|
usb_txe_n => usb_txe_n, -- in std_logic; -- tx fifo empty (redy for new data if low)
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usb_rxf_n => usb_rxf_n, -- in std_logic; -- rx fifo empty (data redy if low)
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usb_rxf_n => usb_rxf_n, -- in std_logic; -- rx fifo empty (data redy if low)
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usb_bd => usb_bd -- inout std_logic_vector(7 downto 0) --bus data
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usb_bd => usb_bd -- inout std_logic_vector(7 downto 0) --bus data
|
);
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);
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|
|
|
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DBG : pc_serializer
|
DBG : pc_serializer
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port map ( --system signals
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port map ( --system signals
|
sys_clk => sys_clk, -- in STD_LOGIC;
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sys_clk => sys_clk, -- in STD_LOGIC;
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resetn => resetn, -- in STD_LOGIC;
|
resetn => resetn, -- in STD_LOGIC;
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--postcode data port
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--postcode data port
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dbg_data => dbg_data, -- in STD_LOGIC_VECTOR (7 downto 0);
|
dbg_data => dbg_data, -- in STD_LOGIC_VECTOR (7 downto 0);
|
dbg_wr => dbg_wr, -- in STD_LOGIC; --write not read
|
dbg_wr => dbg_wr, -- in STD_LOGIC; --write not read
|
dbg_full => dbg_full,--: out STD_LOGIC; --write not read
|
dbg_full => dbg_full,--: out STD_LOGIC; --write not read
|
dbg_almost_full => dbg_almost_full,
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dbg_almost_full => dbg_almost_full,
|
dbg_usedw => dbg_usedw,
|
dbg_usedw => dbg_usedw,
|
|
|
--debug USB port
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--debug USB port
|
dbg_usb_mode_en=> dbg_usb_mode_en, -- in std_logic; -- enable this debug mode
|
dbg_usb_mode_en=> dbg_usb_mode_en, -- in std_logic; -- enable this debug mode
|
dbg_usb_wr => usb_wr, -- out std_logic; -- write performed on edge \ of signal
|
dbg_usb_wr => usb_wr, -- out std_logic; -- write performed on edge \ of signal
|
dbg_usb_txe_n => usb_txe_n, -- in std_logic; -- tx fifo not full (redy for new data if low)
|
dbg_usb_txe_n => usb_txe_n, -- in std_logic; -- tx fifo not full (redy for new data if low)
|
dbg_usb_bd => usb_bd -- inout std_logic_vector(7 downto 0) --bus data
|
dbg_usb_bd => usb_bd -- inout std_logic_vector(7 downto 0) --bus data
|
);
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);
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|
|
|
|
--END MAIN DATAPATH CONNECTIONS
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--END MAIN DATAPATH CONNECTIONS
|
|
|
end rtl;
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end rtl;
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