------------------------------------------------------------------
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------------------------------------------------------------------
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-- Universal dongle board source code
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-- Universal dongle board source code
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--
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--
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-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>
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-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>
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--
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--
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-- This source code is free hardware; you can redistribute it and/or
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-- This source code is free hardware; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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-- version 2.1 of the License, or (at your option) any later version.
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--
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--
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-- This source code is distributed in the hope that it will be useful,
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-- This source code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Lesser General Public License for more details.
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-- Lesser General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU Lesser General Public
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-- You should have received a copy of the GNU Lesser General Public
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-- License along with this library; if not, write to the Free Software
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-- License along with this library; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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--
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--
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-- The complete text of the GNU Lesser General Public License can be found in
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-- The complete text of the GNU Lesser General Public License can be found in
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-- the file 'lesser.txt'.
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-- the file 'lesser.txt'.
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_arith.all;
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entity flash_if is
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entity flash_if is
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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reset_n : in std_logic;
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reset_n : in std_logic;
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--flash Bus
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--flash Bus
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fl_addr : out std_logic_vector(23 downto 0);
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fl_addr : out std_logic_vector(23 downto 0);
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fl_ce_n : out std_logic; --chip select (timing is very chip dependent)
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fl_ce_n : out std_logic; --chip select (timing is very chip dependent)
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fl_oe_n : out std_logic; --output enable for flash (timing is very chip dependent)
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fl_oe_n : out std_logic; --output enable for flash (timing is very chip dependent)
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fl_we_n : out std_logic; --write enable (timing is very chip dependent)
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fl_we_n : out std_logic; --write enable (timing is very chip dependent)
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fl_data : inout std_logic_vector(15 downto 0);
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fl_data : inout std_logic_vector(15 downto 0);
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fl_rp_n : out std_logic; --reset signal
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fl_rp_n : out std_logic; --reset signal
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fl_byte_n : out std_logic; --hold in byte mode
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fl_byte_n : out std_logic; --hold in byte mode
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fl_sts : in std_logic; --status signal
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fl_sts : in std_logic; --status signal
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-- mem Bus
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-- mem Bus
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mem_addr : in std_logic_vector(23 downto 0);
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mem_addr : in std_logic_vector(23 downto 0);
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mem_do : out std_logic_vector(15 downto 0);
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mem_do : out std_logic_vector(15 downto 0);
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mem_di : in std_logic_vector(15 downto 0);
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mem_di : in std_logic_vector(15 downto 0);
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mem_wr : in std_logic; --write not read signal
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mem_wr : in std_logic; --write not read signal
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mem_val : in std_logic;
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mem_val : in std_logic;
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mem_ack : out std_logic
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mem_ack : out std_logic
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);
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);
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end flash_if;
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end flash_if;
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architecture RTL of flash_if is
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architecture RTL of flash_if is
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type state_type is (RESETs,FLREADs,FLWRITEs,WAITs);
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type state_type is (RESETs,FLREADs,FLWRITEs,WAITs);
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signal CS : state_type;
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signal CS : state_type;
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signal fl_cnt : std_logic_vector(3 downto 0);
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signal fl_cnt : std_logic_vector(3 downto 0);
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signal fl_oe_nd : std_logic; --output enable for flash
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signal fl_oe_nd : std_logic; --output enable for flash
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begin
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begin
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fl_rp_n <= reset_n; --make flash reset
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fl_rp_n <= reset_n; --make flash reset
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fl_addr <= mem_addr(23 downto 0);
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fl_addr <= mem_addr(23 downto 0);
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fl_byte_n <= '0'; --all byte accesses
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fl_byte_n <= '0'; --all byte accesses
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fl_oe_n<=fl_oe_nd;
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fl_oe_n<=fl_oe_nd;
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fl_data <= mem_di when fl_oe_nd ='1' else
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fl_data <= mem_di when fl_oe_nd ='1' else
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(others =>'Z');
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(others =>'Z');
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RD: process (clk, reset_n)
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RD: process (clk, reset_n)
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begin -- process READ
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begin -- process READ
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if reset_n='0' then
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if reset_n='0' then
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fl_oe_nd <='1';
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fl_oe_nd <='1';
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CS <= RESETs;
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CS <= RESETs;
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fl_cnt <= (others=>'0');
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fl_cnt <= (others=>'0');
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mem_do <= (others=>'0');
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mem_do <= (others=>'0');
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mem_ack <='0';
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mem_ack <='0';
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elsif clk'event and clk = '1' then -- rising clock edge
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elsif clk'event and clk = '1' then -- rising clock edge
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case CS is
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case CS is
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when RESETs =>
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when RESETs =>
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mem_ack <='0';
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mem_ack <='0';
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fl_ce_n <= (not mem_val); --chipselect 4 flash
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fl_ce_n <= (not mem_val); --chipselect 4 flash
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fl_we_n <= (not (mem_val and mem_wr)); --write enable 4 flash
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fl_we_n <= (not (mem_val and mem_wr)); --write enable 4 flash
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if mem_val='1' and mem_wr = '0' then --READ
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if mem_val='1' and mem_wr = '0' then --READ
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fl_oe_nd <='0';
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fl_oe_nd <='0';
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fl_cnt <= (others=>'0');
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fl_cnt <= (others=>'0');
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CS <= FLREADs;
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CS <= FLREADs;
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elsif mem_val='1' and mem_wr = '1' then --WRITE
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elsif mem_val='1' and mem_wr = '1' then --WRITE
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fl_oe_nd <='1';
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fl_oe_nd <='1';
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fl_cnt <= (others=>'0');
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fl_cnt <= (others=>'0');
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CS <= FLWRITEs;
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CS <= FLWRITEs;
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end if; --elsif mem_cmd
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end if; --elsif mem_cmd
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when FLREADs =>
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when FLREADs =>
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fl_cnt <= fl_cnt + 1;
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fl_cnt <= fl_cnt + 1;
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if fl_cnt=x"3" then --3 cycles later
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if fl_cnt=x"3" then --3 cycles later
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mem_ack <='1';
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mem_ack <='1';
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mem_do <= fl_data; --registered is nicer
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mem_do <= fl_data; --registered is nicer
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elsif fl_cnt=x"4" then --4 cycles later
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elsif fl_cnt=x"4" then --4 cycles later
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mem_ack <='0';
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mem_ack <='0';
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fl_oe_nd <='1';
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fl_oe_nd <='1';
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CS <= WAITs;
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CS <= WAITs;
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end if;
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end if;
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when FLWRITEs =>
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when FLWRITEs =>
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fl_cnt <= fl_cnt + 1;
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fl_cnt <= fl_cnt + 1;
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if fl_cnt=x"3" then --3 cycles later
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if fl_cnt=x"3" then --3 cycles later
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mem_ack <='1';
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mem_ack <='1';
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elsif fl_cnt=x"4" then --4 cycles later
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elsif fl_cnt=x"4" then --4 cycles later
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mem_ack <='0';
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mem_ack <='0';
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CS <= WAITs;
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CS <= WAITs;
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end if;
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end if;
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when WAITs =>
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when WAITs =>
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if mem_val='0' then -- wait untill val is removed
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if mem_val='0' then -- wait untill val is removed
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CS <= RESETs;
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CS <= RESETs;
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end if;
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end if;
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end case;
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end case;
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end if; --system
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end if; --system
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end process RD;
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end process RD;
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end RTL;
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end RTL;
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