--Copyright (C) 1991-2006 Altera Corporation
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--Copyright (C) 1991-2006 Altera Corporation
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--Your use of Altera Corporation's design tools, logic functions
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--Your use of Altera Corporation's design tools, logic functions
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--and other software and tools, and its AMPP partner logic
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--and other software and tools, and its AMPP partner logic
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--functions, and any output files any of the foregoing
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--functions, and any output files any of the foregoing
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--(including device programming or simulation files), and any
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--(including device programming or simulation files), and any
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--associated documentation or information are expressly subject
|
--associated documentation or information are expressly subject
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--to the terms and conditions of the Altera Program License
|
--to the terms and conditions of the Altera Program License
|
--Subscription Agreement, Altera MegaCore Function License
|
--Subscription Agreement, Altera MegaCore Function License
|
--Agreement, or other applicable license agreement, including,
|
--Agreement, or other applicable license agreement, including,
|
--without limitation, that your use is for the sole purpose of
|
--without limitation, that your use is for the sole purpose of
|
--programming logic devices manufactured by Altera and sold by
|
--programming logic devices manufactured by Altera and sold by
|
--Altera or its authorized distributors. Please refer to the
|
--Altera or its authorized distributors. Please refer to the
|
--applicable agreement for further details.
|
--applicable agreement for further details.
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component fifo
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component fifo
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PORT
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PORT
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(
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(
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aclr : IN STD_LOGIC ;
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aclr : IN STD_LOGIC ;
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clock : IN STD_LOGIC ;
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clock : IN STD_LOGIC ;
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data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
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data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
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rdreq : IN STD_LOGIC ;
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rdreq : IN STD_LOGIC ;
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wrreq : IN STD_LOGIC ;
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wrreq : IN STD_LOGIC ;
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almost_full : OUT STD_LOGIC ;
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almost_full : OUT STD_LOGIC ;
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empty : OUT STD_LOGIC ;
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empty : OUT STD_LOGIC ;
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full : OUT STD_LOGIC ;
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full : OUT STD_LOGIC ;
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q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
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q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
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usedw : OUT STD_LOGIC_VECTOR (12 DOWNTO 0)
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usedw : OUT STD_LOGIC_VECTOR (12 DOWNTO 0)
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);
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);
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end component;
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end component;
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