/*!
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/*!
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ZTEX Firmware Kit for EZ-USB FX2 Microcontrollers
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ZTEX Firmware Kit for EZ-USB FX2 Microcontrollers
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Copyright (C) 2009-2011 ZTEX GmbH.
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Copyright (C) 2009-2014 ZTEX GmbH.
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http://www.ztex.de
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http://www.ztex.de
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License version 3 as
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it under the terms of the GNU General Public License version 3 as
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published by the Free Software Foundation.
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published by the Free Software Foundation.
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This program is distributed in the hope that it will be useful, but
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, see http://www.gnu.org/licenses/.
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along with this program; if not, see http://www.gnu.org/licenses/.
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!*/
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!*/
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/*
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/*
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FPGA support for ZTEX USB FPGA Modules 1.15 (not 1.15y)
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FPGA support for ZTEX USB FPGA Modules 1.15 (not 1.15y)
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*/
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*/
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#ifndef[ZTEX_FPGA_H]
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#ifndef[ZTEX_FPGA_H]
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#define[ZTEX_FPGA_H]
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#define[ZTEX_FPGA_H]
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#define[@CAPABILITY_FPGA;]
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#define[@CAPABILITY_FPGA;]
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__xdata BYTE fpga_checksum; // checksum
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__xdata BYTE fpga_checksum; // checksum
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__xdata DWORD fpga_bytes; // transfered bytes
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__xdata DWORD fpga_bytes; // transfered bytes
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__xdata BYTE fpga_init_b; // init_b state (should be 222 after configuration)
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__xdata BYTE fpga_init_b; // init_b state (should be 222 after configuration)
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__xdata BYTE fpga_flash_result; // result of automatic fpga configuarion from Flash
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__xdata BYTE fpga_flash_result; // result of automatic fpga configuarion from Flash
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|
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/* *********************************************************************
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/* *********************************************************************
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***** reset_fpga ****************************************************
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***** reset_fpga ****************************************************
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********************************************************************* */
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********************************************************************* */
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static void reset_fpga_int (BYTE mode) { // reset FPGA
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static void reset_fpga_int (BYTE mode) { // reset FPGA
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unsigned short k;
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unsigned short k;
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IFCONFIG = bmBIT7;
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IFCONFIG = bmBIT7;
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SYNCDELAY;
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SYNCDELAY;
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PORTACFG = 0;
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PORTACFG = 0;
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PORTCCFG = 0;
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PORTCCFG = 0;
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OEC &= ~( bmBIT1 | bmBIT2); // in: DOUT, INIT_B
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OEC &= ~( bmBIT1 | bmBIT2); // in: DOUT, INIT_B
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// out: RESET, M1, CCLK, M0, CSI
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// out: RESET, M1, CCLK, M0, CSI
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OEA = bmBIT1 | bmBIT2 | bmBIT4 | bmBIT5 | bmBIT7;
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OEA = bmBIT1 | bmBIT2 | bmBIT4 | bmBIT5 | bmBIT7;
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IOA = bmBIT7 | bmBIT4 | mode;
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IOA = bmBIT7 | bmBIT4 | mode;
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OEC |= bmBIT3; // out: RDWR_B
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OEC |= bmBIT3; // out: RDWR_B
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IOC &= ~bmBIT3;
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IOC &= ~bmBIT3;
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wait(10);
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wait(10);
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IOA = bmBIT1 | mode; // ready for configuration
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IOA = bmBIT1 | mode; // ready for configuration
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k=0;
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k=0;
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while (!IOC2 && k<65535)
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while (!IOC2 && k<65535)
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k++;
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k++;
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fpga_init_b = IOC2 ? 200 : 100;
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fpga_init_b = IOC2 ? 200 : 100;
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fpga_bytes = 0;
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fpga_bytes = 0;
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fpga_checksum = 0;
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fpga_checksum = 0;
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}
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}
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static void reset_fpga () {
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static void reset_fpga () {
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reset_fpga_int(bmBIT2);
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reset_fpga_int(bmBIT2);
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}
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}
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static void reset_fpga_flash () {
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static void reset_fpga_flash () {
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reset_fpga_int(bmBIT2 | bmBIT4 | bmBIT5 );
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reset_fpga_int(bmBIT2 | bmBIT4 | bmBIT5 );
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}
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}
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/* *********************************************************************
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/* *********************************************************************
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***** init_fpga_configuration ***************************************
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***** init_fpga_configuration ***************************************
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********************************************************************* */
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********************************************************************* */
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static void init_fpga_configuration () {
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static void init_fpga_configuration () {
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{
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{
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PRE_FPGA_RESET
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PRE_FPGA_RESET
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}
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}
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reset_fpga(); // reset FPGA
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reset_fpga(); // reset FPGA
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}
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}
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/* *********************************************************************
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/* *********************************************************************
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***** post_fpga_confog **********************************************
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***** post_fpga_confog **********************************************
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********************************************************************* */
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********************************************************************* */
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static void post_fpga_config () {
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static void post_fpga_config () {
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POST_FPGA_CONFIG
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POST_FPGA_CONFIG
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}
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}
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/* *********************************************************************
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/* *********************************************************************
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***** finish_fpga_configuration *************************************
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***** finish_fpga_configuration *************************************
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********************************************************************* */
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********************************************************************* */
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static void finish_fpga_configuration () {
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static void finish_fpga_configuration () {
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BYTE w;
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BYTE w;
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fpga_init_b += IOC2 ? 22 : 11;
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fpga_init_b += IOC2 ? 22 : 11;
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for ( w=0; w<64; w++ ) {
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for ( w=0; w<64; w++ ) {
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IOA4 = 1; IOA4 = 0;
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IOA4 = 1; IOA4 = 0;
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}
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}
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IOA7 = 1;
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IOA7 = 1;
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IOA4 = 1; IOA4 = 0;
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IOA4 = 1; IOA4 = 0;
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IOA4 = 1; IOA4 = 0;
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IOA4 = 1; IOA4 = 0;
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IOA4 = 1; IOA4 = 0;
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IOA4 = 1; IOA4 = 0;
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IOA4 = 1; IOA4 = 0;
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IOA4 = 1; IOA4 = 0;
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OEA = 0;
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OEA = 0;
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OEC &= ~bmBIT3;
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OEC &= ~bmBIT3;
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if ( IOA1 ) {
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if ( IOA1 ) {
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IOA1 = 1;
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IOA1 = 1;
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post_fpga_config();
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post_fpga_config();
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}
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}
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IOA1 = 1;
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IOA1 = 1;
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OEA |= bmBIT1;
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OEA |= bmBIT1;
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}
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}
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/* *********************************************************************
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/* *********************************************************************
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***** EP0 vendor request 0x30 ***************************************
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***** EP0 vendor request 0x30 ***************************************
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********************************************************************* */
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********************************************************************* */
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ADD_EP0_VENDOR_REQUEST((0x30,, // get FPGA state
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ADD_EP0_VENDOR_REQUEST((0x30,, // get FPGA state
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MEM_COPY1(fpga_checksum,EP0BUF+1,7);
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MEM_COPY1(fpga_checksum,EP0BUF+1,7);
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OEA &= ~bmBIT1;
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OEA &= ~bmBIT1;
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if ( IOA1 ) {
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if ( IOA1 ) {
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EP0BUF[0] = 0; // FPGA configured
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EP0BUF[0] = 0; // FPGA configured
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IOA1 = 1;
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IOA1 = 1;
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OEA |= bmBIT1;
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OEA |= bmBIT1;
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}
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}
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else {
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else {
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EP0BUF[0] = 1; // FPGA unconfigured
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EP0BUF[0] = 1; // FPGA unconfigured
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reset_fpga(); // prepare FPGA for configuration
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reset_fpga(); // prepare FPGA for configuration
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}
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}
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EP0BUF[8] = 1; // bit order for bitstream in Flash memory: swapped
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EP0BUF[8] = 1; // bit order for bitstream in Flash memory: swapped
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EP0BCH = 0;
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EP0BCH = 0;
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EP0BCL = 9;
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EP0BCL = 9;
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,,));;
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,,));;
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/* *********************************************************************
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/* *********************************************************************
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***** EP0 vendor command 0x31 ***************************************
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***** EP0 vendor command 0x31 ***************************************
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********************************************************************* */
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********************************************************************* */
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ADD_EP0_VENDOR_COMMAND((0x31,,init_fpga_configuration();,,));; // reset FPGA
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ADD_EP0_VENDOR_COMMAND((0x31,,init_fpga_configuration();,,));; // reset FPGA
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/* *********************************************************************
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/* *********************************************************************
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***** EP0 vendor command 0x32 ***************************************
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***** EP0 vendor command 0x32 ***************************************
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********************************************************************* */
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********************************************************************* */
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void fpga_send_ep0() { // send FPGA configuration data
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void fpga_send_ep0() { // send FPGA configuration data
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BYTE oOEB;
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BYTE oOEB;
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oOEB = OEB;
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oOEB = OEB;
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OEB = 255;
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OEB = 255;
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fpga_bytes += ep0_payload_transfer;
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fpga_bytes += ep0_payload_transfer;
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__asm
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__asm
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mov dptr,#_EP0BCL
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mov dptr,#_EP0BCL
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movx a,@dptr
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movx a,@dptr
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jz 010000$
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jz 010000$
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mov r2,a
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mov r2,a
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mov _AUTOPTRL1,#(_EP0BUF)
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mov _AUTOPTRL1,#(_EP0BUF)
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mov _AUTOPTRH1,#(_EP0BUF >> 8)
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mov _AUTOPTRH1,#(_EP0BUF >> 8)
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mov _AUTOPTRSETUP,#0x07
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mov _AUTOPTRSETUP,#0x07
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mov dptr,#_fpga_checksum
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mov dptr,#_fpga_checksum
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movx a,@dptr
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movx a,@dptr
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mov r1,a
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mov r1,a
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mov dptr,#_XAUTODAT1
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mov dptr,#_XAUTODAT1
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010001$:
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010001$:
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movx a,@dptr // 2
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movx a,@dptr // 2
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mov _IOB,a // 2
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mov _IOB,a // 2
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setb _IOA4 // 2
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setb _IOA4 // 2
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add a,r1 // 1
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add a,r1 // 1
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mov r1,a // 1
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mov r1,a // 1
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clr _IOA4 // 2
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clr _IOA4 // 2
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djnz r2, 010001$ // 4
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djnz r2, 010001$ // 4
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mov dptr,#_fpga_checksum
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mov dptr,#_fpga_checksum
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mov a,r1
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mov a,r1
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movx @dptr,a
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movx @dptr,a
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010000$:
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010000$:
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__endasm;
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__endasm;
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OEB = oOEB;
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OEB = oOEB;
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if ( EP0BCL<64 ) {
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if ( EP0BCL<64 ) {
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finish_fpga_configuration();
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finish_fpga_configuration();
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}
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}
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}
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}
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ADD_EP0_VENDOR_COMMAND((0x32,, // send FPGA configuration data
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ADD_EP0_VENDOR_COMMAND((0x32,, // send FPGA configuration data
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,,
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,,
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fpga_send_ep0();
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fpga_send_ep0();
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));;
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));;
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#ifdef[HS_FPGA_CONF_EP]
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#ifdef[HS_FPGA_CONF_EP]
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#ifeq[HS_FPGA_CONF_EP][2]
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#ifeq[HS_FPGA_CONF_EP][2]
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#elifeq[HS_FPGA_CONF_EP][4]
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#elifeq[HS_FPGA_CONF_EP][4]
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#elifeq[HS_FPGA_CONF_EP][6]
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#elifeq[HS_FPGA_CONF_EP][6]
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#elifneq[HS_FPGA_CONF_EP][8]
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#elifneq[HS_FPGA_CONF_EP][8]
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#error[`HS_FPGA_CONF_EP' is not defined correctly. Valid values are: `2', `4', `6', `8'.]
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#error[`HS_FPGA_CONF_EP' is not defined correctly. Valid values are: `2', `4', `6', `8'.]
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#endif
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#endif
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#define[@CAPABILITY_HS_FPGA;]
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#define[@CAPABILITY_HS_FPGA;]
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/* *********************************************************************
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/* *********************************************************************
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***** EP0 vendor request 0x33 ***************************************
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***** EP0 vendor request 0x33 ***************************************
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********************************************************************* */
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********************************************************************* */
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ADD_EP0_VENDOR_REQUEST((0x33,, // get high speed fpga configuration endpoint and interface
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ADD_EP0_VENDOR_REQUEST((0x33,, // get high speed fpga configuration endpoint and interface
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EP0BUF[0] = HS_FPGA_CONF_EP; // endpoint
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EP0BUF[0] = HS_FPGA_CONF_EP; // endpoint
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EP0BUF[1] = EPHS_FPGA_CONF_EP_INTERFACE; // interface
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EP0BUF[1] = EPHS_FPGA_CONF_EP_INTERFACE; // interface
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EP0BCH = 0;
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EP0BCH = 0;
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EP0BCL = 2;
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EP0BCL = 2;
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,,));;
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,,));;
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#ifeq[UFM_1_15X_DETECTION_ENABLED][1]
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#ifeq[UFM_1_15X_DETECTION_ENABLED][1]
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/* *********************************************************************
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/* *********************************************************************
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***** interrupt routine for EPn *************************************
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***** interrupt routine for EPn *************************************
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********************************************************************* */
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********************************************************************* */
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xdata WORD old_hsconf_intvec_h, old_hsconf_intvec_l;
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xdata WORD old_hsconf_intvec_h, old_hsconf_intvec_l;
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static void fpga_hs_send_isr () __interrupt {
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static void fpga_hs_send_isr () __interrupt {
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BYTE oOEB;
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BYTE oOEB;
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oOEB = OEB;
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oOEB = OEB;
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EUSB = 0; // block all USB interrupts
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EUSB = 0; // block all USB interrupts
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fpga_bytes += (EPHS_FPGA_CONF_EPBCH<<8) | EPHS_FPGA_CONF_EPBCL;
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fpga_bytes += (EPHS_FPGA_CONF_EPBCH<<8) | EPHS_FPGA_CONF_EPBCL;
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OEB = 255;
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OEB = 255;
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__asm
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__asm
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mov dptr,#_EPHS_FPGA_CONF_EPBCL
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mov dptr,#_EPHS_FPGA_CONF_EPBCL
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movx a,@dptr
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movx a,@dptr
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mov r2,a
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mov r2,a
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anl a,#7
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anl a,#7
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mov r3,a
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mov r3,a
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mov dptr,#_EPHS_FPGA_CONF_EPBCH
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mov dptr,#_EPHS_FPGA_CONF_EPBCH
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movx a,@dptr
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movx a,@dptr
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addc a,#0
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addc a,#0
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rrc a
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rrc a
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mov r1,a
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mov r1,a
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mov a,r2
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mov a,r2
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rrc a
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rrc a
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mov r2,a
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mov r2,a
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mov a,r1
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mov a,r1
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rrc a
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rrc a
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mov r1,a
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mov r1,a
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mov a,r2
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mov a,r2
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rrc a
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rrc a
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mov r2,a
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mov r2,a
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mov a,r1
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mov a,r1
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rrc a
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rrc a
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mov r1,a
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mov r1,a
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mov a,r2
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mov a,r2
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rrc a
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rrc a
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mov r2,a
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mov r2,a
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mov _AUTOPTRL1,#(_EPHS_FPGA_CONF_EPFIFOBUF)
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mov _AUTOPTRL1,#(_EPHS_FPGA_CONF_EPFIFOBUF)
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mov _AUTOPTRH1,#(_EPHS_FPGA_CONF_EPFIFOBUF >> 8)
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mov _AUTOPTRH1,#(_EPHS_FPGA_CONF_EPFIFOBUF >> 8)
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mov _AUTOPTRSETUP,#0x07
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mov _AUTOPTRSETUP,#0x07
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mov dptr,#_XAUTODAT1
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mov dptr,#_XAUTODAT1
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|
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mov a,r3
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mov a,r3
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jz 010011$
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jz 010011$
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010012$:
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010012$:
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movx a,@dptr // 2, 1
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movx a,@dptr // 2, 1
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mov _IOB,a // 2
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mov _IOB,a // 2
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setb _IOA4 // 2
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setb _IOA4 // 2
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clr _IOA4 // 2
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clr _IOA4 // 2
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djnz r3, 010012$ // 4
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djnz r3, 010012$ // 4
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|
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mov a,r2
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mov a,r2
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jz 010010$
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jz 010010$
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010011$:
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010011$:
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movx a,@dptr // 2, 1
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movx a,@dptr // 2, 1
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mov _IOB,a // 2
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mov _IOB,a // 2
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setb _IOA4 // 2
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setb _IOA4 // 2
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clr _IOA4 // 2
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clr _IOA4 // 2
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|
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movx a,@dptr // 2, 2
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movx a,@dptr // 2, 2
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mov _IOB,a // 2
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mov _IOB,a // 2
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setb _IOA4 // 2
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setb _IOA4 // 2
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clr _IOA4 // 2
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clr _IOA4 // 2
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|
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movx a,@dptr // 2, 3
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movx a,@dptr // 2, 3
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mov _IOB,a // 2
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mov _IOB,a // 2
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setb _IOA4 // 2
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setb _IOA4 // 2
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clr _IOA4 // 2
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clr _IOA4 // 2
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|
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movx a,@dptr // 2, 4
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movx a,@dptr // 2, 4
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mov _IOB,a // 2
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mov _IOB,a // 2
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setb _IOA4 // 2
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setb _IOA4 // 2
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clr _IOA4 // 2
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clr _IOA4 // 2
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|
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movx a,@dptr // 2, 5
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movx a,@dptr // 2, 5
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mov _IOB,a // 2
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mov _IOB,a // 2
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setb _IOA4 // 2
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setb _IOA4 // 2
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clr _IOA4 // 2
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clr _IOA4 // 2
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|
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movx a,@dptr // 2, 6
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movx a,@dptr // 2, 6
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mov _IOB,a // 2
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mov _IOB,a // 2
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setb _IOA4 // 2
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setb _IOA4 // 2
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clr _IOA4 // 2
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clr _IOA4 // 2
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|
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movx a,@dptr // 2, 7
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movx a,@dptr // 2, 7
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mov _IOB,a // 2
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mov _IOB,a // 2
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setb _IOA4 // 2
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setb _IOA4 // 2
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clr _IOA4 // 2
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clr _IOA4 // 2
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|
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movx a,@dptr // 2, 8
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movx a,@dptr // 2, 8
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mov _IOB,a // 2
|
mov _IOB,a // 2
|
setb _IOA4 // 2
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setb _IOA4 // 2
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clr _IOA4 // 2
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clr _IOA4 // 2
|
|
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djnz r2, 010011$ // 4
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djnz r2, 010011$ // 4
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|
|
010010$:
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010010$:
|
__endasm;
|
__endasm;
|
OEB = oOEB;
|
OEB = oOEB;
|
|
|
|
|
OUTPKTEND = 0x8HS_FPGA_CONF_EP; // skip package, (re)arm EP
|
OUTPKTEND = 0x8HS_FPGA_CONF_EP; // skip package, (re)arm EP
|
// EPHS_FPGA_CONF_EPBCL = 0x80; // skip package, (re)arm EP
|
// EPHS_FPGA_CONF_EPBCL = 0x80; // skip package, (re)arm EP
|
SYNCDELAY;
|
SYNCDELAY;
|
|
|
EXIF &= ~bmBIT4;
|
EXIF &= ~bmBIT4;
|
EPIRQ = 1 << ((HS_FPGA_CONF_EP >> 1)+3);
|
EPIRQ = 1 << ((HS_FPGA_CONF_EP >> 1)+3);
|
|
|
EUSB = 1;
|
EUSB = 1;
|
}
|
}
|
#endif
|
#endif
|
|
|
/* *********************************************************************
|
/* *********************************************************************
|
***** EP0 vendor command 0x34 ***************************************
|
***** EP0 vendor command 0x34 ***************************************
|
********************************************************************* */
|
********************************************************************* */
|
// FIFO write wave form
|
// FIFO write wave form
|
const char __xdata GPIF_WAVE_DATA_HSFPGA_24MHZ[32] =
|
const char __xdata GPIF_WAVE_DATA_HSFPGA_24MHZ[32] =
|
{
|
{
|
/* LenBr */ 0x01, 0x88, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
|
/* LenBr */ 0x01, 0x88, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
|
/* Opcode*/ 0x02, 0x07, 0x02, 0x02, 0x02, 0x02, 0x02, 0x00,
|
/* Opcode*/ 0x02, 0x07, 0x02, 0x02, 0x02, 0x02, 0x02, 0x00,
|
/* Output*/ 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, // CTL2 <-> 0x04
|
/* Output*/ 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, // CTL2 <-> 0x04
|
/* LFun */ 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
|
/* LFun */ 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
|
};
|
};
|
|
|
const char __xdata GPIF_WAVE_DATA_HSFPGA_12MHZ[32] =
|
const char __xdata GPIF_WAVE_DATA_HSFPGA_12MHZ[32] =
|
{
|
{
|
/* LenBr */ 0x02, 0x01, 0x90, 0x01, 0x01, 0x01, 0x01, 0x07,
|
/* LenBr */ 0x02, 0x01, 0x90, 0x01, 0x01, 0x01, 0x01, 0x07,
|
/* Opcode*/ 0x02, 0x02, 0x07, 0x02, 0x02, 0x02, 0x02, 0x00,
|
/* Opcode*/ 0x02, 0x02, 0x07, 0x02, 0x02, 0x02, 0x02, 0x00,
|
/* Output*/ 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, // CTL2 <-> 0x04
|
/* Output*/ 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, // CTL2 <-> 0x04
|
/* LFun */ 0x00, 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x3F,
|
/* LFun */ 0x00, 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x3F,
|
};
|
};
|
|
|
|
|
void init_cpld_fpga_configuration() {
|
void init_cpld_fpga_configuration() {
|
IFCONFIG = bmBIT7 | bmBIT6 | 2; // Internal source, 48MHz, GPIF
|
IFCONFIG = bmBIT7 | bmBIT6 | 2; // Internal source, 48MHz, GPIF
|
|
|
GPIFREADYCFG = 0;
|
GPIFREADYCFG = 0;
|
GPIFCTLCFG = 0x0;
|
GPIFCTLCFG = 0x0;
|
GPIFIDLECS = 0;
|
GPIFIDLECS = 0;
|
GPIFIDLECTL = 4;
|
GPIFIDLECTL = 4;
|
GPIFWFSELECT = 0x4E;
|
GPIFWFSELECT = 0x4E;
|
GPIFREADYSTAT = 0;
|
GPIFREADYSTAT = 0;
|
|
|
MEM_COPY1(GPIF_WAVE_DATA_HSFPGA_24MHZ,GPIF_WAVE3_DATA,32);
|
MEM_COPY1(GPIF_WAVE_DATA_HSFPGA_24MHZ,GPIF_WAVE3_DATA,32);
|
|
|
FLOWSTATE = 0;
|
FLOWSTATE = 0;
|
FLOWLOGIC = 0x10;
|
FLOWLOGIC = 0x10;
|
FLOWEQ0CTL = 0;
|
FLOWEQ0CTL = 0;
|
FLOWEQ1CTL = 0;
|
FLOWEQ1CTL = 0;
|
FLOWHOLDOFF = 0;
|
FLOWHOLDOFF = 0;
|
FLOWSTB = 0;
|
FLOWSTB = 0;
|
FLOWSTBEDGE = 0;
|
FLOWSTBEDGE = 0;
|
FLOWSTBHPERIOD = 0;
|
FLOWSTBHPERIOD = 0;
|
|
|
REVCTL = 0x1; // reset fifo
|
REVCTL = 0x1; // reset fifo
|
SYNCDELAY;
|
SYNCDELAY;
|
FIFORESET = 0x80;
|
FIFORESET = 0x80;
|
SYNCDELAY;
|
SYNCDELAY;
|
FIFORESET = HS_FPGA_CONF_EP;
|
FIFORESET = HS_FPGA_CONF_EP;
|
SYNCDELAY;
|
SYNCDELAY;
|
FIFORESET = 0x0;
|
FIFORESET = 0x0;
|
SYNCDELAY;
|
SYNCDELAY;
|
|
|
EPHS_FPGA_CONF_EPFIFOCFG = 0; // config fifo
|
EPHS_FPGA_CONF_EPFIFOCFG = 0; // config fifo
|
SYNCDELAY;
|
SYNCDELAY;
|
EPHS_FPGA_CONF_EPFIFOCFG = bmBIT4 | 0;
|
EPHS_FPGA_CONF_EPFIFOCFG = bmBIT4 | 0;
|
SYNCDELAY;
|
SYNCDELAY;
|
EPHS_FPGA_CONF_EPGPIFFLGSEL = 1;
|
EPHS_FPGA_CONF_EPGPIFFLGSEL = 1;
|
SYNCDELAY;
|
SYNCDELAY;
|
|
|
GPIFTCB3 = 1; // abort after at least 14*65536 transactions
|
GPIFTCB3 = 1; // abort after at least 14*65536 transactions
|
SYNCDELAY;
|
SYNCDELAY;
|
GPIFTCB2 = 0;
|
GPIFTCB2 = 0;
|
SYNCDELAY;
|
SYNCDELAY;
|
GPIFTCB1 = 0;
|
GPIFTCB1 = 0;
|
SYNCDELAY;
|
SYNCDELAY;
|
GPIFTCB0 = 0;
|
GPIFTCB0 = 0;
|
SYNCDELAY;
|
SYNCDELAY;
|
|
|
EPHS_FPGA_CONF_EPGPIFTRIG = 0xff; // arm fifos
|
EPHS_FPGA_CONF_EPGPIFTRIG = 0xff; // arm fifos
|
SYNCDELAY;
|
SYNCDELAY;
|
|
|
OEA &= ~bmBIT4; // disable CCLK output
|
OEA &= ~bmBIT4; // disable CCLK output
|
OEA |= bmBIT0; // enable GPIF mode of CPLD
|
OEA |= bmBIT0; // enable GPIF mode of CPLD
|
IOA0 = 0;
|
IOA0 = 0;
|
}
|
}
|
|
|
#ifeq[UFM_1_15X_DETECTION_ENABLED][1]
|
#ifeq[UFM_1_15X_DETECTION_ENABLED][1]
|
xdata WORD old_hsconf_intvec_h, old_hsconf_intvec_l;
|
xdata WORD old_hsconf_intvec_h, old_hsconf_intvec_l;
|
|
|
void init_epn_fpga_configuration() {
|
void init_epn_fpga_configuration() {
|
|
|
IFCONFIG = bmBIT7;
|
IFCONFIG = bmBIT7;
|
|
|
REVCTL = 0x03; // reset fifo
|
REVCTL = 0x03; // reset fifo
|
SYNCDELAY;
|
SYNCDELAY;
|
FIFORESET = 0x80;
|
FIFORESET = 0x80;
|
SYNCDELAY;
|
SYNCDELAY;
|
FIFORESET = HS_FPGA_CONF_EP;
|
FIFORESET = HS_FPGA_CONF_EP;
|
SYNCDELAY;
|
SYNCDELAY;
|
FIFORESET = 0x0;
|
FIFORESET = 0x0;
|
SYNCDELAY;
|
SYNCDELAY;
|
|
|
EPHS_FPGA_CONF_EPFIFOCFG = 0; // config fifo
|
EPHS_FPGA_CONF_EPFIFOCFG = 0; // config fifo
|
SYNCDELAY;
|
SYNCDELAY;
|
|
|
OUTPKTEND = 0x8HS_FPGA_CONF_EP; // skip package, (re)arm EP
|
OUTPKTEND = 0x8HS_FPGA_CONF_EP; // skip package, (re)arm EP
|
SYNCDELAY;
|
SYNCDELAY;
|
OUTPKTEND = 0x8HS_FPGA_CONF_EP; // skip package, (re)arm EP
|
OUTPKTEND = 0x8HS_FPGA_CONF_EP; // skip package, (re)arm EP
|
SYNCDELAY;
|
SYNCDELAY;
|
OUTPKTEND = 0x8HS_FPGA_CONF_EP; // skip package, (re)arm EP
|
OUTPKTEND = 0x8HS_FPGA_CONF_EP; // skip package, (re)arm EP
|
SYNCDELAY;
|
SYNCDELAY;
|
OUTPKTEND = 0x8HS_FPGA_CONF_EP; // skip package, (re)arm EP
|
OUTPKTEND = 0x8HS_FPGA_CONF_EP; // skip package, (re)arm EP
|
SYNCDELAY;
|
SYNCDELAY;
|
|
|
/* EPHS_FPGA_CONF_EPBCL = 0x80; // skip package, (re)arm EP
|
/* EPHS_FPGA_CONF_EPBCL = 0x80; // skip package, (re)arm EP
|
SYNCDELAY;
|
SYNCDELAY;
|
EPHS_FPGA_CONF_EPBCL = 0x80; // skip package, (re)arm EP
|
EPHS_FPGA_CONF_EPBCL = 0x80; // skip package, (re)arm EP
|
SYNCDELAY;
|
SYNCDELAY;
|
EPHS_FPGA_CONF_EPBCL = 0x80; // skip package, (re)arm EP
|
EPHS_FPGA_CONF_EPBCL = 0x80; // skip package, (re)arm EP
|
SYNCDELAY;
|
SYNCDELAY;
|
EPHS_FPGA_CONF_EPBCL = 0x80; // skip package, (re)arm EP
|
EPHS_FPGA_CONF_EPBCL = 0x80; // skip package, (re)arm EP
|
SYNCDELAY; */
|
SYNCDELAY; */
|
|
|
old_hsconf_intvec_l = INTVEC_EPHS_FPGA_CONF_EP.addrL;
|
old_hsconf_intvec_l = INTVEC_EPHS_FPGA_CONF_EP.addrL;
|
old_hsconf_intvec_h = INTVEC_EPHS_FPGA_CONF_EP.addrH;
|
old_hsconf_intvec_h = INTVEC_EPHS_FPGA_CONF_EP.addrH;
|
INTVEC_EPHS_FPGA_CONF_EP.addrH=((unsigned short)(&fpga_hs_send_isr)) >> 8;
|
INTVEC_EPHS_FPGA_CONF_EP.addrH=((unsigned short)(&fpga_hs_send_isr)) >> 8;
|
INTVEC_EPHS_FPGA_CONF_EP.addrL=(unsigned short)(&fpga_hs_send_isr);
|
INTVEC_EPHS_FPGA_CONF_EP.addrL=(unsigned short)(&fpga_hs_send_isr);
|
|
|
EXIF &= ~bmBIT4;
|
EXIF &= ~bmBIT4;
|
EPIRQ = 1 << ((HS_FPGA_CONF_EP >> 1)+3);
|
EPIRQ = 1 << ((HS_FPGA_CONF_EP >> 1)+3);
|
}
|
}
|
#endif
|
#endif
|
|
|
ADD_EP0_VENDOR_COMMAND((0x34,, // init fpga configuration
|
ADD_EP0_VENDOR_COMMAND((0x34,, // init fpga configuration
|
init_fpga_configuration();
|
init_fpga_configuration();
|
|
|
EPHS_FPGA_CONF_EPCS &= ~bmBIT0; // clear stall bit
|
EPHS_FPGA_CONF_EPCS &= ~bmBIT0; // clear stall bit
|
|
|
GPIFABORT = 0xFF; // abort pendig
|
GPIFABORT = 0xFF; // abort pendig
|
|
|
#ifeq[UFM_1_15X_DETECTION_ENABLED][1]
|
#ifeq[UFM_1_15X_DETECTION_ENABLED][1]
|
if ( is_ufm_1_15x )
|
if ( is_ufm_1_15x )
|
init_epn_fpga_configuration();
|
init_epn_fpga_configuration();
|
else
|
else
|
#endif
|
#endif
|
init_cpld_fpga_configuration();
|
init_cpld_fpga_configuration();
|
|
|
,,));;
|
,,));;
|
|
|
|
|
/* *********************************************************************
|
/* *********************************************************************
|
***** EP0 vendor command 0x35 ***************************************
|
***** EP0 vendor command 0x35 ***************************************
|
********************************************************************* */
|
********************************************************************* */
|
ADD_EP0_VENDOR_COMMAND((0x35,, // finish fpga configuration
|
ADD_EP0_VENDOR_COMMAND((0x35,, // finish fpga configuration
|
#ifeq[UFM_1_15X_DETECTION_ENABLED][1]
|
#ifeq[UFM_1_15X_DETECTION_ENABLED][1]
|
if ( is_ufm_1_15x ) {
|
if ( is_ufm_1_15x ) {
|
INTVEC_EPHS_FPGA_CONF_EP.addrL = old_hsconf_intvec_l;
|
INTVEC_EPHS_FPGA_CONF_EP.addrL = old_hsconf_intvec_l;
|
INTVEC_EPHS_FPGA_CONF_EP.addrH = old_hsconf_intvec_h;
|
INTVEC_EPHS_FPGA_CONF_EP.addrH = old_hsconf_intvec_h;
|
}
|
}
|
else
|
else
|
#endif
|
#endif
|
{
|
{
|
IOA0 = 1; // disable GPIF mode of CPLD
|
IOA0 = 1; // disable GPIF mode of CPLD
|
IOA4 = 1; // enable CCLK output
|
IOA4 = 1; // enable CCLK output
|
OEA |= bmBIT4;
|
OEA |= bmBIT4;
|
|
|
GPIFABORT = 0xFF;
|
GPIFABORT = 0xFF;
|
SYNCDELAY;
|
SYNCDELAY;
|
IFCONFIG &= 0xf0;
|
IFCONFIG &= 0xf0;
|
SYNCDELAY;
|
SYNCDELAY;
|
|
|
}
|
}
|
finish_fpga_configuration();
|
finish_fpga_configuration();
|
,,));;
|
,,));;
|
|
|
#endif // HS_FPGA_CONF_EP
|
#endif // HS_FPGA_CONF_EP
|
|
|
|
|
|
|
#ifeq[FLASH_BITSTREAM_ENABLED][1]
|
#ifeq[FLASH_BITSTREAM_ENABLED][1]
|
#ifeq[FLASH_ENABLED][1]
|
#ifeq[FLASH_ENABLED][1]
|
|
|
/* *********************************************************************
|
/* *********************************************************************
|
***** fpga_send_bitstream_from_flash ********************************
|
***** fpga_send_bitstream_from_flash ********************************
|
********************************************************************* */
|
********************************************************************* */
|
void fpga_send_bitstream_from_flash (WORD size) {
|
void fpga_send_bitstream_from_flash (WORD size) {
|
size; // this avoids stupid warnings
|
size; // this avoids stupid warnings
|
__asm
|
__asm
|
push _OEB
|
push _OEB
|
|
|
mov r5,dpl // = size
|
mov r5,dpl // = size
|
mov r6,dph
|
mov r6,dph
|
|
|
// fpga_bytes+=size
|
// fpga_bytes+=size
|
mov dptr,#_fpga_bytes
|
mov dptr,#_fpga_bytes
|
movx a,@dptr
|
movx a,@dptr
|
mov r1,a
|
mov r1,a
|
inc dptr
|
inc dptr
|
movx a,@dptr
|
movx a,@dptr
|
mov r2,a
|
mov r2,a
|
inc dptr
|
inc dptr
|
movx a,@dptr
|
movx a,@dptr
|
mov r3,a
|
mov r3,a
|
inc dptr
|
inc dptr
|
movx a,@dptr
|
movx a,@dptr
|
mov r4,a
|
mov r4,a
|
|
|
mov dptr,#_fpga_bytes
|
mov dptr,#_fpga_bytes
|
mov a,r5
|
mov a,r5
|
add a,r1
|
add a,r1
|
movx @dptr,a
|
movx @dptr,a
|
mov a,r6
|
mov a,r6
|
addc a,r2
|
addc a,r2
|
inc dptr
|
inc dptr
|
movx @dptr,a
|
movx @dptr,a
|
mov a,#0
|
mov a,#0
|
addc a,r3
|
addc a,r3
|
inc dptr
|
inc dptr
|
movx @dptr,a
|
movx @dptr,a
|
mov a,#0
|
mov a,#0
|
addc a,r4
|
addc a,r4
|
inc dptr
|
inc dptr
|
movx @dptr,a
|
movx @dptr,a
|
|
|
// size == 512
|
// size == 512
|
cjne r5,#0,010004$
|
cjne r5,#0,010004$
|
cjne r6,#2,010004$
|
cjne r6,#2,010004$
|
// sjmp 010004$
|
// sjmp 010004$
|
|
|
mov _OEB, #0
|
mov _OEB, #0
|
anl _OEA, #(~bmBIT4)
|
anl _OEA, #(~bmBIT4)
|
setb _IOC6
|
setb _IOC6
|
anl _OEC, #(~bmBIT6)
|
anl _OEC, #(~bmBIT6)
|
orl _OEA, #(bmBIT3)
|
orl _OEA, #(bmBIT3)
|
clr _IOA3
|
clr _IOA3
|
setb _IOA3
|
setb _IOA3
|
anl _OEA, #(~bmBIT3)
|
anl _OEA, #(~bmBIT3)
|
|
|
mov r2, #3 // wait > 2 clocks
|
mov r2, #3 // wait > 2 clocks
|
010008$:
|
010008$:
|
mov r1, #227
|
mov r1, #227
|
010009$:
|
010009$:
|
djnz r1, 010009$
|
djnz r1, 010009$
|
djnz r2, 010008$
|
djnz r2, 010008$
|
|
|
setb _IOA4
|
setb _IOA4
|
orl _OEA, #(bmBIT4)
|
orl _OEA, #(bmBIT4)
|
orl _OEC, #(bmBIT6)
|
orl _OEC, #(bmBIT6)
|
clr _IOC6
|
clr _IOC6
|
pop _OEB
|
pop _OEB
|
ret
|
ret
|
|
|
// size != 512
|
// size != 512
|
010004$:
|
010004$:
|
mov _OEB,#1
|
mov _OEB,#1
|
010003$:
|
010003$:
|
cjne r5,#0x00,010002$ // 4
|
cjne r5,#0x00,010002$ // 4
|
cjne r6,#0x00,010002$
|
cjne r6,#0x00,010002$
|
pop _OEB
|
pop _OEB
|
ret
|
ret
|
010002$: // approx 105 cycles per byte
|
010002$: // approx 105 cycles per byte
|
mov C, _IOC4 // 2
|
mov C, _IOC4 // 2
|
mov _IOB0, C // 2
|
mov _IOB0, C // 2
|
clr _IOA4 // 2
|
clr _IOA4 // 2
|
setb _IOA4 // 2
|
setb _IOA4 // 2
|
setb _IOC6 // 2
|
setb _IOC6 // 2
|
clr _IOC6 // 2
|
clr _IOC6 // 2
|
|
|
mov C, _IOC4
|
mov C, _IOC4
|
mov _IOB0, C
|
mov _IOB0, C
|
clr _IOA4
|
clr _IOA4
|
setb _IOA4
|
setb _IOA4
|
setb _IOC6
|
setb _IOC6
|
clr _IOC6
|
clr _IOC6
|
|
|
mov C, _IOC4
|
mov C, _IOC4
|
mov _IOB0, C
|
mov _IOB0, C
|
clr _IOA4
|
clr _IOA4
|
setb _IOA4
|
setb _IOA4
|
setb _IOC6
|
setb _IOC6
|
clr _IOC6
|
clr _IOC6
|
|
|
mov C, _IOC4
|
mov C, _IOC4
|
mov _IOB0, C
|
mov _IOB0, C
|
clr _IOA4
|
clr _IOA4
|
setb _IOA4
|
setb _IOA4
|
setb _IOC6
|
setb _IOC6
|
clr _IOC6
|
clr _IOC6
|
|
|
mov C, _IOC4
|
mov C, _IOC4
|
mov _IOB0, C
|
mov _IOB0, C
|
clr _IOA4
|
clr _IOA4
|
setb _IOA4
|
setb _IOA4
|
setb _IOC6
|
setb _IOC6
|
clr _IOC6
|
clr _IOC6
|
|
|
mov C, _IOC4
|
mov C, _IOC4
|
mov _IOB0, C
|
mov _IOB0, C
|
clr _IOA4
|
clr _IOA4
|
setb _IOA4
|
setb _IOA4
|
setb _IOC6
|
setb _IOC6
|
clr _IOC6
|
clr _IOC6
|
|
|
mov C, _IOC4
|
mov C, _IOC4
|
mov _IOB0, C
|
mov _IOB0, C
|
clr _IOA4
|
clr _IOA4
|
setb _IOA4
|
setb _IOA4
|
setb _IOC6
|
setb _IOC6
|
clr _IOC6
|
clr _IOC6
|
|
|
mov C, _IOC4
|
mov C, _IOC4
|
mov _IOB0, C
|
mov _IOB0, C
|
clr _IOA4
|
clr _IOA4
|
setb _IOA4
|
setb _IOA4
|
setb _IOC6
|
setb _IOC6
|
clr _IOC6
|
clr _IOC6
|
|
|
dec r5 // 1
|
dec r5 // 1
|
cjne r5,#0xff,010003$ // 4
|
cjne r5,#0xff,010003$ // 4
|
dec r6
|
dec r6
|
sjmp 010003$
|
sjmp 010003$
|
__endasm;
|
__endasm;
|
}
|
}
|
|
|
#include[ztex-fpga-flash1.h]
|
#include[ztex-fpga-flash1.h]
|
|
|
#else
|
#else
|
#warning[Flash interface is not enabled but required for FPGA configuration using a bitstream from Flash meomory]
|
#warning[Flash interface is not enabled but required for FPGA configuration using a bitstream from Flash meomory]
|
#define[FLASH_BITSTREAM_ENABLED][0]
|
#define[FLASH_BITSTREAM_ENABLED][0]
|
#endif
|
#endif
|
#endif
|
#endif
|
|
|
#endif /*ZTEX_FPGA_H*/
|
#endif /*ZTEX_FPGA_H*/
|
|
|
