/*!
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/*!
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ZTEX Firmware Kit for EZ-USB FX2 Microcontrollers
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ZTEX Firmware Kit for EZ-USB FX2 Microcontrollers
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Copyright (C) 2009-2011 ZTEX GmbH.
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Copyright (C) 2009-2014 ZTEX GmbH.
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http://www.ztex.de
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http://www.ztex.de
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License version 3 as
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it under the terms of the GNU General Public License version 3 as
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published by the Free Software Foundation.
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published by the Free Software Foundation.
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This program is distributed in the hope that it will be useful, but
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, see http://www.gnu.org/licenses/.
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along with this program; if not, see http://www.gnu.org/licenses/.
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!*/
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!*/
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/*
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/*
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FPGA support for ZTEX USB FPGA Modules 1.15y
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FPGA support for ZTEX USB FPGA Modules 1.15y
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*/
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*/
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#ifndef[ZTEX_FPGA_H]
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#ifndef[ZTEX_FPGA_H]
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#define[ZTEX_FPGA_H]
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#define[ZTEX_FPGA_H]
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#define[@CAPABILITY_FPGA;]
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#define[@CAPABILITY_FPGA;]
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#define[@CAPABILITY_MULTI_FPGA;]
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#define[@CAPABILITY_MULTI_FPGA;]
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__xdata BYTE fpga_checksum; // checksum
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__xdata BYTE fpga_checksum; // checksum
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__xdata DWORD fpga_bytes; // transferred bytes
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__xdata DWORD fpga_bytes; // transferred bytes
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__xdata BYTE fpga_init_b; // init_b state (should be 222 after configuration)
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__xdata BYTE fpga_init_b; // init_b state (should be 222 after configuration)
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__xdata BYTE select_num;
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__xdata BYTE select_num;
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__xdata BYTE prev_select_num;
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__xdata BYTE prev_select_num;
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__xdata BYTE select_mask;
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__xdata BYTE select_mask;
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__xdata BYTE config_mask_h;
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__xdata BYTE config_mask_h;
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__xdata BYTE config_mask_l;
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__xdata BYTE config_mask_l;
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/* *********************************************************************
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/* *********************************************************************
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***** init_fpga *****************************************************
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***** init_fpga *****************************************************
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********************************************************************* */
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********************************************************************* */
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void init_fpga () {
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void init_fpga () {
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IOE = 0x1f;
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IOE = 0x1f;
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OEE = 0xff;
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OEE = 0xff;
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prev_select_num = 0;
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prev_select_num = 0;
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select_num = 0;
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select_num = 0;
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select_mask = 0x10;
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select_mask = 0x10;
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config_mask_h = 0x10;
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config_mask_h = 0x10;
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config_mask_l = 0x01;
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config_mask_l = 0x01;
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}
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}
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/* *********************************************************************
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/* *********************************************************************
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***** reset_fpga ****************************************************
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***** reset_fpga ****************************************************
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********************************************************************* */
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********************************************************************* */
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static void reset_fpga () { // reset FPGA
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static void reset_fpga () { // reset FPGA
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WORD k;
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WORD k;
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IFCONFIG = bmBIT7;
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IFCONFIG = bmBIT7;
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SYNCDELAY;
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SYNCDELAY;
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PORTACFG = 0;
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PORTACFG = 0;
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PORTCCFG = 0;
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PORTCCFG = 0;
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IOC2 = 1; // out: INIT_B
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IOC2 = 1; // out: INIT_B
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OEC |= bmBIT2;
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OEC |= bmBIT2;
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OEA &= ~bmBIT6; // in: CSO
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OEA &= ~bmBIT6; // in: CSO
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OEC &= ~bmBIT1; // in: DOUT
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OEC &= ~bmBIT1; // in: DOUT
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IOC3 = 0;
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IOC3 = 0;
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OEC |= bmBIT3; // out: RDWR_B
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OEC |= bmBIT3; // out: RDWR_B
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// out: CCLK, M1, GPIF, M0, CSI
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// out: CCLK, M1, GPIF, M0, CSI
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OEA |= bmBIT1 | bmBIT2 | bmBIT3 | bmBIT5 | bmBIT7;
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OEA |= bmBIT1 | bmBIT2 | bmBIT3 | bmBIT5 | bmBIT7;
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IOA5 = 0;
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IOA5 = 0;
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IOA |= bmBIT1 | bmBIT2 | bmBIT3 | bmBIT7;
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IOA |= bmBIT1 | bmBIT2 | bmBIT3 | bmBIT7;
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IOE = config_mask_h | ((~config_mask_l) & 0x0f);
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IOE = config_mask_h | ((~config_mask_l) & 0x0f);
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OEE = 0xff;
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OEE = 0xff;
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wait(1);
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wait(1);
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IOA7 = 0;
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IOA7 = 0;
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IOA1 = 0;
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IOA1 = 0;
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IOE = config_mask_h | 0x0f;
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IOE = config_mask_h | 0x0f;
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k=0;
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k=0;
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OEC &= ~bmBIT2; // in: INIT_B
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OEC &= ~bmBIT2; // in: INIT_B
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while ( (!IOC2) && (k<65535) ) {
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while ( (!IOC2) && (k<65535) ) {
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k++;
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k++;
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}
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}
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fpga_init_b = IOC2 ? 200 : 100;
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fpga_init_b = IOC2 ? 200 : 100;
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fpga_bytes = 0;
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fpga_bytes = 0;
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fpga_checksum = 0;
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fpga_checksum = 0;
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}
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}
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/* *********************************************************************
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/* *********************************************************************
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***** init_fpga_configuration ***************************************
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***** init_fpga_configuration ***************************************
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********************************************************************* */
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********************************************************************* */
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static void init_fpga_configuration () {
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static void init_fpga_configuration () {
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{
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{
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PRE_FPGA_RESET
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PRE_FPGA_RESET
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}
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}
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reset_fpga(); // reset FPGA
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reset_fpga(); // reset FPGA
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}
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}
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/* *********************************************************************
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/* *********************************************************************
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***** post_fpga_confog **********************************************
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***** post_fpga_confog **********************************************
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********************************************************************* */
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********************************************************************* */
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static void post_fpga_config () {
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static void post_fpga_config () {
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POST_FPGA_CONFIG
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POST_FPGA_CONFIG
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}
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}
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/* *********************************************************************
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/* *********************************************************************
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***** finish_fpga_configuration *************************************
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***** finish_fpga_configuration *************************************
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********************************************************************* */
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********************************************************************* */
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static void finish_fpga_configuration () {
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static void finish_fpga_configuration () {
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BYTE b;
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BYTE b;
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fpga_init_b += 22;
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fpga_init_b += 22;
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for ( b=0; b<255; b++ ) {
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for ( b=0; b<255; b++ ) {
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IOA1 = 1; IOA1 = 0;
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IOA1 = 1; IOA1 = 0;
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}
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}
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IOA7 = 1;
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IOA7 = 1;
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IOA4 = 1; IOA4 = 0;
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IOA4 = 1; IOA4 = 0;
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IOA4 = 1; IOA4 = 0;
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IOA4 = 1; IOA4 = 0;
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IOA4 = 1; IOA4 = 0;
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IOA4 = 1; IOA4 = 0;
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IOA4 = 1; IOA4 = 0;
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IOA4 = 1; IOA4 = 0;
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OEA &= ~(bmBIT1 | bmBIT2 | bmBIT3 | bmBIT7);
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OEA &= ~(bmBIT1 | bmBIT2 | bmBIT3 | bmBIT7);
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OEC &= ~bmBIT3;
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OEC &= ~bmBIT3;
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OEE = 0xf0;
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OEE = 0xf0;
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if ( (IOE & config_mask_l) == config_mask_l ) {
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if ( (IOE & config_mask_l) == config_mask_l ) {
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post_fpga_config();
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post_fpga_config();
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}
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}
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IOE = select_mask | 0x0f;
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IOE = select_mask | 0x0f;
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OEE = 0xff;
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OEE = 0xff;
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}
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}
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/* *********************************************************************
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/* *********************************************************************
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***** EP0 vendor request 0x30 ***************************************
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***** EP0 vendor request 0x30 ***************************************
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********************************************************************* */
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********************************************************************* */
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ADD_EP0_VENDOR_REQUEST((0x30,, // get FPGA state
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ADD_EP0_VENDOR_REQUEST((0x30,, // get FPGA state
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MEM_COPY1(fpga_checksum,EP0BUF+1,6);
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MEM_COPY1(fpga_checksum,EP0BUF+1,6);
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OEE = 0xf0;
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OEE = 0xf0;
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if ( (IOE & config_mask_l) == config_mask_l ) {
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if ( (IOE & config_mask_l) == config_mask_l ) {
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EP0BUF[0] = 0; // FPGA configured
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EP0BUF[0] = 0; // FPGA configured
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IOE = select_mask | 0x0f;
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IOE = select_mask | 0x0f;
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OEE = 0xff;
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OEE = 0xff;
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}
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}
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else {
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else {
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EP0BUF[0] = 1; // FPGA unconfigured
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EP0BUF[0] = 1; // FPGA unconfigured
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reset_fpga(); // prepare FPGA for configuration
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reset_fpga(); // prepare FPGA for configuration
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}
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}
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EP0BUF[7] = 0; // not used
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EP0BUF[7] = 0; // not used
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EP0BUF[8] = 0; // not used
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EP0BUF[8] = 0; // not used
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EP0BCH = 0;
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EP0BCH = 0;
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EP0BCL = 9;
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EP0BCL = 9;
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,,));;
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,,));;
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/* *********************************************************************
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/* *********************************************************************
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***** EP0 vendor command 0x31 ***************************************
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***** EP0 vendor command 0x31 ***************************************
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********************************************************************* */
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********************************************************************* */
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ADD_EP0_VENDOR_COMMAND((0x31,,init_fpga_configuration();,,));; // reset FPGA
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ADD_EP0_VENDOR_COMMAND((0x31,,init_fpga_configuration();,,));; // reset FPGA
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/* *********************************************************************
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/* *********************************************************************
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***** EP0 vendor command 0x32 ***************************************
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***** EP0 vendor command 0x32 ***************************************
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********************************************************************* */
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********************************************************************* */
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void fpga_send_ep0() { // send FPGA configuration data
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void fpga_send_ep0() { // send FPGA configuration data
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BYTE oOEB;
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BYTE oOEB;
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oOEB = OEB;
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oOEB = OEB;
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OEB = 255;
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OEB = 255;
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fpga_bytes += ep0_payload_transfer;
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fpga_bytes += ep0_payload_transfer;
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__asm
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__asm
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mov dptr,#_EP0BCL
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mov dptr,#_EP0BCL
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movx a,@dptr
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movx a,@dptr
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jz 010000$
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jz 010000$
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mov r2,a
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mov r2,a
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mov _AUTOPTRL1,#(_EP0BUF)
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mov _AUTOPTRL1,#(_EP0BUF)
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mov _AUTOPTRH1,#(_EP0BUF >> 8)
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mov _AUTOPTRH1,#(_EP0BUF >> 8)
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mov _AUTOPTRSETUP,#0x07
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mov _AUTOPTRSETUP,#0x07
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mov dptr,#_fpga_checksum
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mov dptr,#_fpga_checksum
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movx a,@dptr
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movx a,@dptr
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mov r1,a
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mov r1,a
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mov dptr,#_XAUTODAT1
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mov dptr,#_XAUTODAT1
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010001$:
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010001$:
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movx a,@dptr // 2
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movx a,@dptr // 2
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mov _IOB,a // 2
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mov _IOB,a // 2
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setb _IOA1 // 2
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setb _IOA1 // 2
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add a,r1 // 1
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add a,r1 // 1
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mov r1,a // 1
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mov r1,a // 1
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clr _IOA1 // 2
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clr _IOA1 // 2
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djnz r2, 010001$ // 4
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djnz r2, 010001$ // 4
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mov dptr,#_fpga_checksum
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mov dptr,#_fpga_checksum
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mov a,r1
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mov a,r1
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movx @dptr,a
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movx @dptr,a
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010000$:
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010000$:
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__endasm;
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__endasm;
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OEB = oOEB;
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OEB = oOEB;
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if ( EP0BCL<64 ) {
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if ( EP0BCL<64 ) {
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finish_fpga_configuration();
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finish_fpga_configuration();
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}
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}
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}
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}
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ADD_EP0_VENDOR_COMMAND((0x32,, // send FPGA configuration data
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ADD_EP0_VENDOR_COMMAND((0x32,, // send FPGA configuration data
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,,
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,,
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fpga_send_ep0();
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fpga_send_ep0();
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));;
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));;
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#ifdef[HS_FPGA_CONF_EP]
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#ifdef[HS_FPGA_CONF_EP]
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#ifeq[HS_FPGA_CONF_EP][2]
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#ifeq[HS_FPGA_CONF_EP][2]
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#elifeq[HS_FPGA_CONF_EP][4]
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#elifeq[HS_FPGA_CONF_EP][4]
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#elifeq[HS_FPGA_CONF_EP][6]
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#elifeq[HS_FPGA_CONF_EP][6]
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#elifneq[HS_FPGA_CONF_EP][8]
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#elifneq[HS_FPGA_CONF_EP][8]
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#error[`HS_FPGA_CONF_EP' is not defined correctly. Valid values are: `2', `4', `6', `8'.]
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#error[`HS_FPGA_CONF_EP' is not defined correctly. Valid values are: `2', `4', `6', `8'.]
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#endif
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#endif
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#define[@CAPABILITY_HS_FPGA;]
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#define[@CAPABILITY_HS_FPGA;]
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/* *********************************************************************
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/* *********************************************************************
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***** EP0 vendor request 0x33 ***************************************
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***** EP0 vendor request 0x33 ***************************************
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********************************************************************* */
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********************************************************************* */
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ADD_EP0_VENDOR_REQUEST((0x33,, // get high speed fpga configuration endpoint and interface
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ADD_EP0_VENDOR_REQUEST((0x33,, // get high speed fpga configuration endpoint and interface
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EP0BUF[0] = HS_FPGA_CONF_EP; // endpoint
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EP0BUF[0] = HS_FPGA_CONF_EP; // endpoint
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EP0BUF[1] = EPHS_FPGA_CONF_EP_INTERFACE; // interface
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EP0BUF[1] = EPHS_FPGA_CONF_EP_INTERFACE; // interface
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EP0BCH = 0;
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EP0BCH = 0;
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EP0BCL = 2;
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EP0BCL = 2;
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,,));;
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,,));;
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/* *********************************************************************
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/* *********************************************************************
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***** EP0 vendor command 0x34 ***************************************
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***** EP0 vendor command 0x34 ***************************************
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********************************************************************* */
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********************************************************************* */
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// FIFO write wave form
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// FIFO write wave form
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const char __xdata GPIF_WAVE_DATA_HSFPGA_24MHZ[32] =
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const char __xdata GPIF_WAVE_DATA_HSFPGA_24MHZ[32] =
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{
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{
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/* LenBr */ 0x01, 0x88, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
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/* LenBr */ 0x01, 0x88, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
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/* Opcode*/ 0x02, 0x07, 0x02, 0x02, 0x02, 0x02, 0x02, 0x00,
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/* Opcode*/ 0x02, 0x07, 0x02, 0x02, 0x02, 0x02, 0x02, 0x00,
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/* Output*/ 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
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/* Output*/ 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
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/* LFun */ 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
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/* LFun */ 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
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};
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};
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const char __xdata GPIF_WAVE_DATA_HSFPGA_12MHZ[32] =
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const char __xdata GPIF_WAVE_DATA_HSFPGA_12MHZ[32] =
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{
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{
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/* LenBr */ 0x02, 0x01, 0x90, 0x01, 0x01, 0x01, 0x01, 0x07,
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/* LenBr */ 0x02, 0x01, 0x90, 0x01, 0x01, 0x01, 0x01, 0x07,
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/* Opcode*/ 0x02, 0x02, 0x07, 0x02, 0x02, 0x02, 0x02, 0x00,
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/* Opcode*/ 0x02, 0x02, 0x07, 0x02, 0x02, 0x02, 0x02, 0x00,
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/* Output*/ 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
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/* Output*/ 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
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/* LFun */ 0x00, 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x3F,
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/* LFun */ 0x00, 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x3F,
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};
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};
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|
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void init_cpld_fpga_configuration() {
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void init_cpld_fpga_configuration() {
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IFCONFIG = bmBIT7 | bmBIT6 | 2; // Internal source, 48MHz, GPIF
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IFCONFIG = bmBIT7 | bmBIT6 | 2; // Internal source, 48MHz, GPIF
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// IFCONFIG = bmBIT7 | 2; // Internal source, 30MHz, GPIF
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// IFCONFIG = bmBIT7 | 2; // Internal source, 30MHz, GPIF
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|
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GPIFREADYCFG = 0x0;
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GPIFREADYCFG = 0x0;
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GPIFCTLCFG = 0;
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GPIFCTLCFG = 0;
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GPIFIDLECS = 0;
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GPIFIDLECS = 0;
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GPIFIDLECTL = 0x20;
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GPIFIDLECTL = 0x20;
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GPIFWFSELECT = 0x4E;
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GPIFWFSELECT = 0x4E;
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GPIFREADYSTAT = 0;
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GPIFREADYSTAT = 0;
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|
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MEM_COPY1(GPIF_WAVE_DATA_HSFPGA_24MHZ,GPIF_WAVE3_DATA,32);
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MEM_COPY1(GPIF_WAVE_DATA_HSFPGA_24MHZ,GPIF_WAVE3_DATA,32);
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|
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FLOWSTATE = 0;
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FLOWSTATE = 0;
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FLOWLOGIC = 0x10;
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FLOWLOGIC = 0x10;
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FLOWEQ0CTL = 0;
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FLOWEQ0CTL = 0;
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FLOWEQ1CTL = 0;
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FLOWEQ1CTL = 0;
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FLOWHOLDOFF = 0;
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FLOWHOLDOFF = 0;
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FLOWSTB = 0;
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FLOWSTB = 0;
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FLOWSTBEDGE = 0;
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FLOWSTBEDGE = 0;
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FLOWSTBHPERIOD = 0;
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FLOWSTBHPERIOD = 0;
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|
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REVCTL = 0x1; // reset fifo
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REVCTL = 0x1; // reset fifo
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SYNCDELAY;
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SYNCDELAY;
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FIFORESET = 0x80;
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FIFORESET = 0x80;
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SYNCDELAY;
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SYNCDELAY;
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FIFORESET = HS_FPGA_CONF_EP;
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FIFORESET = HS_FPGA_CONF_EP;
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SYNCDELAY;
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SYNCDELAY;
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FIFORESET = 0x0;
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FIFORESET = 0x0;
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SYNCDELAY;
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SYNCDELAY;
|
|
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EPHS_FPGA_CONF_EPFIFOCFG = 0; // config fifo
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EPHS_FPGA_CONF_EPFIFOCFG = 0; // config fifo
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SYNCDELAY;
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SYNCDELAY;
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EPHS_FPGA_CONF_EPFIFOCFG = bmBIT4;
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EPHS_FPGA_CONF_EPFIFOCFG = bmBIT4;
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SYNCDELAY;
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SYNCDELAY;
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EPHS_FPGA_CONF_EPGPIFFLGSEL = 1;
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EPHS_FPGA_CONF_EPGPIFFLGSEL = 1;
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SYNCDELAY;
|
SYNCDELAY;
|
|
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GPIFTCB3 = 1; // abort after at least 14*65536 transactions
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GPIFTCB3 = 1; // abort after at least 14*65536 transactions
|
SYNCDELAY;
|
SYNCDELAY;
|
GPIFTCB2 = 0;
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GPIFTCB2 = 0;
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SYNCDELAY;
|
SYNCDELAY;
|
GPIFTCB1 = 0;
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GPIFTCB1 = 0;
|
SYNCDELAY;
|
SYNCDELAY;
|
GPIFTCB0 = 0;
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GPIFTCB0 = 0;
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SYNCDELAY;
|
SYNCDELAY;
|
|
|
EPHS_FPGA_CONF_EPGPIFTRIG = 0xff; // arm fifos
|
EPHS_FPGA_CONF_EPGPIFTRIG = 0xff; // arm fifos
|
SYNCDELAY;
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SYNCDELAY;
|
|
|
IOA3 = 0;
|
IOA3 = 0;
|
}
|
}
|
|
|
|
|
ADD_EP0_VENDOR_COMMAND((0x34,, // init fpga configuration
|
ADD_EP0_VENDOR_COMMAND((0x34,, // init fpga configuration
|
init_fpga_configuration();
|
init_fpga_configuration();
|
|
|
EPHS_FPGA_CONF_EPCS &= ~bmBIT0; // clear stall bit
|
EPHS_FPGA_CONF_EPCS &= ~bmBIT0; // clear stall bit
|
|
|
GPIFABORT = 0xFF; // abort pendig
|
GPIFABORT = 0xFF; // abort pendig
|
|
|
init_cpld_fpga_configuration();
|
init_cpld_fpga_configuration();
|
,,));;
|
,,));;
|
|
|
|
|
/* *********************************************************************
|
/* *********************************************************************
|
***** EP0 vendor command 0x35 ***************************************
|
***** EP0 vendor command 0x35 ***************************************
|
********************************************************************* */
|
********************************************************************* */
|
ADD_EP0_VENDOR_COMMAND((0x35,, // finish fpga configuration
|
ADD_EP0_VENDOR_COMMAND((0x35,, // finish fpga configuration
|
IOA3 = 1; // disable GPIF mode of CPLD
|
IOA3 = 1; // disable GPIF mode of CPLD
|
|
|
GPIFABORT = 0xFF;
|
GPIFABORT = 0xFF;
|
SYNCDELAY;
|
SYNCDELAY;
|
IFCONFIG &= 0xf0;
|
IFCONFIG &= 0xf0;
|
SYNCDELAY;
|
SYNCDELAY;
|
|
|
finish_fpga_configuration();
|
finish_fpga_configuration();
|
,,));;
|
,,));;
|
|
|
#endif // HS_FPGA_CONF_EP
|
#endif // HS_FPGA_CONF_EP
|
|
|
|
|
/* *********************************************************************
|
/* *********************************************************************
|
***** select_fpga ***************************************************
|
***** select_fpga ***************************************************
|
********************************************************************* */
|
********************************************************************* */
|
void select_fpga ( BYTE fn )
|
void select_fpga ( BYTE fn )
|
{
|
{
|
prev_select_num = select_num;
|
prev_select_num = select_num;
|
select_num = fn & 3;
|
select_num = fn & 3;
|
select_mask = 0x10 << fn;
|
select_mask = 0x10 << fn;
|
config_mask_h = select_mask;
|
config_mask_h = select_mask;
|
|
|
IOE = 0x0f;
|
IOE = 0x0f;
|
{
|
{
|
PRE_FPGA_SELECT
|
PRE_FPGA_SELECT
|
}
|
}
|
IOE = select_mask | 0x0f;
|
IOE = select_mask | 0x0f;
|
}
|
}
|
|
|
|
|
/* *********************************************************************
|
/* *********************************************************************
|
***** EP0 vendor request 0x50 ***************************************
|
***** EP0 vendor request 0x50 ***************************************
|
********************************************************************* */
|
********************************************************************* */
|
ADD_EP0_VENDOR_REQUEST((0x50,, // Return multi-FPGA information
|
ADD_EP0_VENDOR_REQUEST((0x50,, // Return multi-FPGA information
|
EP0BUF[0] = 3; // 1 FPGA's
|
EP0BUF[0] = 3; // 1 FPGA's
|
EP0BUF[1] = select_num; // select methods: any combination
|
EP0BUF[1] = select_num; // select methods: any combination
|
EP0BUF[2] = 0; // no parallel configuration support
|
EP0BUF[2] = 0; // no parallel configuration support
|
EP0BCH = 0;
|
EP0BCH = 0;
|
EP0BCL = 3;
|
EP0BCL = 3;
|
,,));;
|
,,));;
|
|
|
/* *********************************************************************
|
/* *********************************************************************
|
***** EP0 vendor command 0x51 ***************************************
|
***** EP0 vendor command 0x51 ***************************************
|
********************************************************************* */
|
********************************************************************* */
|
ADD_EP0_VENDOR_COMMAND((0x51,, // select command
|
ADD_EP0_VENDOR_COMMAND((0x51,, // select command
|
if ( SETUPDAT[4] == 1 ) {
|
if ( SETUPDAT[4] == 1 ) {
|
config_mask_h = 0xf0;
|
config_mask_h = 0xf0;
|
}
|
}
|
else {
|
else {
|
select_fpga( SETUPDAT[2] );
|
select_fpga( SETUPDAT[2] );
|
}
|
}
|
config_mask_l = config_mask_h >> 4;
|
config_mask_l = config_mask_h >> 4;
|
,,
|
,,
|
NOP;
|
NOP;
|
));;
|
));;
|
|
|
#endif /*ZTEX_FPGA_H*/
|
#endif /*ZTEX_FPGA_H*/
|
|
|
