/*!
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/*!
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ZTEX Firmware Kit for EZ-USB Microcontrollers
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ZTEX Firmware Kit for EZ-USB FX2 Microcontrollers
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Copyright (C) 2009-2010 ZTEX e.K.
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Copyright (C) 2009-2011 ZTEX GmbH.
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http://www.ztex.de
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http://www.ztex.de
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License version 3 as
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it under the terms of the GNU General Public License version 3 as
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published by the Free Software Foundation.
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published by the Free Software Foundation.
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This program is distributed in the hope that it will be useful, but
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, see http://www.gnu.org/licenses/.
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along with this program; if not, see http://www.gnu.org/licenses/.
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!*/
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!*/
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/*
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/*
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AVR XMEGA support
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AVR XMEGA support
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*/
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*/
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#ifndef[ZTEX_XMEGA_H]
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#ifndef[ZTEX_XMEGA_H]
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#define[ZTEX_XMEGA_H]
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#define[ZTEX_XMEGA_H]
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#define[@CAPABILITY_XMEGA;]
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#define[@CAPABILITY_XMEGA;]
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#define[XMEGA_ENABLED][1]
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#define[XMEGA_ENABLED][1]
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#ifeq[PDI_PORT][E]
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#define[PDI_bmMODE]
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#elifeq[PDI_PORT][A]
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#elifeq[PDI_PORT][B]
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#elifeq[PDI_PORT][C]
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#elifneq[PDI_PORT][D]
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#error[Macro `PDI_PORT' is not defined correctly. Valid values are: `A', `B', `C', `D' and `E'.]
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#endif
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__xdata BYTE xmega_ec;
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__xdata WORD xmega_flash_pages; // in pages
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__xdata WORD xmega_eeprom_pages; // in pages
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__xdata BYTE xmega_flash_page_size; // as power of 2
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__xdata BYTE xmega_eeprom_page_size; // as power of 2
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__xdata BYTE nvm_page_type; // current page type (0: none; 1:FLASH; 2:EEPROM)
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__xdata WORD nvm_current_page;
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__xdata DWORD nvm_addr;
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__xdata BYTE nvm_boot_base; // BOOT_BASE >> 16
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#define[XMEGA_FLASH_START][0x800000]
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#define[XMEGA_EEPROM_START][0x8C0000]
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#define[XMEGA_FUSE_START][0x8F0020]
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#define[XMEGA_EC_NO_ERROR][0]
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#define[XMEGA_EC_PDI_READ_ERROR][1]
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#define[XMEGA_EC_NVM_TIMEOUT][2]
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#define[XMEGA_EC_INVALID_DEVICE][3]
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#define[XMEGA_EC_ADDRESS_ERROR][4]
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#define[XMEGA_EC_NVM_BUSY][5]
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#define[PDI_IO][IOPDI_PORT]
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#define[PDI_CLK][IOPDI_PORTPDI_BIT_CLK]
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#define[PDI_DATA][IOPDI_PORTPDI_BIT_DATA]
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#define[PDI_bmCLK][(1<<PDI_BIT_CLK)]
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#define[PDI_bmDATA][(1<<PDI_BIT_DATA)]
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#define[NVM_CMD][0xca]
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#define[NVM_CTRLA][0xcb]
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#define[NVM_STATUS][0xcf]
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/* *********************************************************************
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***** pdi_send ******************************************************
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********************************************************************* */
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// send one byte to pdi
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void pdi_send(BYTE b) {
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b; // this avoids stupid warnings
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OEPDI_PORT |= bmBITPDI_BIT_DATA;
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__asm
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#ifdef[PDI_bmMODE]
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mov a,dpl
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anl _PDI_IO, #(~PDI_bmDATA) // start bit
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anl _PDI_IO, #(~PDI_bmCLK)
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rrc a
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orl _PDI_IO, #(PDI_bmCLK)
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anl _PDI_IO, #(~PDI_bmDATA) // 0
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jnc 0100200$
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orl _PDI_IO, #(PDI_bmDATA)
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0100200$:
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anl _PDI_IO, #(~PDI_bmCLK)
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rrc a
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orl _PDI_IO, #(PDI_bmCLK)
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anl _PDI_IO, #(~PDI_bmDATA) // 1
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jnc 0100201$
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orl _PDI_IO, #(PDI_bmDATA)
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0100201$:
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anl _PDI_IO, #(~PDI_bmCLK)
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rrc a
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orl _PDI_IO, #(PDI_bmCLK)
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anl _PDI_IO, #(~PDI_bmDATA) // 2
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jnc 0100202$
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orl _PDI_IO, #(PDI_bmDATA)
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0100202$:
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anl _PDI_IO, #(~PDI_bmCLK)
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rrc a
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orl _PDI_IO, #(PDI_bmCLK)
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anl _PDI_IO, #(~PDI_bmDATA) // 3
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jnc 0100203$
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orl _PDI_IO, #(PDI_bmDATA)
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0100203$:
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anl _PDI_IO, #(~PDI_bmCLK)
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rrc a
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orl _PDI_IO, #(PDI_bmCLK)
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anl _PDI_IO, #(~PDI_bmDATA) // 4
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jnc 0100204$
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orl _PDI_IO, #(PDI_bmDATA)
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0100204$:
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anl _PDI_IO, #(~PDI_bmCLK)
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rrc a
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orl _PDI_IO, #(PDI_bmCLK)
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anl _PDI_IO, #(~PDI_bmDATA) // 5
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jnc 0100205$
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orl _PDI_IO, #(PDI_bmDATA)
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0100205$:
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anl _PDI_IO, #(~PDI_bmCLK)
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rrc a
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orl _PDI_IO, #(PDI_bmCLK)
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anl _PDI_IO, #(~PDI_bmDATA) // 6
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jnc 0100206$
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orl _PDI_IO, #(PDI_bmDATA)
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0100206$:
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anl _PDI_IO, #(~PDI_bmCLK)
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rrc a
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orl _PDI_IO, #(PDI_bmCLK)
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anl _PDI_IO, #(~PDI_bmDATA) // 7
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jnc 0100207$
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orl _PDI_IO, #(PDI_bmDATA)
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0100207$:
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anl _PDI_IO, #(~PDI_bmCLK)
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rrc a
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orl _PDI_IO, #(PDI_bmCLK)
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anl _PDI_IO, #(~PDI_bmDATA) // parity bit
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jnb _PF,0100208$
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orl _PDI_IO, #(PDI_bmDATA)
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0100208$:
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anl _PDI_IO, #(~PDI_bmCLK)
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orl _PDI_IO, #(PDI_bmCLK)
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orl _PDI_IO, #(PDI_bmDATA) // stop bit 1
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anl _PDI_IO, #(~PDI_bmCLK)
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orl _PDI_IO, #(PDI_bmCLK)
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anl _PDI_IO, #(~PDI_bmCLK) // stop bit 1
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orl _PDI_IO, #(PDI_bmCLK)
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#else
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mov a,dpl
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clr _PDI_DATA // start bit
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clr _PDI_CLK
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rrc a
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setb _PDI_CLK
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mov _PDI_DATA,c // 0
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clr _PDI_CLK
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rrc a
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setb _PDI_CLK
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mov _PDI_DATA,c // 1
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clr _PDI_CLK
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rrc a
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setb _PDI_CLK
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mov _PDI_DATA,c // 2
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clr _PDI_CLK
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rrc a
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setb _PDI_CLK
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mov _PDI_DATA,c // 3
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clr _PDI_CLK
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rrc a
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setb _PDI_CLK
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mov _PDI_DATA,c // 4
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clr _PDI_CLK
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rrc a
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setb _PDI_CLK
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mov _PDI_DATA,c // 5
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clr _PDI_CLK
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rrc a
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setb _PDI_CLK
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mov _PDI_DATA,c // 6
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clr _PDI_CLK
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rrc a
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setb _PDI_CLK
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mov _PDI_DATA,c // 7
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clr _PDI_CLK
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rrc a
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setb _PDI_CLK
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mov c,_PF
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mov _PDI_DATA,c // parity bit
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clr _PDI_CLK
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setb _PDI_CLK
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setb _PDI_DATA // stop bit 1
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clr _PDI_CLK
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setb _PDI_CLK
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clr _PDI_CLK // stop bit 2
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setb _PDI_CLK
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#endif[PDI_PORT][A]
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__endasm;
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}
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/* *********************************************************************
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***** pdi_read ******************************************************
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********************************************************************* */
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// read byte from PDI
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BYTE pdi_read() {
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xmega_ec = XMEGA_EC_NO_ERROR;
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OEPDI_PORT &= ~bmBITPDI_BIT_DATA;
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__asm
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#ifdef[PDI_bmMODE]
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anl _PDI_IO, #(~PDI_bmCLK)
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orl _PDI_IO, #(PDI_bmCLK)
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mov r1,0
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010020$: // wait for the start bit
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mov a, _PDI_IO // start bit
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anl a, #(PDI_bmDATA)
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jz 010021$
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anl _PDI_IO, #(~PDI_bmCLK)
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orl _PDI_IO, #(PDI_bmCLK)
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djnz r1,010020$
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010021$:
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anl _PDI_IO, #(~PDI_bmCLK)
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orl _PDI_IO, #(PDI_bmCLK)
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mov a, _PDI_IO // 0
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anl a, #(PDI_bmDATA)
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subb a,#1
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mov a,r1
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rrc a
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mov r1,a
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anl _PDI_IO, #(~PDI_bmCLK)
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orl _PDI_IO, #(PDI_bmCLK)
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mov a, _PDI_IO // 1
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anl a, #(PDI_bmDATA)
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subb a,#1
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mov a,r1
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rrc a
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mov r1,a
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anl _PDI_IO, #(~PDI_bmCLK)
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orl _PDI_IO, #(PDI_bmCLK)
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mov a, _PDI_IO // 2
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anl a, #(PDI_bmDATA)
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subb a,#1
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mov a,r1
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rrc a
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mov r1,a
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anl _PDI_IO, #(~PDI_bmCLK)
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orl _PDI_IO, #(PDI_bmCLK)
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mov a, _PDI_IO // 3
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anl a, #(PDI_bmDATA)
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subb a,#1
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mov a,r1
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rrc a
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mov r1,a
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anl _PDI_IO, #(~PDI_bmCLK)
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orl _PDI_IO, #(PDI_bmCLK)
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mov a, _PDI_IO // 4
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anl a, #(PDI_bmDATA)
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subb a,#1
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mov a,r1
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rrc a
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mov r1,a
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anl _PDI_IO, #(~PDI_bmCLK)
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orl _PDI_IO, #(PDI_bmCLK)
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mov a, _PDI_IO // 5
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anl a, #(PDI_bmDATA)
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subb a,#1
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mov a,r1
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rrc a
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mov r1,a
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anl _PDI_IO, #(~PDI_bmCLK)
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orl _PDI_IO, #(PDI_bmCLK)
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mov a, _PDI_IO // 6
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anl a, #(PDI_bmDATA)
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subb a,#1
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mov a,r1
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rrc a
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mov r1,a
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anl _PDI_IO, #(~PDI_bmCLK)
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orl _PDI_IO, #(PDI_bmCLK)
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mov a, _PDI_IO // 7
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anl a, #(PDI_bmDATA)
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subb a,#1
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mov a,r1
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rrc a
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xrl a,#255
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mov r1,a
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anl _PDI_IO, #(~PDI_bmCLK)
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orl _PDI_IO, #(PDI_bmCLK)
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mov a, _PDI_IO // parity bit
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anl a, #(PDI_bmDATA)
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subb a,#1
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mov a,r1
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jnc 010022$
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jb _PF, 010023$ // parity error
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sjmp 010026$
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010022$:
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jnb _PF, 010023$ // parity error
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010026$:
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anl _PDI_IO, #(~PDI_bmCLK)
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orl _PDI_IO, #(PDI_bmCLK)
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mov a, _PDI_IO // stop bit 1
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anl a, #(PDI_bmDATA)
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jz 010024$
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anl _PDI_IO, #(~PDI_bmCLK)
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orl _PDI_IO, #(PDI_bmCLK)
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mov a, _PDI_IO // stop bit 2
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anl a, #(PDI_bmDATA)
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jz 010024$
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mov dpl,r1
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ret
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010023$:
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anl _PDI_IO, #(~PDI_bmCLK)
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orl _PDI_IO, #(PDI_bmCLK)
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010024$:
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anl _PDI_IO, #(~PDI_bmCLK)
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orl _PDI_IO, #(PDI_bmCLK)
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010025$:
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#else
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clr _PDI_CLK
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setb _PDI_CLK
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mov r1,0
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010020$: // wait for the start bit
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mov c,_PDI_DATA
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jnc 010021$ // start bit
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clr _PDI_CLK
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setb _PDI_CLK
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djnz r1,010020$
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010021$:
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clr _PDI_CLK
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setb _PDI_CLK
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mov c,_PDI_DATA // 0
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rrc a
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clr _PDI_CLK
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setb _PDI_CLK
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mov c,_PDI_DATA // 1
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rrc a
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clr _PDI_CLK
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setb _PDI_CLK
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mov c,_PDI_DATA // 2
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rrc a
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clr _PDI_CLK
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setb _PDI_CLK
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mov c,_PDI_DATA // 3
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rrc a
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clr _PDI_CLK
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setb _PDI_CLK
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mov c,_PDI_DATA // 4
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rrc a
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clr _PDI_CLK
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setb _PDI_CLK
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mov c,_PDI_DATA // 5
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rrc a
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clr _PDI_CLK
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setb _PDI_CLK
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mov c,_PDI_DATA // 6
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rrc a
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clr _PDI_CLK
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setb _PDI_CLK
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mov c,_PDI_DATA // 7
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rrc a
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clr _PDI_CLK
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setb _PDI_CLK
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mov c,_PDI_DATA // parity bit
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jc 010022$
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jb _PF, 010023$ // parity error
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sjmp 010026$
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010022$:
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jnb _PF, 010023$ // parity error
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010026$:
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clr _PDI_CLK
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setb _PDI_CLK
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mov c,_PDI_DATA // stop bit 1
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jnc 010024$
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clr _PDI_CLK
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setb _PDI_CLK
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mov c,_PDI_DATA // stop bit 2
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jnc 010025$
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mov dpl,a
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ret
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010023$:
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clr _PDI_CLK
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setb _PDI_CLK
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010024$:
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clr _PDI_CLK
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setb _PDI_CLK
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010025$:
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#endif
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__endasm;
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xmega_ec = XMEGA_EC_PDI_READ_ERROR;
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return 0; // never called (just to avoid warnings)
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}
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/* *********************************************************************
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***** pdi_enable ****************************************************
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********************************************************************* */
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// enable the pdi
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void pdi_enable() { // enter PDI mode
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BYTE i;
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PDI_IO &= ~PDI_bmDATA;
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PDI_IO |= PDI_bmCLK;
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OEPDI_PORT |= bmBITPDI_BIT_DATA | bmBITPDI_BIT_CLK;
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PDI_IO |= PDI_bmDATA;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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for (i=0; i<16; i++) {
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PDI_IO &= ~PDI_bmCLK;
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PDI_IO |= PDI_bmCLK;
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}
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pdi_send(0xc2);
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pdi_send(2);
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}
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/* *********************************************************************
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***** nvm_status ****************************************************
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********************************************************************* */
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// read the NVM_STATUS register
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BYTE nvm_status () {
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pdi_send(0x0c);
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pdi_send(NVM_STATUS);
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pdi_send(0x01);
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pdi_send(0x00);
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pdi_send(0x01);
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return pdi_read();
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}
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/* *********************************************************************
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***** nvm_wait_busy *************************************************
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********************************************************************* */
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// wait up to 40ms if NVM is busy
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void nvm_wait_busy() {
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WORD w;
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// wait if nvm controller is busy
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for ( w=0; w<40000; w++ ) {
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if ( ( (nvm_status() & bmBIT7) == 0) || xmega_ec!=0 )
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return;
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}
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xmega_ec = XMEGA_EC_NVM_BUSY;
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}
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|
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/* *********************************************************************
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***** nvm_init ******************************************************
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********************************************************************* */
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// enable the NVM access via PDI
|
|
void nvm_init() { // activate the NVM controller
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|
BYTE b,c,d;
|
|
pdi_enable();
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|
|
pdi_send(0xc1); // reset
|
|
pdi_send(0x59);
|
|
|
|
pdi_send(0xe0); // send key
|
|
pdi_send(0xff);
|
|
pdi_send(0x88);
|
|
pdi_send(0xd8);
|
|
pdi_send(0xcd);
|
|
pdi_send(0x45);
|
|
pdi_send(0xab);
|
|
pdi_send(0x89);
|
|
pdi_send(0x12);
|
|
|
|
// wait until NVM is available
|
|
b = 0; c = 0;
|
|
do {
|
|
pdi_send(0x80);
|
|
c = pdi_read();
|
|
d = ((c & bmBIT1) == 0) && (xmega_ec==0);
|
|
b+=1;
|
|
} while ( (b!=0) && d );
|
|
if ( d )
|
|
xmega_ec = XMEGA_EC_NVM_TIMEOUT;
|
|
}
|
|
|
|
/* *********************************************************************
|
|
***** nvm_register_write*********************************************
|
|
********************************************************************* */
|
|
// write to NVM register
|
|
void nvm_register_write(BYTE offs, BYTE b) {
|
|
pdi_send(0x4c); // direct write
|
|
pdi_send(offs);
|
|
pdi_send(0x01);
|
|
pdi_send(0x00);
|
|
pdi_send(0x01);
|
|
pdi_send(b);
|
|
}
|
|
|
|
/* *********************************************************************
|
|
***** nvm_register_write ********************************************
|
|
********************************************************************* */
|
|
// enable the NVM access via PDI
|
|
void nvm_done() { // deactivate the NVM controller
|
|
pdi_send(0xc1); // disable reset
|
|
pdi_send(0);
|
|
|
|
nvm_register_write(NVM_CMD,0); // VNM NOP
|
|
|
|
PDI_IO &= ~PDI_bmDATA;
|
|
PDI_IO |= PDI_bmCLK;
|
|
}
|
|
|
|
void nvm_done2() { // deactivate the NVM controller
|
|
nvm_register_write(NVM_CMD,0); // VNM NOP
|
|
|
|
PDI_IO &= ~PDI_bmDATA;
|
|
PDI_IO |= PDI_bmCLK;
|
|
}
|
|
|
|
|
|
/* *********************************************************************
|
|
***** nvm_read ******************************************************
|
|
********************************************************************* */
|
|
// read NVM
|
|
BYTE nvm_read ( __xdata BYTE *buf, DWORD addr, BYTE length ) {
|
|
BYTE ol = length;
|
|
|
|
if ( length == 0 )
|
|
return 0;
|
|
|
|
nvm_register_write(NVM_CMD,0x43); // load NVM read command into NVM CMD register
|
|
|
|
pdi_send( 0x6b ); // set ptr
|
|
pdi_send( addr & 255 );
|
|
pdi_send( (addr>>8) & 255 );
|
|
pdi_send( (addr>>16) & 255 );
|
|
pdi_send( (addr>>24) & 255 );
|
|
|
|
pdi_send( 0xa0 ); // repeat cmd
|
|
pdi_send( length-1 );
|
|
pdi_send( 0x24 ); // read one byte cmd
|
|
while ( (length!=0) && (xmega_ec==0) ) {
|
|
*buf = pdi_read(); buf++;
|
|
length-= 1;
|
|
}
|
|
|
|
return ol-length;
|
|
}
|
|
|
|
/* *********************************************************************
|
|
***** nvm_page_load *************************************************
|
|
********************************************************************* */
|
|
// write data into NVM page buffer. Flash: cmd=0x23 , EEPROM: cmd=0x33
|
|
#define[nvm_flash_page_load(][);][nvm_page_load(0x23, $0);]
|
|
#define[nvm_eeprom_page_load(][);][nvm_page_load(0x33, $0);]
|
|
|
|
void nvm_page_load ( BYTE cmd, __xdata BYTE *buf, DWORD addr, BYTE length ) {
|
|
BYTE ol = length;
|
|
|
|
if ( length == 0 )
|
|
return;
|
|
|
|
nvm_register_write(NVM_CMD,cmd); // load "Load Page Buffer" command into CMD register NVM CMD register
|
|
|
|
pdi_send( 0x6b ); // set ptr
|
|
pdi_send( addr & 255 );
|
|
pdi_send( (addr>>8) & 255 );
|
|
pdi_send( (addr>>16) & 255 );
|
|
pdi_send( (addr>>24) & 255 );
|
|
|
|
pdi_send( 0xa0 ); // repeat cmd
|
|
pdi_send( length-1 );
|
|
pdi_send( 0x64 ); // write one byte cmd
|
|
while ( length!=0 ) {
|
|
pdi_send(*buf); buf++;
|
|
length-= 1;
|
|
}
|
|
}
|
|
|
|
|
|
/* *********************************************************************
|
|
***** nvm_page_write ************************************************
|
|
********************************************************************* */
|
|
// erase and write nvm page
|
|
#define[nvm_flash_page_write(][);][nvm_page_write(((BYTE)((($0)>>16) & 255)) < nvm_boot_base ? 0x25 : 0x2d, $0);]
|
|
#define[nvm_eeprom_page_write(][);][nvm_page_write(0x35, $0);]
|
|
void nvm_page_write (BYTE cmd, DWORD addr ) {
|
|
nvm_register_write(NVM_CMD, cmd); // load "erase and write page" command into NVM CMD register
|
|
|
|
pdi_send( 0x4c ); // direct write
|
|
pdi_send( addr & 255 );
|
|
pdi_send( (addr>>8) & 255 );
|
|
pdi_send( (addr>>16) & 255 );
|
|
pdi_send( (addr>>24) & 255 );
|
|
pdi_send( 0 );
|
|
|
|
nvm_wait_busy();
|
|
}
|
|
|
|
/* *********************************************************************
|
|
***** nvm_fuse_write ************************************************
|
|
********************************************************************* */
|
|
// write fuse
|
|
void nvm_fuse_write (BYTE idx, BYTE val) {
|
|
nvm_register_write(NVM_CMD, 0x4c); // load "write fuse" command into NVM CMD register
|
|
|
|
pdi_send( 0x4c ); // direct write
|
|
pdi_send( 0x20 | idx );
|
|
pdi_send( 0 );
|
|
pdi_send( 0x8f );
|
|
pdi_send( 0 );
|
|
pdi_send( val );
|
|
|
|
nvm_wait_busy();
|
|
}
|
|
|
|
/* *********************************************************************
|
|
***** xmega_reset ***************************************************
|
|
********************************************************************* */
|
|
// reset the xmega
|
|
void xmega_reset () {
|
|
OEPDI_PORT |= bmBITPDI_BIT_CLK;
|
|
uwait(20); // disable
|
|
PDI_IO &= ~PDI_bmCLK; // enable reset
|
|
|
|
uwait(5);
|
|
PDI_IO |= PDI_bmCLK;
|
|
}
|
|
|
|
/* *********************************************************************
|
|
***** xmega_init ****************************************************
|
|
********************************************************************* */
|
|
void xmega_init() {
|
|
__xdata BYTE xmega_id[3];
|
|
|
|
nvm_page_type = 0;
|
|
xmega_flash_pages = 0;
|
|
xmega_eeprom_pages = 64;
|
|
xmega_eeprom_page_size = 5;
|
|
xmega_flash_page_size = 9;
|
|
|
|
|
|
nvm_init();
|
|
if ( xmega_ec != 0 )
|
|
return;
|
|
nvm_read(xmega_id, 0x01000090, 3);
|
|
if ( xmega_ec != 0 )
|
|
return;
|
|
nvm_done();
|
|
|
|
if ( xmega_id[0] != 0x1e ) {
|
|
xmega_ec = XMEGA_EC_INVALID_DEVICE;
|
|
return;
|
|
}
|
|
|
|
/* if ( xmega_id[1] == 0x96 && xmega_id[2] == 0x4e ) { // 64A1 currently not supported
|
|
mega_flash_pages = 272;
|
|
mega_flash_page_size = 8;
|
|
nvm_boot_base = 0x81;
|
|
} */
|
|
if ( xmega_id[1] == 0x97 && xmega_id[2] == 0x4c ) { // 128A1
|
|
xmega_flash_pages = 272;
|
|
nvm_boot_base = 0x82;
|
|
}
|
|
else if ( xmega_id[1] == 0x97 && xmega_id[2] == 0x4e ) { // 192A1
|
|
xmega_flash_pages = 400;
|
|
nvm_boot_base = 0x83;
|
|
}
|
|
else if ( xmega_id[1] == 0x98 && xmega_id[2] == 0x46 ) { // 256A1
|
|
xmega_flash_pages = 528;
|
|
xmega_eeprom_pages = 128;
|
|
nvm_boot_base = 0x84;
|
|
}
|
|
else {
|
|
xmega_ec = XMEGA_EC_INVALID_DEVICE;
|
|
}
|
|
}
|
|
|
|
|
|
|
|
/* *********************************************************************
|
|
***** EP0 vendor request 0x48 ***************************************
|
|
********************************************************************* */
|
|
// send xmega error and status information to the host
|
|
ADD_EP0_VENDOR_REQUEST((0x48,,
|
|
MEM_COPY1(xmega_ec,EP0BUF,7);
|
|
EP0BCH = 0;
|
|
EP0BCL = 7;
|
|
,,
|
|
NOP;
|
|
));;
|
|
|
|
|
|
/* *********************************************************************
|
|
***** EP0 vendor request 0x49 ***************************************
|
|
********************************************************************* */
|
|
// reset xmega
|
|
ADD_EP0_VENDOR_COMMAND((0x49,,
|
|
xmega_reset();
|
|
,,
|
|
NOP;
|
|
));;
|
|
|
|
|
|
/* *********************************************************************
|
|
***** EP0 vendor requests 0x4A, 0x4B, 0x4C,0x4D *********************
|
|
********************************************************************* */
|
|
// read from nvm using: pdi address space (0x4a), flash base (0x4b), EEPROM base (0x4c), FUSE base (0x4d)
|
|
BYTE nvm_read_ep0 () {
|
|
BYTE i, b;
|
|
b = ep0_payload_transfer;
|
|
if ( b == 0 )
|
|
return 0;
|
|
|
|
nvm_init();
|
|
i = xmega_ec==0 ? nvm_read(EP0BUF, nvm_addr, b) : 0;
|
|
nvm_done();
|
|
|
|
nvm_addr += b;
|
|
return i;
|
|
}
|
|
|
|
ADD_EP0_VENDOR_REQUEST((0x4a: case 0x4b: case 0x4c: case 0x4d,, // read from NVM
|
|
nvm_addr = *(DWORD*)(&SETUPDAT[2]);
|
|
if ( bRequest == 0x4b ) { // read from Flash
|
|
nvm_addr += XMEGA_FLASH_START;
|
|
}
|
|
else if ( bRequest == 0x4c ) { // read from EEPROM
|
|
nvm_addr += XMEGA_EEPROM_START;
|
|
}
|
|
else if ( bRequest == 0x4d ) { // read FUSES
|
|
nvm_addr += XMEGA_FUSE_START;
|
|
}
|
|
EP0BCH = 0;
|
|
EP0BCL = nvm_read_ep0();
|
|
,,
|
|
EP0BCH = 0;
|
|
EP0BCL = nvm_read_ep0();
|
|
));;
|
|
|
|
|
|
/* *********************************************************************
|
|
***** EP0 vendor command 0x4B ***************************************
|
|
********************************************************************* */
|
|
// write exactly one flash page
|
|
void nvm_flash_write_ep0 () {
|
|
BYTE b;
|
|
b = ep0_payload_transfer;
|
|
|
|
nvm_init();
|
|
if ( xmega_ec != 0 )
|
|
return;
|
|
|
|
nvm_flash_page_load(EP0BUF, nvm_addr, b);
|
|
|
|
if ( ep0_payload_remaining == 0 ) {
|
|
nvm_flash_page_write( nvm_addr );
|
|
nvm_done();
|
|
}
|
|
else {
|
|
nvm_done2();
|
|
}
|
|
|
|
nvm_addr += b;
|
|
}
|
|
|
|
ADD_EP0_VENDOR_COMMAND((0x4B,,
|
|
nvm_addr = *(DWORD*)(&SETUPDAT[2]);
|
|
nvm_addr += XMEGA_FLASH_START;
|
|
if ( SETUPDAT[2]!=0 || (SETUPDAT[3] & 1)!=0 || SETUPDAT[7]!=2 || SETUPDAT[6]!=0 || (*(WORD*)(&SETUPDAT[3])>>1)>=xmega_flash_pages ) // only 512 byte pages supported
|
|
{
|
|
xmega_ec = XMEGA_EC_ADDRESS_ERROR;
|
|
EP0_STALL;
|
|
}
|
|
,,
|
|
if ( ep0_payload_transfer != 0 ) {
|
|
xmega_ec = 0;
|
|
nvm_flash_write_ep0();
|
|
if ( xmega_ec != 0 ) {
|
|
EP0_STALL;
|
|
}
|
|
}
|
|
));;
|
|
|
|
/* *********************************************************************
|
|
***** EP0 vendor command 0x4C ***************************************
|
|
********************************************************************* */
|
|
// write exactly one EEPROM page
|
|
ADD_EP0_VENDOR_COMMAND((0x4C,,
|
|
nvm_addr = *(DWORD*)(&SETUPDAT[2]);
|
|
nvm_addr += XMEGA_EEPROM_START;
|
|
if ( ( SETUPDAT[2] & 31 ) != 0 || SETUPDAT[7]!=0 || SETUPDAT[6]!=32 || (*(WORD*)(&SETUPDAT[2])>>5)>=xmega_eeprom_pages ) // only 32 byte pages supported
|
|
{
|
|
xmega_ec = XMEGA_EC_ADDRESS_ERROR;
|
|
EP0_STALL;
|
|
}
|
|
|
|
nvm_init();
|
|
if ( xmega_ec != 0 )
|
|
return;
|
|
|
|
nvm_eeprom_page_load(EP0BUF, nvm_addr, 32);
|
|
nvm_eeprom_page_write( nvm_addr );
|
|
nvm_done();
|
|
,,
|
|
));;
|
|
|
|
/* *********************************************************************
|
|
***** EP0 vendor command 0x4D ***************************************
|
|
********************************************************************* */
|
|
// write one fuse
|
|
ADD_EP0_VENDOR_COMMAND((0x4D,,
|
|
if ( SETUPDAT[6]!=0 || SETUPDAT[7]!=0 || SETUPDAT[5]!=0 || SETUPDAT[4]>7 )
|
|
{
|
|
xmega_ec = XMEGA_EC_ADDRESS_ERROR;
|
|
EP0_STALL;
|
|
}
|
|
|
|
nvm_init();
|
|
nvm_fuse_write(SETUPDAT[4], SETUPDAT[2]);
|
|
nvm_done();
|
|
,,
|
|
NOP;
|
|
));;
|
|
|
|
|
#endif /*ZTEX_XMEGA_H*/
|
#endif /*ZTEX_XMEGA_H*/
|
|
|
