/*!
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/*!
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ZTEX Firmware Kit for EZ-USB Microcontrollers
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ZTEX Firmware Kit for EZ-USB Microcontrollers
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Copyright (C) 2008-2009 ZTEX e.K.
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Copyright (C) 2008-2009 ZTEX e.K.
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http://www.ztex.de
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http://www.ztex.de
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License version 3 as
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it under the terms of the GNU General Public License version 3 as
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published by the Free Software Foundation.
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published by the Free Software Foundation.
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This program is distributed in the hope that it will be useful, but
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, see http://www.gnu.org/licenses/.
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along with this program; if not, see http://www.gnu.org/licenses/.
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!*/
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!*/
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/*
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/*
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Puts everything in the right order together.
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Puts everything together.
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*/
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*/
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#ifndef[ZTEX_H]
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#ifndef[ZTEX_H]
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#define[ZTEX_H]
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#define[ZTEX_H]
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/* *********************************************************************
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/* *********************************************************************
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***** include the basic functions ***********************************
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***** include the basic functions ***********************************
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********************************************************************* */
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********************************************************************* */
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#include[ztex-utils.h]
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#include[ztex-utils.h]
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/* *********************************************************************
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/* *********************************************************************
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***** EEPROM support and some I2c helper functions ******************
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********************************************************************* */
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#ifneq[EEPROM_DISABLED][1]
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#include[ztex-eeprom.h]
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#endif
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/* *********************************************************************
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***** Flash memory support ******************************************
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***** Flash memory support ******************************************
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********************************************************************* */
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********************************************************************* */
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#ifeq[FLASH_ENABLED][1]
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#ifeq[FLASH_ENABLED][1]
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#ifeq[PRODUCT_IS][UFM-1_1]
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#ifeq[PRODUCT_IS][UFM-1_1]
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#define[MMC_PORT][E]
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#define[MMC_BIT_CS][7]
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#define[MMC_BIT_DI][6]
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#define[MMC_BIT_DO][4]
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#define[MMC_BIT_CLK][5]
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#include[ztex-flash1.h]
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#include[ztex-flash1.h]
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#elifeq[PRODUCT_IS][UFM-1_2]
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#elifeq[PRODUCT_IS][UFM-1_2]
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#define[MMC_PORT][E]
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#define[MMC_BIT_CS][7]
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#define[MMC_BIT_DI][6]
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#define[MMC_BIT_DO][4]
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#define[MMC_BIT_CLK][5]
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#include[ztex-flash1.h]
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#elifeq[PRODUCT_IS][UM-1_0]
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#define[MMC_PORT][C]
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#define[MMC_BIT_CS][7]
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#define[MMC_BIT_DI][6]
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#define[MMC_BIT_DO][4]
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#define[MMC_BIT_CLK][5]
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#include[ztex-flash1.h]
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#include[ztex-flash1.h]
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#elifeq[PRODUCT_IS][UM-1_10]
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#define[MMC_PORT][C]
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#define[MMC_BIT_CS][4]
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#define[MMC_BIT_DI][5]
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#define[MMC_BIT_DO][7]
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#define[MMC_BIT_CLK][6]
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#include[ztex-flash1.h]
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#else
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#else
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#warning[FLASH option is not supported by this product]
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#warning[FLASH option is not supported by this product]
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#define[FLASH_ENABLED][0]
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#define[FLASH_ENABLED][0]
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#endif
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#endif
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#endif
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#endif
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/* *********************************************************************
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***** EEPROM support and some I2c helper functions ******************
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********************************************************************* */
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#ifneq[EEPROM_DISABLED][1]
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#include[ztex-eeprom.h]
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#endif
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/* *********************************************************************
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/* *********************************************************************
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***** FPGA configuration support ************************************
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***** FPGA configuration support ************************************
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********************************************************************* */
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********************************************************************* */
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#ifeq[PRODUCT_IS][UFM-1_0]
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#ifeq[PRODUCT_IS][UFM-1_0]
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#include[ztex-fpga.h]
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#include[ztex-fpga.h]
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#elifeq[PRODUCT_IS][UFM-1_1]
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#elifeq[PRODUCT_IS][UFM-1_1]
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#include[ztex-fpga.h]
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#include[ztex-fpga.h]
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#elifeq[PRODUCT_IS][UFM-1_2]
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#elifeq[PRODUCT_IS][UFM-1_2]
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#include[ztex-fpga.h]
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#include[ztex-fpga.h]
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#endif
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#endif
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/* *********************************************************************
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/* *********************************************************************
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***** define the descriptors and the interrupt routines *************
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***** define the descriptors and the interrupt routines *************
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********************************************************************* */
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********************************************************************* */
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#include[ztex-descriptors.h]
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#include[ztex-descriptors.h]
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#include[ztex-isr.h]
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#include[ztex-isr.h]
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/* *********************************************************************
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/* *********************************************************************
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***** init_USB ******************************************************
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***** init_USB ******************************************************
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********************************************************************* */
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********************************************************************* */
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#define[EPXCFG(][);][ EP$0CFG =
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#define[EPXCFG(][);][ EP$0CFG =
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#ifeq[EP$0_DIR][IN]
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#ifeq[EP$0_DIR][IN]
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bmBIT7 | bmBIT6
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bmBIT7 | bmBIT6
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#elifeq[EP$0_DIR][OUT]
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#elifeq[EP$0_DIR][OUT]
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bmBIT7
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bmBIT7
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#else
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#else
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0
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0
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#endif
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#endif
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#ifeq[EP$0_TYPE][BULK]
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#ifeq[EP$0_TYPE][BULK]
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| bmBIT5
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| bmBIT5
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#elifeq[EP$0_TYPE][ISO]
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#elifeq[EP$0_TYPE][ISO]
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| bmBIT4
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| bmBIT4
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#elifeq[EP$0_TYPE][INT]
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#elifeq[EP$0_TYPE][INT]
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| bmBIT5 | bmBIT4
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| bmBIT5 | bmBIT4
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#endif
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#endif
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#ifeq[EP$0_SIZE][1024]
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#ifeq[EP$0_SIZE][1024]
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| bmBIT3
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| bmBIT3
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#endif
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#endif
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#ifeq[EP$0_BUFFERS][2]
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#ifeq[EP$0_BUFFERS][2]
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| bmBIT1
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| bmBIT1
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#elifeq[EP$0_BUFFERS][3]
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#elifeq[EP$0_BUFFERS][3]
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| bmBIT1 | bmBIT0
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| bmBIT1 | bmBIT0
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#endif
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#endif
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;
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;
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SYNCDELAY;
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SYNCDELAY;
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]
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]
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#define[EP1XCFG(][);][#ifeq[EP$0_TYPE][BULK]
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#define[EP1XCFG(][);][#ifeq[EP$0_TYPE][BULK]
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EP$0CFG = bmBIT7 | bmBIT5;
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EP$0CFG = bmBIT7 | bmBIT5;
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#elifeq[EP$0_TYPE][ISO]
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#elifeq[EP$0_TYPE][ISO]
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EP$0CFG = bmBIT7 | bmBIT4;
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EP$0CFG = bmBIT7 | bmBIT4;
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#elifeq[EP$0_TYPE][INT]
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#elifeq[EP$0_TYPE][INT]
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EP$0CFG = bmBIT7 | bmBIT5 | bmBIT4;
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EP$0CFG = bmBIT7 | bmBIT5 | bmBIT4;
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#else
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#else
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EP$0CFG = 0;
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EP$0CFG = 0;
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#endif
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#endif
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SYNCDELAY;
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SYNCDELAY;
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]
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]
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void init_USB ()
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void init_USB ()
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{
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{
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USBCS |= 0x08;
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CPUCS = bmBIT4 | bmBIT1;
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CPUCS = bmBIT4 | bmBIT1;
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CKCON &= ~7;
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CKCON &= ~7;
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#ifeq[PRODUCT_IS][UFM-1_0]
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IOA1 = 1;
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OEA |= bmBIT1;
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#elifeq[PRODUCT_IS][UFM-1_1]
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IOA1 = 1;
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IOA1 = 1;
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OEA |= bmBIT1;
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OEA |= bmBIT1;
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#elifeq[PRODUCT_IS][UFM-1_2]
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IOA1 = 1;
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OEA |= bmBIT1;
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#endif
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EA = 0;
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EA = 0;
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EUSB = 0;
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ENABLE_AVUSB;
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ENABLE_AVUSB;
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INIT_INTERRUPT_VECTOR(INTVEC_SUDAV, SUDAV_ISR);
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INIT_INTERRUPT_VECTOR(INTVEC_SUDAV, SUDAV_ISR);
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INIT_INTERRUPT_VECTOR(INTVEC_SOF, SOF_ISR);
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INIT_INTERRUPT_VECTOR(INTVEC_SOF, SOF_ISR);
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INIT_INTERRUPT_VECTOR(INTVEC_SUTOK, SUTOK_ISR);
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INIT_INTERRUPT_VECTOR(INTVEC_SUTOK, SUTOK_ISR);
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INIT_INTERRUPT_VECTOR(INTVEC_SUSPEND, SUSP_ISR);
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INIT_INTERRUPT_VECTOR(INTVEC_SUSPEND, SUSP_ISR);
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INIT_INTERRUPT_VECTOR(INTVEC_USBRESET, URES_ISR);
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INIT_INTERRUPT_VECTOR(INTVEC_USBRESET, URES_ISR);
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INIT_INTERRUPT_VECTOR(INTVEC_HISPEED, HSGRANT_ISR);
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INIT_INTERRUPT_VECTOR(INTVEC_HISPEED, HSGRANT_ISR);
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INIT_INTERRUPT_VECTOR(INTVEC_EP0ACK, EP0ACK_ISR);
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INIT_INTERRUPT_VECTOR(INTVEC_EP0ACK, EP0ACK_ISR);
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INIT_INTERRUPT_VECTOR(INTVEC_EP0IN, EP0IN_ISR);
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INIT_INTERRUPT_VECTOR(INTVEC_EP0IN, EP0IN_ISR);
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INIT_INTERRUPT_VECTOR(INTVEC_EP0OUT, EP0OUT_ISR);
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INIT_INTERRUPT_VECTOR(INTVEC_EP0OUT, EP0OUT_ISR);
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INIT_INTERRUPT_VECTOR(INTVEC_EP1IN, EP1IN_ISR);
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INIT_INTERRUPT_VECTOR(INTVEC_EP1IN, EP1IN_ISR);
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INIT_INTERRUPT_VECTOR(INTVEC_EP1OUT, EP1OUT_ISR);
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INIT_INTERRUPT_VECTOR(INTVEC_EP1OUT, EP1OUT_ISR);
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INIT_INTERRUPT_VECTOR(INTVEC_EP2, EP2_ISR);
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INIT_INTERRUPT_VECTOR(INTVEC_EP2, EP2_ISR);
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INIT_INTERRUPT_VECTOR(INTVEC_EP4, EP4_ISR);
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INIT_INTERRUPT_VECTOR(INTVEC_EP4, EP4_ISR);
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INIT_INTERRUPT_VECTOR(INTVEC_EP6, EP6_ISR);
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INIT_INTERRUPT_VECTOR(INTVEC_EP6, EP6_ISR);
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INIT_INTERRUPT_VECTOR(INTVEC_EP8, EP8_ISR);
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INIT_INTERRUPT_VECTOR(INTVEC_EP8, EP8_ISR);
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EXIF &= ~bmBIT4;
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EXIF &= ~bmBIT4;
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USBIRQ = 0x7f;
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USBIRQ = 0x7f;
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USBIE |= 0x7f;
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USBIE |= 0x7f;
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EPIRQ = 0xff;
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EPIRQ = 0xff;
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EPIE = 0xff;
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EPIE = 0xff;
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EUSB = 1;
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EUSB = 1;
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EA = 1;
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EA = 1;
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USBCS |= 0x08;
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USBCS |= bmBIT7 | bmBIT1;
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wait(500);
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USBCS &= ~0x08;
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wait(500);
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EP1XCFG(1IN);
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EP1XCFG(1IN);
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EP1XCFG(1OUT);
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EP1XCFG(1OUT);
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EPXCFG(2);
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EPXCFG(2);
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EPXCFG(4);
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EPXCFG(4);
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EPXCFG(6);
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EPXCFG(6);
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EPXCFG(8);
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EPXCFG(8);
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#ifeq[FLASH_ENABLED][1]
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flash_init();
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#endif
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#ifeq[FLASH_BITSTREAM_ENABLED][1]
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fpga_configure_from_flash_init();
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#endif
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USBCS |= bmBIT7 | bmBIT1;
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wait(250);
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USBCS &= ~0x08;
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}
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}
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#endif /* ZTEX_H */
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#endif /* ZTEX_H */
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