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USB 1.1 PHY
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USB 1.1 PHY
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==========
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==========
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Status
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Status
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------
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------
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This core is done. It was tested with a USB 1.1 core I have written on
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This core is done. It was tested with a USB 1.1 core I have written on
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a XESS XCV800 board with a a Philips PDIUSBP11A transceiver.
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a XESS XCV800 board with a a Philips PDIUSBP11A transceiver.
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I have NOT yet tested it with my USB 2.0 Function IP core.
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I have NOT yet tested it with my USB 2.0 Function IP core.
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Test Bench
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Test Bench
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----------
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----------
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There is no test bench, period !
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There is no test bench, period !
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Please don't email me asking for one, unless you want to hire me to
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Please don't email me asking for one, unless you want to hire me to
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write one ! As I said above I have tested this core in real hardware and
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write one ! As I said above I have tested this core in real hardware and
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it works just fine.
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it works just fine.
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Documentation
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Documentation
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-------------
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-------------
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Sorry, there is none. I just don't have the time to write it. I have tried
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Sorry, there is none. I just don't have the time to write it. I have tried
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to follow the UTMI interface specification from USB 2.0 with one exception:
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to follow the UTMI interface specification from USB 2.0 with one exception:
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I have not added any error checking in the RX PHY, hence the RxError pin
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I have not added any error checking in the RX PHY, hence the RxError pin
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is permanently tide to ground.
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is permanently tide to ground.
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Misc
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Misc
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----
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----
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The USB 1.1 Phy Project Page is:
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The USB 1.1 Phy Project Page is:
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http://www.opencores.org/cores/usb_phy
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http://www.opencores.org/cores/usb_phy
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To find out more about me (Rudolf Usselmann), please visit:
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To find out more about me (Rudolf Usselmann), please visit:
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http://www.asics.ws
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http://www.asics.ws
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Directory Structure
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Directory Structure
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-------------------
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-------------------
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[core_root]
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[core_root]
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+-doc Documentation
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+-doc Documentation
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+-bench--+ Test Bench
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+-bench--+ Test Bench
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| +- verilog Verilog Sources
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| +- verilog Verilog Sources
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| +-vhdl VHDL Sources
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| +-vhdl VHDL Sources
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+-rtl----+ Core RTL Sources
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+-rtl----+ Core RTL Sources
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| +-verilog Verilog Sources
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| +-verilog Verilog Sources
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| +-vhdl VHDL Sources
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| +-vhdl VHDL Sources
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+-sim----+
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+-sim----+
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| +-rtl_sim---+ Functional verification Directory
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| +-rtl_sim---+ Functional verification Directory
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| | +-bin Makefiles/Run Scripts
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| | +-bin Makefiles/Run Scripts
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| | +-run Working Directory
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| | +-run Working Directory
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| +-gate_sim--+ Functional & Timing Gate Level
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| +-gate_sim--+ Functional & Timing Gate Level
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| | Verification Directory
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| | Verification Directory
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| +-bin Makefiles/Run Scripts
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| +-bin Makefiles/Run Scripts
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| +-run Working Directory
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| +-run Working Directory
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+-lint--+ Lint Directory Tree
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+-lint--+ Lint Directory Tree
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| +-bin Makefiles/Run Scripts
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| +-bin Makefiles/Run Scripts
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| +-run Working Directory
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| +-run Working Directory
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| +-log Linter log & result files
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| +-log Linter log & result files
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+-syn---+ Synthesis Directory Tree
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+-syn---+ Synthesis Directory Tree
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| +-bin Synthesis Scripts
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| +-bin Synthesis Scripts
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| +-run Working Directory
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| +-run Working Directory
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| +-log Synthesis log files
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| +-log Synthesis log files
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| +-out Synthesis Output
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| +-out Synthesis Output
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