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`/////////////////////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////////////////////`
`//// ////`	`//// ////`
`//// USB 1.1 PHY ////`	`//// USB 1.1 PHY ////`
`//// ////`	`//// ////`
`//// ////`	`//// ////`
`//// Author: Rudolf Usselmann ////`	`//// Author: Rudolf Usselmann ////`
`//// rudi@asics.ws ////`	`//// rudi@asics.ws ////`
`//// ////`	`//// ////`
`//// ////`	`//// ////`
`//// Downloaded from: http://www.opencores.org/cores/usb_phy/ ////`	`//// Downloaded from: http://www.opencores.org/cores/usb_phy/ ////`
`//// ////`	`//// ////`
`/////////////////////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////////////////////`
`//// ////`	`//// ////`
`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`	`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
`//// www.asics.ws ////`	`//// www.asics.ws ////`
`//// rudi@asics.ws ////`	`//// rudi@asics.ws ////`
`//// ////`	`//// ////`
`//// This source file may be used and distributed without ////`	`//// This source file may be used and distributed without ////`
`//// restriction provided that this copyright statement is not ////`	`//// restriction provided that this copyright statement is not ////`
`//// removed from the file and that any derivative work contains ////`	`//// removed from the file and that any derivative work contains ////`
`//// the original copyright notice and the associated disclaimer.////`	`//// the original copyright notice and the associated disclaimer.////`
`//// ////`	`//// ////`
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////	//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`	`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`	`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`	`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`	`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`	`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`	`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`	`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`	`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`	`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`	`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`	`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
`//// POSSIBILITY OF SUCH DAMAGE. ////`	`//// POSSIBILITY OF SUCH DAMAGE. ////`
`//// ////`	`//// ////`
`/////////////////////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////////////////////`

`// CVS Log`	`// CVS Log`
`//`	`//`
`// $Id: usb_phy.v,v 1.1.1.1 2002-09-16 14:26:59 rudi Exp $`	`// $Id: usb_phy.v,v 1.2 2002-09-16 16:06:37 rudi Exp $`
`//`	`//`
`// $Date: 2002-09-16 14:26:59 $`	`// $Date: 2002-09-16 16:06:37 $`
`// $Revision: 1.1.1.1 $`	`// $Revision: 1.2 $`
`// $Author: rudi $`	`// $Author: rudi $`
`// $Locker: $`	`// $Locker: $`
`// $State: Exp $`	`// $State: Exp $`
`//`	`//`
`// Change History:`	`// Change History:`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1.1.1 2002/09/16 14:26:59 rudi`
	`// Created Directory Structure`
	`//`
`//`	`//`
`//`	`//`
`//`	`//`
`//`	`//`
`//`	`//`
`//`	`//`
`//`	`//`

`include "timescale.v"	`include "timescale.v"

`module usbf_phy(clk, rst, phy_tx_mode, usb_rst,`	`module usb_phy(clk, rst, phy_tx_mode, usb_rst,`

`// Transciever Interface`	`// Transciever Interface`
`txdp, txdn, txoe,`	`txdp, txdn, txoe,`
`rxd, rxdp, rxdn,`	`rxd, rxdp, rxdn,`

`// UTMI Interface`	`// UTMI Interface`
`DataOut_i, TxValid_i, TxReady_o, RxValid_o,`	`DataOut_i, TxValid_i, TxReady_o, RxValid_o,`
`RxActive_o, RxError_o, DataIn_o, LineState_o`	`RxActive_o, RxError_o, DataIn_o, LineState_o`
`);`	`);`

`input clk;`	`input clk;`
`input rst;`	`input rst;`
`input phy_tx_mode;`	`input phy_tx_mode;`
`output usb_rst;`	`output usb_rst;`
`output txdp, txdn, txoe;`	`output txdp, txdn, txoe;`
`input rxd, rxdp, rxdn;`	`input rxd, rxdp, rxdn;`
`input [7:0] DataOut_i;`	`input [7:0] DataOut_i;`
`input TxValid_i;`	`input TxValid_i;`
`output TxReady_o;`	`output TxReady_o;`
`output [7:0] DataIn_o;`	`output [7:0] DataIn_o;`
`output RxValid_o;`	`output RxValid_o;`
`output RxActive_o;`	`output RxActive_o;`
`output RxError_o;`	`output RxError_o;`
`output [1:0] LineState_o;`	`output [1:0] LineState_o;`

`///////////////////////////////////////////////////////////////////`	`///////////////////////////////////////////////////////////////////`
`//`	`//`
`// Local Wires and Registers`	`// Local Wires and Registers`
`//`	`//`

`reg [5:0] rst_cnt;`	`reg [5:0] rst_cnt;`
`reg usb_rst;`	`reg usb_rst;`
`wire reset;`	`wire reset;`

`///////////////////////////////////////////////////////////////////`	`///////////////////////////////////////////////////////////////////`
`//`	`//`
`// Misc Logic`	`// Misc Logic`
`//`	`//`

`assign reset = rst & ~usb_rst;`	`assign reset = rst & ~usb_rst;`

`///////////////////////////////////////////////////////////////////`	`///////////////////////////////////////////////////////////////////`
`//`	`//`
`// TX Phy`	`// TX Phy`
`//`	`//`

`usb_tx_phy i_tx_phy(`	`usb_tx_phy i_tx_phy(`
`.clk( clk ),`	`.clk( clk ),`
`.rst( reset ),`	`.rst( reset ),`
`.fs_ce( fs_ce ),`	`.fs_ce( fs_ce ),`
`.phy_mode( phy_tx_mode ),`	`.phy_mode( phy_tx_mode ),`

`// Transciever Interface`	`// Transciever Interface`
`.txdp( txdp ),`	`.txdp( txdp ),`
`.txdn( txdn ),`	`.txdn( txdn ),`
`.txoe( txoe ),`	`.txoe( txoe ),`

`// UTMI Interface`	`// UTMI Interface`
`.DataOut_i( DataOut_i ),`	`.DataOut_i( DataOut_i ),`
`.TxValid_i( TxValid_i ),`	`.TxValid_i( TxValid_i ),`
`.TxReady_o( TxReady_o )`	`.TxReady_o( TxReady_o )`
`);`	`);`

`///////////////////////////////////////////////////////////////////`	`///////////////////////////////////////////////////////////////////`
`//`	`//`
`// RX Phy and DPLL`	`// RX Phy and DPLL`
`//`	`//`

`usb_rx_phy i_rx_phy(`	`usb_rx_phy i_rx_phy(`
`.clk( clk ),`	`.clk( clk ),`
`.rst( reset ),`	`.rst( reset ),`
`.fs_ce( fs_ce ),`	`.fs_ce( fs_ce ),`

`// Transciever Interface`	`// Transciever Interface`
`.rxd( rxd ),`	`.rxd( rxd ),`
`.rxdp( rxdp ),`	`.rxdp( rxdp ),`
`.rxdn( rxdn ),`	`.rxdn( rxdn ),`

`// UTMI Interface`	`// UTMI Interface`
`.DataIn_o( DataIn_o ),`	`.DataIn_o( DataIn_o ),`
`.RxValid_o( RxValid_o ),`	`.RxValid_o( RxValid_o ),`
`.RxActive_o( RxActive_o ),`	`.RxActive_o( RxActive_o ),`
`.RxError_o( RxError_o ),`	`.RxError_o( RxError_o ),`
`.RxEn_i( txoe ),`	`.RxEn_i( txoe ),`
`.LineState( LineState_o )`	`.LineState( LineState_o )`
`);`	`);`

`///////////////////////////////////////////////////////////////////`	`///////////////////////////////////////////////////////////////////`
`//`	`//`
`// Generate an USB Reset is we see SE0 for at least 2.5uS`	`// Generate an USB Reset is we see SE0 for at least 2.5uS`
`//`	`//`

`always @(posedge clk)`	`always @(posedge clk)`
`if(!rst) rst_cnt <= #1 5'h0;`	`if(!rst) rst_cnt <= #1 5'h0;`
`else`	`else`
`if(LineState_o != 2'h0) rst_cnt <= #1 5'h0;`	`if(LineState_o != 2'h0) rst_cnt <= #1 5'h0;`
`else`	`else`
`if(!usb_rst & fs_ce) rst_cnt <= #1 rst_cnt + 5'h1;`	`if(!usb_rst & fs_ce) rst_cnt <= #1 rst_cnt + 5'h1;`

`always @(posedge clk)`	`always @(posedge clk)`
`usb_rst <= #1 (rst_cnt == 5'd31);`	`usb_rst <= #1 (rst_cnt == 5'd31);`

`endmodule`	`endmodule`

/////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////

////                                                             ////

////                                                             ////

////  USB 1.1 PHY                                                ////

////  USB 1.1 PHY                                                ////

////                                                             ////

////                                                             ////

////                                                             ////

////                                                             ////

////  Author: Rudolf Usselmann                                   ////

////  Author: Rudolf Usselmann                                   ////

////          rudi@asics.ws                                      ////

////          rudi@asics.ws                                      ////

////                                                             ////

////                                                             ////

////                                                             ////

////                                                             ////

////  Downloaded from: http://www.opencores.org/cores/usb_phy/   ////

////  Downloaded from: http://www.opencores.org/cores/usb_phy/   ////

////                                                             ////

////                                                             ////

/////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////

////                                                             ////

////                                                             ////

//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////

//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////

////                         www.asics.ws                        ////

////                         www.asics.ws                        ////

////                         rudi@asics.ws                       ////

////                         rudi@asics.ws                       ////

////                                                             ////

////                                                             ////

//// This source file may be used and distributed without        ////

//// This source file may be used and distributed without        ////

//// restriction provided that this copyright statement is not   ////

//// restriction provided that this copyright statement is not   ////

//// removed from the file and that any derivative work contains ////

//// removed from the file and that any derivative work contains ////

//// the original copyright notice and the associated disclaimer.////

//// the original copyright notice and the associated disclaimer.////

////                                                             ////

////                                                             ////

////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////

////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////

//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////

//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////

//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////

//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////

//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////

//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////

//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////

//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////

//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////

//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////

//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////

//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////

//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////

//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////

//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////

//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////

//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////

//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////

//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////

//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////

//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////

//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////

//// POSSIBILITY OF SUCH DAMAGE.                                 ////

//// POSSIBILITY OF SUCH DAMAGE.                                 ////

////                                                             ////

////                                                             ////

/////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////

//  CVS Log

//  CVS Log

//

//

//  $Id: usb_phy.v,v 1.1.1.1 2002-09-16 14:26:59 rudi Exp $

//  $Id: usb_phy.v,v 1.2 2002-09-16 16:06:37 rudi Exp $

//

//

//  $Date: 2002-09-16 14:26:59 $

//  $Date: 2002-09-16 16:06:37 $

//  $Revision: 1.1.1.1 $

//  $Revision: 1.2 $

//  $Author: rudi $

//  $Author: rudi $

//  $Locker:  $

//  $Locker:  $

//  $State: Exp $

//  $State: Exp $

//

//

// Change History:

// Change History:

//               $Log: not supported by cvs2svn $

//               $Log: not supported by cvs2svn $

//               Revision 1.1.1.1  2002/09/16 14:26:59  rudi

//               Created Directory Structure

//

//

//

//

//

//

//

//

//

//

//

//

//

//

//

`include "timescale.v"

`include "timescale.v"

module usbf_phy(clk, rst, phy_tx_mode, usb_rst,

module usb_phy(clk, rst, phy_tx_mode, usb_rst,

                // Transciever Interface

                // Transciever Interface

                txdp, txdn, txoe,

                txdp, txdn, txoe,

                rxd, rxdp, rxdn,

                rxd, rxdp, rxdn,

                // UTMI Interface

                // UTMI Interface

                DataOut_i, TxValid_i, TxReady_o, RxValid_o,

                DataOut_i, TxValid_i, TxReady_o, RxValid_o,

                RxActive_o, RxError_o, DataIn_o, LineState_o

                RxActive_o, RxError_o, DataIn_o, LineState_o

);

);

input           clk;

input           clk;

input           rst;

input           rst;

input           phy_tx_mode;

input           phy_tx_mode;

output          usb_rst;

output          usb_rst;

output          txdp, txdn, txoe;

output          txdp, txdn, txoe;

input           rxd, rxdp, rxdn;

input           rxd, rxdp, rxdn;

input   [7:0]    DataOut_i;

input   [7:0]    DataOut_i;

input           TxValid_i;

input           TxValid_i;

output          TxReady_o;

output          TxReady_o;

output  [7:0]    DataIn_o;

output  [7:0]    DataIn_o;

output          RxValid_o;

output          RxValid_o;

output          RxActive_o;

output          RxActive_o;

output          RxError_o;

output          RxError_o;

output  [1:0]    LineState_o;

output  [1:0]    LineState_o;

///////////////////////////////////////////////////////////////////

///////////////////////////////////////////////////////////////////

//

//

// Local Wires and Registers

// Local Wires and Registers

//

//

reg     [5:0]    rst_cnt;

reg     [5:0]    rst_cnt;

reg             usb_rst;

reg             usb_rst;

wire            reset;

wire            reset;

///////////////////////////////////////////////////////////////////

///////////////////////////////////////////////////////////////////

//

//

// Misc Logic

// Misc Logic

//

//

assign reset = rst & ~usb_rst;

assign reset = rst & ~usb_rst;

///////////////////////////////////////////////////////////////////

///////////////////////////////////////////////////////////////////

//

//

// TX Phy

// TX Phy

//

//

usb_tx_phy i_tx_phy(

usb_tx_phy i_tx_phy(

        .clk(           clk             ),

        .clk(           clk             ),

        .rst(           reset           ),

        .rst(           reset           ),

        .fs_ce(         fs_ce           ),

        .fs_ce(         fs_ce           ),

        .phy_mode(      phy_tx_mode     ),

        .phy_mode(      phy_tx_mode     ),

        // Transciever Interface

        // Transciever Interface

        .txdp(          txdp            ),

        .txdp(          txdp            ),

        .txdn(          txdn            ),

        .txdn(          txdn            ),

        .txoe(          txoe            ),

        .txoe(          txoe            ),

        // UTMI Interface

        // UTMI Interface

        .DataOut_i(     DataOut_i       ),

        .DataOut_i(     DataOut_i       ),

        .TxValid_i(     TxValid_i       ),

        .TxValid_i(     TxValid_i       ),

        .TxReady_o(     TxReady_o       )

        .TxReady_o(     TxReady_o       )

);

);

///////////////////////////////////////////////////////////////////

///////////////////////////////////////////////////////////////////

//

//

// RX Phy and DPLL

// RX Phy and DPLL

//

//

usb_rx_phy i_rx_phy(

usb_rx_phy i_rx_phy(

        .clk(           clk             ),

        .clk(           clk             ),

        .rst(           reset           ),

        .rst(           reset           ),

        .fs_ce(         fs_ce           ),

        .fs_ce(         fs_ce           ),

        // Transciever Interface

        // Transciever Interface

        .rxd(           rxd             ),

        .rxd(           rxd             ),

        .rxdp(          rxdp            ),

        .rxdp(          rxdp            ),

        .rxdn(          rxdn            ),

        .rxdn(          rxdn            ),

        // UTMI Interface

        // UTMI Interface

        .DataIn_o(      DataIn_o        ),

        .DataIn_o(      DataIn_o        ),

        .RxValid_o(     RxValid_o       ),

        .RxValid_o(     RxValid_o       ),

        .RxActive_o(    RxActive_o      ),

        .RxActive_o(    RxActive_o      ),

        .RxError_o(     RxError_o       ),

        .RxError_o(     RxError_o       ),

        .RxEn_i(        txoe            ),

        .RxEn_i(        txoe            ),

        .LineState(     LineState_o     )

        .LineState(     LineState_o     )

);

);

///////////////////////////////////////////////////////////////////

///////////////////////////////////////////////////////////////////

//

//

// Generate an USB Reset is we see SE0 for at least 2.5uS

// Generate an USB Reset is we see SE0 for at least 2.5uS

//

//

always @(posedge clk)

always @(posedge clk)

        if(!rst)                        rst_cnt <= #1 5'h0;

        if(!rst)                        rst_cnt <= #1 5'h0;

        else

        else

        if(LineState_o != 2'h0)         rst_cnt <= #1 5'h0;

        if(LineState_o != 2'h0)         rst_cnt <= #1 5'h0;

        else

        else

        if(!usb_rst & fs_ce)            rst_cnt <= #1 rst_cnt + 5'h1;

        if(!usb_rst & fs_ce)            rst_cnt <= #1 rst_cnt + 5'h1;

always @(posedge clk)

always @(posedge clk)

        usb_rst <= #1 (rst_cnt == 5'd31);

        usb_rst <= #1 (rst_cnt == 5'd31);

endmodule

endmodule

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