//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// fifoMem.v ////
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//// fifoMem.v ////
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//// ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// ////
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//// Module Description: ////
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//// Module Description: ////
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////
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////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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////
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////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// $Id: fifoMem.v,v 1.1.1.1 2004-10-11 04:00:51 sfielding Exp $
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// $Id: fifoMem.v,v 1.1.1.1 2004-10-11 04:00:51 sfielding Exp $
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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//
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//
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module fifoMem( addrIn, addrOut, clk, dataIn, writeEn, readEn, dataOut);
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module fifoMem( addrIn, addrOut, clk, dataIn, writeEn, readEn, dataOut);
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//FIFO_DEPTH = ADDR_WIDTH^2
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//FIFO_DEPTH = ADDR_WIDTH^2
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parameter FIFO_WIDTH = 8;
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parameter FIFO_WIDTH = 8;
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parameter FIFO_DEPTH = 64;
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parameter FIFO_DEPTH = 64;
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parameter ADDR_WIDTH = 6;
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parameter ADDR_WIDTH = 6;
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input clk;
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input clk;
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input [FIFO_WIDTH-1:0] dataIn;
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input [FIFO_WIDTH-1:0] dataIn;
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output [FIFO_WIDTH-1:0] dataOut;
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output [FIFO_WIDTH-1:0] dataOut;
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input writeEn;
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input writeEn;
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input readEn;
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input readEn;
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input [ADDR_WIDTH-1:0] addrIn;
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input [ADDR_WIDTH-1:0] addrIn;
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input [ADDR_WIDTH-1:0] addrOut;
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input [ADDR_WIDTH-1:0] addrOut;
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wire clk;
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wire clk;
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wire [FIFO_WIDTH-1:0] dataIn;
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wire [FIFO_WIDTH-1:0] dataIn;
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wire [FIFO_WIDTH-1:0] dataOut;
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wire [FIFO_WIDTH-1:0] dataOut;
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wire writeEn;
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wire writeEn;
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wire readEn;
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wire readEn;
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wire [ADDR_WIDTH-1:0] addrIn;
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wire [ADDR_WIDTH-1:0] addrIn;
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wire [ADDR_WIDTH-1:0] addrOut;
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wire [ADDR_WIDTH-1:0] addrOut;
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/* generic_dpram #(ADDR_WIDTH, FIFO_WIDTH) u_generic_dpram(
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/* generic_dpram #(ADDR_WIDTH, FIFO_WIDTH) u_generic_dpram(
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// Generic synchronous dual-port RAM interface
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// Generic synchronous dual-port RAM interface
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.rclk(clk),
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.rclk(clk),
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.rrst(1'b0),
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.rrst(1'b0),
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.rce(1'b1),
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.rce(1'b1),
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.oe(readEn),
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.oe(readEn),
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.raddr(addrOut),
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.raddr(addrOut),
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.do(dataOut),
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.do(dataOut),
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.wclk(clk),
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.wclk(clk),
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.wrst(1'b0),
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.wrst(1'b0),
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.wce(1'b1),
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.wce(1'b1),
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.we(writeEn),
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.we(writeEn),
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.waddr(addrIn),
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.waddr(addrIn),
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.di(dataIn)
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.di(dataIn)
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); */
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); */
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simFifoMem #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH) u_simFifoMem (
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simFifoMem #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH) u_simFifoMem (
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.addrIn(addrIn),
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.addrIn(addrIn),
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.addrOut(addrOut),
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.addrOut(addrOut),
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.clk(clk),
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.clk(clk),
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.dataIn(dataIn),
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.dataIn(dataIn),
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.writeEn(writeEn),
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.writeEn(writeEn),
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.readEn(readEn),
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.readEn(readEn),
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.dataOut(dataOut));
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.dataOut(dataOut));
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