//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// usbSerialInterfaceEngine_h.v ////
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//// usbSerialInterfaceEngine_h.v ////
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//// ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// ////
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//// Module Description: ////
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//// Module Description: ////
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////
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////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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////
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////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// $Id: usbSerialInterfaceEngine_h.v,v 1.1.1.1 2004-10-11 04:00:57 sfielding Exp $
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// $Id: usbSerialInterfaceEngine_h.v,v 1.1.1.1 2004-10-11 04:00:57 sfielding Exp $
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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//
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//
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// Sampling at 'OVER_SAMPLE_RATE' * full speed bit rate
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// Sampling at 'OVER_SAMPLE_RATE' * full speed bit rate
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`define OVER_SAMPLE_RATE 4
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`define OVER_SAMPLE_RATE 4
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//timeOuts
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//timeOuts
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`define RX_PACKET_TOUT 18
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`define RX_PACKET_TOUT 18
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//TXStreamControlTypes
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//TXStreamControlTypes
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`define TX_DIRECT_CONTROL 8'h00
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`define TX_DIRECT_CONTROL 8'h00
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`define TX_RESUME_START 8'h01
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`define TX_RESUME_START 8'h01
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`define TX_PACKET_START 8'h02
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`define TX_PACKET_START 8'h02
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`define TX_PACKET_STREAM 8'h03
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`define TX_PACKET_STREAM 8'h03
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`define TX_PACKET_STOP 8'h04
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`define TX_PACKET_STOP 8'h04
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`define TX_IDLE 8'h05
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`define TX_IDLE 8'h05
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//RXStreamControlTypes
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//RXStreamControlTypes
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`define RX_PACKET_START 0
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`define RX_PACKET_START 0
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`define RX_PACKET_STREAM 1
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`define RX_PACKET_STREAM 1
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`define RX_PACKET_STOP 2
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`define RX_PACKET_STOP 2
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//USBLineStates
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//USBLineStates
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// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo
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// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo
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`define ONE_ZERO 2'b10
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`define ONE_ZERO 2'b10
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`define ZERO_ONE 2'b01
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`define ZERO_ONE 2'b01
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`define SE0 2'b00
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`define SE0 2'b00
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`define SE1 2'b11
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`define SE1 2'b11
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//RXStatusIndices
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//RXStatusIndices
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`define CRC_ERROR_BIT 0
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`define CRC_ERROR_BIT 0
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`define BIT_STUFF_ERROR_BIT 1
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`define BIT_STUFF_ERROR_BIT 1
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`define RX_OVERFLOW_BIT 2
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`define RX_OVERFLOW_BIT 2
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`define NAK_RXED_BIT 3
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`define NAK_RXED_BIT 3
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`define STALL_RXED_BIT 4
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`define STALL_RXED_BIT 4
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`define ACK_RXED_BIT 5
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`define ACK_RXED_BIT 5
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`define DATA_SEQUENCE_BIT 6
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`define DATA_SEQUENCE_BIT 6
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//usbWireControlStates
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//usbWireControlStates
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`define TRI_STATE 1'b0
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`define TRI_STATE 1'b0
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`define DRIVE 1'b1
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`define DRIVE 1'b1
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//limits
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//limits
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`define MAX_CONSEC_SAME_BITS 6
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`define MAX_CONSEC_SAME_BITS 6
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`define RESUME_WAIT_TIME 10
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`define RESUME_WAIT_TIME 10
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`define RESUME_WAIT_TIME_MINUS1 9
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`define RESUME_WAIT_TIME_MINUS1 9
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`define RESUME_LEN 20
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`define RESUME_LEN 20
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`define CONNECT_WAIT_TIME 8'd20
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`define CONNECT_WAIT_TIME 8'd20
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`define DISCONNECT_WAIT_TIME 8'd20
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`define DISCONNECT_WAIT_TIME 8'd20
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//RXConnectStates
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//RXConnectStates
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`define DISCONNECT 2'b00
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`define DISCONNECT 2'b00
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`define LOW_SPEED_CONNECT 2'b01
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`define LOW_SPEED_CONNECT 2'b01
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`define FULL_SPEED_CONNECT 2'b10
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`define FULL_SPEED_CONNECT 2'b10
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//TX_RX_InternalStreamTypes
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//TX_RX_InternalStreamTypes
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`define DATA_START 8'h00
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`define DATA_START 8'h00
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`define DATA_STOP 8'h01
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`define DATA_STOP 8'h01
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`define DATA_STREAM 8'h02
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`define DATA_STREAM 8'h02
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`define DATA_BIT_STUFF_ERROR 8'h03
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`define DATA_BIT_STUFF_ERROR 8'h03
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//RXStMach states
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//RXStMach states
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`define DISCONNECT_ST 4'h0
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`define DISCONNECT_ST 4'h0
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`define WAIT_FULL_SPEED_CONN_ST 4'h1
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`define WAIT_FULL_SPEED_CONN_ST 4'h1
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`define WAIT_LOW_SPEED_CONN_ST 4'h2
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`define WAIT_LOW_SPEED_CONN_ST 4'h2
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`define CONNECT_LOW_SPEED_ST 4'h3
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`define CONNECT_LOW_SPEED_ST 4'h3
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`define CONNECT_FULL_SPEED_ST 4'h4
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`define CONNECT_FULL_SPEED_ST 4'h4
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`define WAIT_LOW_SP_DISCONNECT_ST 4'h5
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`define WAIT_LOW_SP_DISCONNECT_ST 4'h5
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`define WAIT_FULL_SP_DISCONNECT_ST 4'h6
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`define WAIT_FULL_SP_DISCONNECT_ST 4'h6
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//RXBitStateMachStates
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//RXBitStateMachStates
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`define IDLE_BIT_ST 2'b00
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`define IDLE_BIT_ST 2'b00
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`define DATA_RECEIVE_BIT_ST 2'b01
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`define DATA_RECEIVE_BIT_ST 2'b01
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`define WAIT_RESUME_ST 2'b10
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`define WAIT_RESUME_ST 2'b10
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`define RESUME_END_WAIT_ST 2'b11
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`define RESUME_END_WAIT_ST 2'b11
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//RXByteStateMachStates
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//RXByteStateMachStates
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`define IDLE_BYTE_ST 3'b000
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`define IDLE_BYTE_ST 3'b000
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`define CHECK_SYNC_ST 3'b001
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`define CHECK_SYNC_ST 3'b001
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`define CHECK_PID_ST 3'b010
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`define CHECK_PID_ST 3'b010
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`define HS_BYTE_ST 3'b011
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`define HS_BYTE_ST 3'b011
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`define TOKEN_BYTE_ST 3'b100
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`define TOKEN_BYTE_ST 3'b100
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`define DATA_BYTE_ST 3'b101
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`define DATA_BYTE_ST 3'b101
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