//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// readUSBWireData.v ////
|
//// readUSBWireData.v ////
|
//// ////
|
//// ////
|
//// This file is part of the usbhostslave opencores effort.
|
//// This file is part of the usbhostslave opencores effort.
|
//// <http://www.opencores.org/cores//> ////
|
//// <http://www.opencores.org/cores//> ////
|
//// ////
|
//// ////
|
//// Module Description: ////
|
//// Module Description: ////
|
////
|
////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
////
|
////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Steve Fielding, sfielding@base2designs.com ////
|
//// - Steve Fielding, sfielding@base2designs.com ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
|
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from <http://www.opencores.org/lgpl.shtml> ////
|
//// from <http://www.opencores.org/lgpl.shtml> ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// $Id: readUSBWireData.v,v 1.1.1.1 2004-10-11 04:01:01 sfielding Exp $
|
// $Id: readUSBWireData.v,v 1.1.1.1 2004-10-11 04:01:01 sfielding Exp $
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
//
|
//
|
|
|
`timescale 1ns / 1ps
|
`timescale 1ns / 1ps
|
`include "usbSerialInterfaceEngine_h.v"
|
`include "usbSerialInterfaceEngine_h.v"
|
|
|
module readUSBWireData (RxBitsIn, RxDataInTick, RxBitsOut, SIERxRdyIn, SIERxWEn, fullSpeedRate, disableWireRead, clk, rst);
|
module readUSBWireData (RxBitsIn, RxDataInTick, RxBitsOut, SIERxRdyIn, SIERxWEn, fullSpeedRate, disableWireRead, clk, rst);
|
input [1:0] RxBitsIn;
|
input [1:0] RxBitsIn;
|
output RxDataInTick;
|
output RxDataInTick;
|
input SIERxRdyIn;
|
input SIERxRdyIn;
|
input clk;
|
input clk;
|
input fullSpeedRate;
|
input fullSpeedRate;
|
input rst;
|
input rst;
|
input disableWireRead;
|
input disableWireRead;
|
output [1:0] RxBitsOut;
|
output [1:0] RxBitsOut;
|
output SIERxWEn;
|
output SIERxWEn;
|
|
|
wire [1:0] RxBitsIn;
|
wire [1:0] RxBitsIn;
|
reg RxDataInTick;
|
reg RxDataInTick;
|
wire SIERxRdyIn;
|
wire SIERxRdyIn;
|
wire clk;
|
wire clk;
|
wire fullSpeedRate;
|
wire fullSpeedRate;
|
wire rst;
|
wire rst;
|
reg [1:0] RxBitsOut;
|
reg [1:0] RxBitsOut;
|
reg SIERxWEn;
|
reg SIERxWEn;
|
|
|
// local registers
|
// local registers
|
reg [1:0]buffer0;
|
reg [1:0]buffer0;
|
reg [1:0]buffer1;
|
reg [1:0]buffer1;
|
reg [1:0]buffer2;
|
reg [1:0]buffer2;
|
reg [1:0]buffer3;
|
reg [1:0]buffer3;
|
reg [2:0]bufferCnt;
|
reg [2:0]bufferCnt;
|
reg [1:0]bufferInIndex;
|
reg [1:0]bufferInIndex;
|
reg [1:0]bufferOutIndex;
|
reg [1:0]bufferOutIndex;
|
reg decBufferCnt;
|
reg decBufferCnt;
|
reg [4:0]i;
|
reg [4:0]i;
|
reg incBufferCnt;
|
reg incBufferCnt;
|
reg [1:0]oldRxBitsIn;
|
reg [1:0]oldRxBitsIn;
|
|
|
// buffer output state machine state codes:
|
// buffer output state machine state codes:
|
`define WAIT_BUFFER_NOT_EMPTY 2'b00
|
`define WAIT_BUFFER_NOT_EMPTY 2'b00
|
`define WAIT_SIE_RX_READY 2'b01
|
`define WAIT_SIE_RX_READY 2'b01
|
`define SIE_RX_WRITE 2'b10
|
`define SIE_RX_WRITE 2'b10
|
|
|
reg [1:0] bufferOutStMachCurrState;
|
reg [1:0] bufferOutStMachCurrState;
|
|
|
|
|
always @(posedge clk) begin
|
always @(posedge clk) begin
|
if (rst == 1'b1)
|
if (rst == 1'b1)
|
begin
|
begin
|
bufferCnt <= 3'b000;
|
bufferCnt <= 3'b000;
|
end
|
end
|
else begin
|
else begin
|
if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
|
if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
|
bufferCnt <= bufferCnt + 1'b1;
|
bufferCnt <= bufferCnt + 1'b1;
|
else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
|
else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
|
bufferCnt <= bufferCnt - 1'b1;
|
bufferCnt <= bufferCnt - 1'b1;
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
//Perform line rate clock recovery
|
//Perform line rate clock recovery
|
//Recover the wire data, and store data to buffer
|
//Recover the wire data, and store data to buffer
|
always @(posedge clk) begin
|
always @(posedge clk) begin
|
if (rst == 1'b1)
|
if (rst == 1'b1)
|
begin
|
begin
|
i <= 5'b00000;
|
i <= 5'b00000;
|
incBufferCnt <= 1'b0;
|
incBufferCnt <= 1'b0;
|
bufferInIndex <= 2'b00;
|
bufferInIndex <= 2'b00;
|
buffer0 <= 2'b00;
|
buffer0 <= 2'b00;
|
buffer1 <= 2'b00;
|
buffer1 <= 2'b00;
|
buffer2 <= 2'b00;
|
buffer2 <= 2'b00;
|
buffer3 <= 2'b00;
|
buffer3 <= 2'b00;
|
RxDataInTick <= 1'b0;
|
RxDataInTick <= 1'b0;
|
end
|
end
|
else begin
|
else begin
|
incBufferCnt <= 1'b0; //default value
|
incBufferCnt <= 1'b0; //default value
|
oldRxBitsIn <= RxBitsIn;
|
oldRxBitsIn <= RxBitsIn;
|
if (oldRxBitsIn != RxBitsIn) //if edge detected then
|
if (oldRxBitsIn != RxBitsIn) //if edge detected then
|
i <= 5'b00000; //reset the counter
|
i <= 5'b00000; //reset the counter
|
else
|
else
|
i <= i + 1'b1;
|
i <= i + 1'b1;
|
if ( (fullSpeedRate == 1'b1 && i[1:0] == 2'b10) || (fullSpeedRate == 1'b0 && i == 5'b10000) )
|
if ( (fullSpeedRate == 1'b1 && i[1:0] == 2'b10) || (fullSpeedRate == 1'b0 && i == 5'b10000) )
|
begin
|
begin
|
RxDataInTick <= !RxDataInTick;
|
RxDataInTick <= !RxDataInTick;
|
if (disableWireRead != 1'b1) //do not read wire data when transmitter is active
|
if (disableWireRead != 1'b1) //do not read wire data when transmitter is active
|
begin
|
begin
|
incBufferCnt <= 1'b1;
|
incBufferCnt <= 1'b1;
|
bufferInIndex <= bufferInIndex + 1'b1;
|
bufferInIndex <= bufferInIndex + 1'b1;
|
case (bufferInIndex)
|
case (bufferInIndex)
|
2'b00 : buffer0 <= RxBitsIn;
|
2'b00 : buffer0 <= RxBitsIn;
|
2'b01 : buffer1 <= RxBitsIn;
|
2'b01 : buffer1 <= RxBitsIn;
|
2'b10 : buffer2 <= RxBitsIn;
|
2'b10 : buffer2 <= RxBitsIn;
|
2'b11 : buffer3 <= RxBitsIn;
|
2'b11 : buffer3 <= RxBitsIn;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
//read from buffer, and output to SIEReceiver
|
//read from buffer, and output to SIEReceiver
|
always @(posedge clk) begin
|
always @(posedge clk) begin
|
if (rst == 1'b1)
|
if (rst == 1'b1)
|
begin
|
begin
|
decBufferCnt <= 1'b0;
|
decBufferCnt <= 1'b0;
|
bufferOutIndex <= 2'b00;
|
bufferOutIndex <= 2'b00;
|
RxBitsOut <= 2'b00;
|
RxBitsOut <= 2'b00;
|
SIERxWEn <= 1'b0;
|
SIERxWEn <= 1'b0;
|
bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
|
bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
|
end
|
end
|
else begin
|
else begin
|
case (bufferOutStMachCurrState)
|
case (bufferOutStMachCurrState)
|
`WAIT_BUFFER_NOT_EMPTY:
|
`WAIT_BUFFER_NOT_EMPTY:
|
begin
|
begin
|
if (bufferCnt != 3'b000)
|
if (bufferCnt != 3'b000)
|
bufferOutStMachCurrState <= `WAIT_SIE_RX_READY;
|
bufferOutStMachCurrState <= `WAIT_SIE_RX_READY;
|
end
|
end
|
`WAIT_SIE_RX_READY:
|
`WAIT_SIE_RX_READY:
|
begin
|
begin
|
if (SIERxRdyIn == 1'b1)
|
if (SIERxRdyIn == 1'b1)
|
begin
|
begin
|
SIERxWEn <= 1'b1;
|
SIERxWEn <= 1'b1;
|
bufferOutStMachCurrState <= `SIE_RX_WRITE;
|
bufferOutStMachCurrState <= `SIE_RX_WRITE;
|
decBufferCnt <= 1'b1;
|
decBufferCnt <= 1'b1;
|
bufferOutIndex <= bufferOutIndex + 1'b1;
|
bufferOutIndex <= bufferOutIndex + 1'b1;
|
case (bufferOutIndex)
|
case (bufferOutIndex)
|
2'b00 : RxBitsOut <= buffer0;
|
2'b00 : RxBitsOut <= buffer0;
|
2'b01 : RxBitsOut <= buffer1;
|
2'b01 : RxBitsOut <= buffer1;
|
2'b10 : RxBitsOut <= buffer2;
|
2'b10 : RxBitsOut <= buffer2;
|
2'b11 : RxBitsOut <= buffer3;
|
2'b11 : RxBitsOut <= buffer3;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
`SIE_RX_WRITE:
|
`SIE_RX_WRITE:
|
begin
|
begin
|
SIERxWEn <= 1'b0;
|
SIERxWEn <= 1'b0;
|
decBufferCnt <= 1'b0;
|
decBufferCnt <= 1'b0;
|
bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
|
bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
|
|
|
|
|
|