//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// readUSBWireData.v ////
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//// readUSBWireData.v ////
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//// ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// ////
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//// Module Description: ////
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//// Module Description: ////
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////
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////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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////
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////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// $Id: readUSBWireData.v,v 1.1.1.1 2004-10-11 04:01:01 sfielding Exp $
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// $Id: readUSBWireData.v,v 1.1.1.1 2004-10-11 04:01:01 sfielding Exp $
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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//
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//
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbSerialInterfaceEngine_h.v"
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module readUSBWireData (RxBitsIn, RxDataInTick, RxBitsOut, SIERxRdyIn, SIERxWEn, fullSpeedRate, disableWireRead, clk, rst);
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module readUSBWireData (RxBitsIn, RxDataInTick, RxBitsOut, SIERxRdyIn, SIERxWEn, fullSpeedRate, disableWireRead, clk, rst);
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input [1:0] RxBitsIn;
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input [1:0] RxBitsIn;
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output RxDataInTick;
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output RxDataInTick;
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input SIERxRdyIn;
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input SIERxRdyIn;
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input clk;
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input clk;
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input fullSpeedRate;
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input fullSpeedRate;
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input rst;
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input rst;
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input disableWireRead;
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input disableWireRead;
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output [1:0] RxBitsOut;
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output [1:0] RxBitsOut;
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output SIERxWEn;
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output SIERxWEn;
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wire [1:0] RxBitsIn;
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wire [1:0] RxBitsIn;
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reg RxDataInTick;
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reg RxDataInTick;
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wire SIERxRdyIn;
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wire SIERxRdyIn;
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wire clk;
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wire clk;
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wire fullSpeedRate;
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wire fullSpeedRate;
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wire rst;
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wire rst;
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reg [1:0] RxBitsOut;
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reg [1:0] RxBitsOut;
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reg SIERxWEn;
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reg SIERxWEn;
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// local registers
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// local registers
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reg [1:0]buffer0;
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reg [1:0]buffer0;
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reg [1:0]buffer1;
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reg [1:0]buffer1;
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reg [1:0]buffer2;
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reg [1:0]buffer2;
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reg [1:0]buffer3;
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reg [1:0]buffer3;
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reg [2:0]bufferCnt;
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reg [2:0]bufferCnt;
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reg [1:0]bufferInIndex;
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reg [1:0]bufferInIndex;
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reg [1:0]bufferOutIndex;
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reg [1:0]bufferOutIndex;
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reg decBufferCnt;
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reg decBufferCnt;
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reg [4:0]i;
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reg [4:0]i;
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reg incBufferCnt;
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reg incBufferCnt;
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reg [1:0]oldRxBitsIn;
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reg [1:0]oldRxBitsIn;
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// buffer output state machine state codes:
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// buffer output state machine state codes:
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`define WAIT_BUFFER_NOT_EMPTY 2'b00
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`define WAIT_BUFFER_NOT_EMPTY 2'b00
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`define WAIT_SIE_RX_READY 2'b01
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`define WAIT_SIE_RX_READY 2'b01
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`define SIE_RX_WRITE 2'b10
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`define SIE_RX_WRITE 2'b10
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reg [1:0] bufferOutStMachCurrState;
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reg [1:0] bufferOutStMachCurrState;
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (rst == 1'b1)
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if (rst == 1'b1)
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begin
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begin
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bufferCnt <= 3'b000;
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bufferCnt <= 3'b000;
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end
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end
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else begin
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else begin
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if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
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if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
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bufferCnt <= bufferCnt + 1'b1;
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bufferCnt <= bufferCnt + 1'b1;
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else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
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else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
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bufferCnt <= bufferCnt - 1'b1;
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bufferCnt <= bufferCnt - 1'b1;
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end
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end
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end
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end
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//Perform line rate clock recovery
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//Perform line rate clock recovery
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//Recover the wire data, and store data to buffer
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//Recover the wire data, and store data to buffer
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (rst == 1'b1)
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if (rst == 1'b1)
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begin
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begin
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i <= 5'b00000;
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i <= 5'b00000;
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incBufferCnt <= 1'b0;
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incBufferCnt <= 1'b0;
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bufferInIndex <= 2'b00;
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bufferInIndex <= 2'b00;
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buffer0 <= 2'b00;
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buffer0 <= 2'b00;
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buffer1 <= 2'b00;
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buffer1 <= 2'b00;
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buffer2 <= 2'b00;
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buffer2 <= 2'b00;
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buffer3 <= 2'b00;
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buffer3 <= 2'b00;
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RxDataInTick <= 1'b0;
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RxDataInTick <= 1'b0;
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end
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end
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else begin
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else begin
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incBufferCnt <= 1'b0; //default value
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incBufferCnt <= 1'b0; //default value
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oldRxBitsIn <= RxBitsIn;
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oldRxBitsIn <= RxBitsIn;
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if (oldRxBitsIn != RxBitsIn) //if edge detected then
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if (oldRxBitsIn != RxBitsIn) //if edge detected then
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i <= 5'b00000; //reset the counter
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i <= 5'b00000; //reset the counter
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else
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else
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i <= i + 1'b1;
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i <= i + 1'b1;
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if ( (fullSpeedRate == 1'b1 && i[1:0] == 2'b10) || (fullSpeedRate == 1'b0 && i == 5'b10000) )
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if ( (fullSpeedRate == 1'b1 && i[1:0] == 2'b10) || (fullSpeedRate == 1'b0 && i == 5'b10000) )
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begin
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begin
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RxDataInTick <= !RxDataInTick;
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RxDataInTick <= !RxDataInTick;
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if (disableWireRead != 1'b1) //do not read wire data when transmitter is active
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if (disableWireRead != 1'b1) //do not read wire data when transmitter is active
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begin
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begin
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incBufferCnt <= 1'b1;
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incBufferCnt <= 1'b1;
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bufferInIndex <= bufferInIndex + 1'b1;
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bufferInIndex <= bufferInIndex + 1'b1;
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case (bufferInIndex)
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case (bufferInIndex)
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2'b00 : buffer0 <= RxBitsIn;
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2'b00 : buffer0 <= RxBitsIn;
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2'b01 : buffer1 <= RxBitsIn;
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2'b01 : buffer1 <= RxBitsIn;
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2'b10 : buffer2 <= RxBitsIn;
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2'b10 : buffer2 <= RxBitsIn;
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2'b11 : buffer3 <= RxBitsIn;
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2'b11 : buffer3 <= RxBitsIn;
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endcase
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endcase
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end
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end
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end
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end
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end
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end
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end
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end
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//read from buffer, and output to SIEReceiver
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//read from buffer, and output to SIEReceiver
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (rst == 1'b1)
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if (rst == 1'b1)
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begin
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begin
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decBufferCnt <= 1'b0;
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decBufferCnt <= 1'b0;
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bufferOutIndex <= 2'b00;
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bufferOutIndex <= 2'b00;
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RxBitsOut <= 2'b00;
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RxBitsOut <= 2'b00;
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SIERxWEn <= 1'b0;
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SIERxWEn <= 1'b0;
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bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
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bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
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end
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end
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else begin
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else begin
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case (bufferOutStMachCurrState)
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case (bufferOutStMachCurrState)
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`WAIT_BUFFER_NOT_EMPTY:
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`WAIT_BUFFER_NOT_EMPTY:
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begin
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begin
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if (bufferCnt != 3'b000)
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if (bufferCnt != 3'b000)
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bufferOutStMachCurrState <= `WAIT_SIE_RX_READY;
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bufferOutStMachCurrState <= `WAIT_SIE_RX_READY;
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end
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end
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`WAIT_SIE_RX_READY:
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`WAIT_SIE_RX_READY:
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begin
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begin
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if (SIERxRdyIn == 1'b1)
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if (SIERxRdyIn == 1'b1)
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begin
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begin
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SIERxWEn <= 1'b1;
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SIERxWEn <= 1'b1;
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bufferOutStMachCurrState <= `SIE_RX_WRITE;
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bufferOutStMachCurrState <= `SIE_RX_WRITE;
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decBufferCnt <= 1'b1;
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decBufferCnt <= 1'b1;
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bufferOutIndex <= bufferOutIndex + 1'b1;
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bufferOutIndex <= bufferOutIndex + 1'b1;
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case (bufferOutIndex)
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case (bufferOutIndex)
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2'b00 : RxBitsOut <= buffer0;
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2'b00 : RxBitsOut <= buffer0;
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2'b01 : RxBitsOut <= buffer1;
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2'b01 : RxBitsOut <= buffer1;
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2'b10 : RxBitsOut <= buffer2;
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2'b10 : RxBitsOut <= buffer2;
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2'b11 : RxBitsOut <= buffer3;
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2'b11 : RxBitsOut <= buffer3;
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endcase
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endcase
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end
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end
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end
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end
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`SIE_RX_WRITE:
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`SIE_RX_WRITE:
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begin
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begin
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SIERxWEn <= 1'b0;
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SIERxWEn <= 1'b0;
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decBufferCnt <= 1'b0;
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decBufferCnt <= 1'b0;
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bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
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bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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