//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// USBHostControlBI.v ////
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//// USBHostControlBI.v ////
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//// ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// ////
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//// Module Description: ////
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//// Module Description: ////
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////
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////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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////
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////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// $Id: USBHostControlBI.v,v 1.2 2004-12-18 14:36:09 sfielding Exp $
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// $Id: USBHostControlBI.v,v 1.2 2004-12-18 14:36:09 sfielding Exp $
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1 2004/10/11 04:00:56 sfielding
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// Revision 1.1.1.1 2004/10/11 04:00:56 sfielding
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// Created
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// Created
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//
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//
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//
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//
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`include "usbHostControl_h.v"
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`include "usbHostControl_h.v"
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module USBHostControlBI (address, dataIn, dataOut, writeEn,
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module USBHostControlBI (address, dataIn, dataOut, writeEn,
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strobe_i,
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strobe_i,
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clk, rst,
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clk, rst,
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SOFSentIntOut, connEventIntOut, resumeIntOut, transDoneIntOut,
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SOFSentIntOut, connEventIntOut, resumeIntOut, transDoneIntOut,
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TxTransTypeReg, TxSOFEnableReg,
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TxTransTypeReg, TxSOFEnableReg,
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TxAddrReg, TxEndPReg, frameNumIn,
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TxAddrReg, TxEndPReg, frameNumIn,
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RxPktStatusIn, RxPIDIn,
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RxPktStatusIn, RxPIDIn,
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connectStateIn,
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connectStateIn,
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SOFSentIn, connEventIn, resumeIntIn, transDoneIn,
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SOFSentIn, connEventIn, resumeIntIn, transDoneIn,
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hostControlSelect,
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hostControlSelect,
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clrTransReq,
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clrTransReq,
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preambleEn,
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preambleEn,
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SOFSync,
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SOFSync,
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TxLineState,
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TxLineState,
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LineDirectControlEn,
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LineDirectControlEn,
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fullSpeedPol,
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fullSpeedPol,
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fullSpeedRate,
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fullSpeedRate,
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transReq
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transReq
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);
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);
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input [3:0] address;
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input [3:0] address;
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input [7:0] dataIn;
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input [7:0] dataIn;
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input writeEn;
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input writeEn;
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input strobe_i;
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input strobe_i;
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input clk;
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input clk;
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input rst;
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input rst;
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output [7:0] dataOut;
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output [7:0] dataOut;
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output SOFSentIntOut;
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output SOFSentIntOut;
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output connEventIntOut;
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output connEventIntOut;
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output resumeIntOut;
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output resumeIntOut;
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output transDoneIntOut;
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output transDoneIntOut;
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output [1:0] TxTransTypeReg;
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output [1:0] TxTransTypeReg;
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output TxSOFEnableReg;
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output TxSOFEnableReg;
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output [6:0] TxAddrReg;
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output [6:0] TxAddrReg;
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output [3:0] TxEndPReg;
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output [3:0] TxEndPReg;
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input [10:0] frameNumIn;
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input [10:0] frameNumIn;
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input [7:0] RxPktStatusIn;
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input [7:0] RxPktStatusIn;
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input [3:0] RxPIDIn;
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input [3:0] RxPIDIn;
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input [1:0] connectStateIn;
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input [1:0] connectStateIn;
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input SOFSentIn;
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input SOFSentIn;
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input connEventIn;
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input connEventIn;
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input resumeIntIn;
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input resumeIntIn;
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input transDoneIn;
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input transDoneIn;
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input hostControlSelect;
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input hostControlSelect;
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input clrTransReq;
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input clrTransReq;
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output preambleEn;
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output preambleEn;
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output SOFSync;
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output SOFSync;
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output [1:0] TxLineState;
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output [1:0] TxLineState;
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output LineDirectControlEn;
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output LineDirectControlEn;
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output fullSpeedPol;
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output fullSpeedPol;
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output fullSpeedRate;
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output fullSpeedRate;
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output transReq;
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output transReq;
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wire [3:0] address;
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wire [3:0] address;
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wire [7:0] dataIn;
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wire [7:0] dataIn;
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wire writeEn;
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wire writeEn;
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wire strobe_i;
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wire strobe_i;
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wire clk;
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wire clk;
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wire rst;
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wire rst;
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reg [7:0] dataOut;
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reg [7:0] dataOut;
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reg SOFSentIntOut;
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reg SOFSentIntOut;
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reg connEventIntOut;
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reg connEventIntOut;
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reg resumeIntOut;
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reg resumeIntOut;
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reg transDoneIntOut;
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reg transDoneIntOut;
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reg [1:0] TxTransTypeReg;
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reg [1:0] TxTransTypeReg;
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reg TxSOFEnableReg;
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reg TxSOFEnableReg;
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reg [6:0] TxAddrReg;
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reg [6:0] TxAddrReg;
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reg [3:0] TxEndPReg;
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reg [3:0] TxEndPReg;
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wire [10:0] frameNumIn;
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wire [10:0] frameNumIn;
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wire [7:0] RxPktStatusIn;
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wire [7:0] RxPktStatusIn;
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wire [3:0] RxPIDIn;
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wire [3:0] RxPIDIn;
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wire [1:0] connectStateIn;
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wire [1:0] connectStateIn;
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wire SOFSentIn;
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wire SOFSentIn;
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wire connEventIn;
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wire connEventIn;
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wire resumeIntIn;
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wire resumeIntIn;
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wire transDoneIn;
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wire transDoneIn;
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wire hostControlSelect;
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wire hostControlSelect;
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wire clrTransReq;
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wire clrTransReq;
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reg preambleEn;
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reg preambleEn;
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reg SOFSync;
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reg SOFSync;
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reg [1:0] TxLineState;
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reg [1:0] TxLineState;
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reg LineDirectControlEn;
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reg LineDirectControlEn;
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reg fullSpeedPol;
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reg fullSpeedPol;
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reg fullSpeedRate;
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reg fullSpeedRate;
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reg transReq;
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reg transReq;
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//internal wire and regs
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//internal wire and regs
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reg [1:0] TxControlReg;
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reg [1:0] TxControlReg;
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reg [4:0] TxLineControlReg;
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reg [4:0] TxLineControlReg;
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reg clrSOFReq;
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reg clrSOFReq;
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reg clrConnEvtReq;
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reg clrConnEvtReq;
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reg clrResInReq;
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reg clrResInReq;
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reg clrTransDoneReq;
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reg clrTransDoneReq;
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reg SOFSentInt;
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reg SOFSentInt;
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reg connEventInt;
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reg connEventInt;
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reg resumeInt;
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reg resumeInt;
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reg transDoneInt;
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reg transDoneInt;
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reg [3:0] interruptMaskReg;
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reg [3:0] interruptMaskReg;
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reg setTransReq;
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reg setTransReq;
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//sync write demux
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//sync write demux
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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clrSOFReq <= 1'b0;
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clrSOFReq <= 1'b0;
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clrConnEvtReq <= 1'b0;
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clrConnEvtReq <= 1'b0;
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clrResInReq <= 1'b0;
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clrResInReq <= 1'b0;
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clrTransDoneReq <= 1'b0;
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clrTransDoneReq <= 1'b0;
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setTransReq <= 1'b0;
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setTransReq <= 1'b0;
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if (writeEn == 1'b1 && strobe_i == 1'b1 && hostControlSelect == 1'b1)
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if (writeEn == 1'b1 && strobe_i == 1'b1 && hostControlSelect == 1'b1)
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begin
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begin
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case (address)
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case (address)
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`TX_CONTROL_REG : begin
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`TX_CONTROL_REG : begin
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preambleEn <= dataIn[2];
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preambleEn <= dataIn[2];
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SOFSync <= dataIn[1];
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SOFSync <= dataIn[1];
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setTransReq <= dataIn[0];
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setTransReq <= dataIn[0];
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end
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end
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`TX_TRANS_TYPE_REG : TxTransTypeReg <= dataIn[1:0];
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`TX_TRANS_TYPE_REG : TxTransTypeReg <= dataIn[1:0];
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`TX_LINE_CONTROL_REG : TxLineControlReg <= dataIn[4:0];
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`TX_LINE_CONTROL_REG : TxLineControlReg <= dataIn[4:0];
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`TX_SOF_ENABLE_REG : TxSOFEnableReg <= dataIn[0];
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`TX_SOF_ENABLE_REG : TxSOFEnableReg <= dataIn[0];
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`TX_ADDR_REG : TxAddrReg <= dataIn[6:0];
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`TX_ADDR_REG : TxAddrReg <= dataIn[6:0];
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`TX_ENDP_REG : TxEndPReg <= dataIn[3:0];
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`TX_ENDP_REG : TxEndPReg <= dataIn[3:0];
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`INTERRUPT_STATUS_REG : begin
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`INTERRUPT_STATUS_REG : begin
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clrSOFReq <= dataIn[3];
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clrSOFReq <= dataIn[3];
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clrConnEvtReq <= dataIn[2];
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clrConnEvtReq <= dataIn[2];
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clrResInReq <= dataIn[1];
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clrResInReq <= dataIn[1];
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clrTransDoneReq <= dataIn[0];
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clrTransDoneReq <= dataIn[0];
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end
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end
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`INTERRUPT_MASK_REG : interruptMaskReg <= dataIn[3:0];
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`INTERRUPT_MASK_REG : interruptMaskReg <= dataIn[3:0];
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endcase
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endcase
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end
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end
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end
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end
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//interrupt control
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//interrupt control
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if (SOFSentIn == 1'b1)
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if (SOFSentIn == 1'b1)
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SOFSentInt <= 1'b1;
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SOFSentInt <= 1'b1;
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else if (clrSOFReq == 1'b1)
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else if (clrSOFReq == 1'b1)
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SOFSentInt <= 1'b0;
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SOFSentInt <= 1'b0;
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if (connEventIn == 1'b1)
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if (connEventIn == 1'b1)
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connEventInt <= 1'b1;
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connEventInt <= 1'b1;
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else if (clrConnEvtReq == 1'b1)
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else if (clrConnEvtReq == 1'b1)
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connEventInt <= 1'b0;
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connEventInt <= 1'b0;
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if (resumeIntIn == 1'b1)
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if (resumeIntIn == 1'b1)
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resumeInt <= 1'b1;
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resumeInt <= 1'b1;
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else if (clrResInReq == 1'b1)
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else if (clrResInReq == 1'b1)
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resumeInt <= 1'b0;
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resumeInt <= 1'b0;
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if (transDoneIn == 1'b1)
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if (transDoneIn == 1'b1)
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transDoneInt <= 1'b1;
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transDoneInt <= 1'b1;
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else if (clrTransDoneReq == 1'b1)
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else if (clrTransDoneReq == 1'b1)
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transDoneInt <= 1'b0;
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transDoneInt <= 1'b0;
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end
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end
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//mask interrupts
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//mask interrupts
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always @(interruptMaskReg or transDoneInt or resumeInt or connEventInt or SOFSentInt) begin
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always @(interruptMaskReg or transDoneInt or resumeInt or connEventInt or SOFSentInt) begin
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transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
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transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
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resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
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resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
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connEventIntOut <= connEventInt & interruptMaskReg[`CONNECTION_EVENT_BIT];
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connEventIntOut <= connEventInt & interruptMaskReg[`CONNECTION_EVENT_BIT];
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SOFSentIntOut <= SOFSentInt & interruptMaskReg[`SOF_SENT_BIT];
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SOFSentIntOut <= SOFSentInt & interruptMaskReg[`SOF_SENT_BIT];
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end
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end
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//transaction request set/clear
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//transaction request set/clear
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if (setTransReq == 1'b1)
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if (setTransReq == 1'b1)
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transReq <= 1'b1;
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transReq <= 1'b1;
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else if (clrTransReq == 1'b1)
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else if (clrTransReq == 1'b1)
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transReq <= 1'b0;
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transReq <= 1'b0;
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end
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end
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//break out control signals
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//break out control signals
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always @(TxControlReg or TxLineControlReg) begin
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always @(TxControlReg or TxLineControlReg) begin
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TxLineState <= TxLineControlReg[`TX_LINE_STATE_MSBIT:`TX_LINE_STATE_LSBIT];
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TxLineState <= TxLineControlReg[`TX_LINE_STATE_MSBIT:`TX_LINE_STATE_LSBIT];
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LineDirectControlEn <= TxLineControlReg[`DIRECT_CONTROL_BIT];
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LineDirectControlEn <= TxLineControlReg[`DIRECT_CONTROL_BIT];
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fullSpeedPol <= TxLineControlReg[`FULL_SPEED_LINE_POLARITY_BIT];
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fullSpeedPol <= TxLineControlReg[`FULL_SPEED_LINE_POLARITY_BIT];
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fullSpeedRate <= TxLineControlReg[`FULL_SPEED_LINE_RATE_BIT];
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fullSpeedRate <= TxLineControlReg[`FULL_SPEED_LINE_RATE_BIT];
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end
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end
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// async read mux
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// async read mux
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always @(address or
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always @(address or
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TxControlReg or TxTransTypeReg or TxLineControlReg or TxSOFEnableReg or
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TxControlReg or TxTransTypeReg or TxLineControlReg or TxSOFEnableReg or
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TxAddrReg or TxEndPReg or frameNumIn or
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TxAddrReg or TxEndPReg or frameNumIn or
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SOFSentInt or connEventInt or resumeInt or transDoneInt or
|
SOFSentInt or connEventInt or resumeInt or transDoneInt or
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interruptMaskReg or RxPktStatusIn or RxPIDIn or connectStateIn or
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interruptMaskReg or RxPktStatusIn or RxPIDIn or connectStateIn or
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preambleEn or SOFSync or transReq)
|
preambleEn or SOFSync or transReq)
|
begin
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begin
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case (address)
|
case (address)
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`TX_CONTROL_REG : dataOut <= {5'b00000, preambleEn, SOFSync, transReq} ;
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`TX_CONTROL_REG : dataOut <= {5'b00000, preambleEn, SOFSync, transReq} ;
|
`TX_TRANS_TYPE_REG : dataOut <= {6'b000000, TxTransTypeReg};
|
`TX_TRANS_TYPE_REG : dataOut <= {6'b000000, TxTransTypeReg};
|
`TX_LINE_CONTROL_REG : dataOut <= {3'b000, TxLineControlReg};
|
`TX_LINE_CONTROL_REG : dataOut <= {3'b000, TxLineControlReg};
|
`TX_SOF_ENABLE_REG : dataOut <= {7'b0000000, TxSOFEnableReg};
|
`TX_SOF_ENABLE_REG : dataOut <= {7'b0000000, TxSOFEnableReg};
|
`TX_ADDR_REG : dataOut <= {1'b0, TxAddrReg};
|
`TX_ADDR_REG : dataOut <= {1'b0, TxAddrReg};
|
`TX_ENDP_REG : dataOut <= {4'h0, TxEndPReg};
|
`TX_ENDP_REG : dataOut <= {4'h0, TxEndPReg};
|
`FRAME_NUM_MSB_REG : dataOut <= frameNumIn[10:3];
|
`FRAME_NUM_MSB_REG : dataOut <= frameNumIn[10:3];
|
`FRAME_NUM_LSB_REG : dataOut <= {5'b00000, frameNumIn[2:0]};
|
`FRAME_NUM_LSB_REG : dataOut <= {5'b00000, frameNumIn[2:0]};
|
`INTERRUPT_STATUS_REG : dataOut <= {4'h0, SOFSentInt, connEventInt, resumeInt, transDoneInt};
|
`INTERRUPT_STATUS_REG : dataOut <= {4'h0, SOFSentInt, connEventInt, resumeInt, transDoneInt};
|
`INTERRUPT_MASK_REG : dataOut <= {4'h0, interruptMaskReg};
|
`INTERRUPT_MASK_REG : dataOut <= {4'h0, interruptMaskReg};
|
`RX_STATUS_REG : dataOut <= RxPktStatusIn;
|
`RX_STATUS_REG : dataOut <= RxPktStatusIn;
|
`RX_PID_REG : dataOut <= {4'b0000, RxPIDIn};
|
`RX_PID_REG : dataOut <= {4'b0000, RxPIDIn};
|
`RX_CONNECT_STATE_REG : dataOut <= {6'b000000, connectStateIn};
|
`RX_CONNECT_STATE_REG : dataOut <= {6'b000000, connectStateIn};
|
default: dataOut <= 8'h00;
|
default: dataOut <= 8'h00;
|
endcase
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endcase
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end
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end
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