//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// fifoRTL.v ////
|
//// fifoRTL.v ////
|
//// ////
|
//// ////
|
//// This file is part of the usbhostslave opencores effort.
|
//// This file is part of the usbhostslave opencores effort.
|
//// <http://www.opencores.org/cores//> ////
|
//// <http://www.opencores.org/cores//> ////
|
//// ////
|
//// ////
|
//// Module Description: ////
|
//// Module Description: ////
|
//// parameterized fifo. fifo depth is restricted to 2^ADDR_WIDTH
|
//// parameterized fifo. fifo depth is restricted to 2^ADDR_WIDTH
|
//// No protection against over runs and under runs.
|
//// No protection against over runs and under runs.
|
//// User must check full and empty flags before accessing fifo
|
//// User must check full and empty flags before accessing fifo
|
////
|
////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
////
|
////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Steve Fielding, sfielding@base2designs.com ////
|
//// - Steve Fielding, sfielding@base2designs.com ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
|
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from <http://www.opencores.org/lgpl.shtml> ////
|
//// from <http://www.opencores.org/lgpl.shtml> ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// $Id: fifoRTL.v,v 1.2 2004-12-18 14:36:06 sfielding Exp $
|
|
//
|
|
// CVS Revision History
|
|
//
|
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.1.1.1 2004/10/11 04:00:51 sfielding
|
|
// Created
|
|
//
|
|
//
|
|
|
|
`timescale 1ns / 1ps
|
`timescale 1ns / 1ps
|
|
|
module fifoRTL(clk, rst, dataIn, dataOut, fifoWEn, fifoREn, fifoFull, fifoEmpty, forceEmpty, numElementsInFifo);
|
module fifoRTL(clk, rst, dataIn, dataOut, fifoWEn, fifoREn, fifoFull, fifoEmpty, forceEmpty, numElementsInFifo);
|
//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536
|
//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536
|
parameter FIFO_WIDTH = 8;
|
parameter FIFO_WIDTH = 8;
|
parameter FIFO_DEPTH = 64;
|
parameter FIFO_DEPTH = 64;
|
parameter ADDR_WIDTH = 6;
|
parameter ADDR_WIDTH = 6;
|
|
|
input clk;
|
input clk;
|
input rst;
|
input rst;
|
input [FIFO_WIDTH-1:0] dataIn;
|
input [FIFO_WIDTH-1:0] dataIn;
|
output [FIFO_WIDTH-1:0] dataOut;
|
output [FIFO_WIDTH-1:0] dataOut;
|
input fifoWEn;
|
input fifoWEn;
|
input fifoREn;
|
input fifoREn;
|
output fifoFull;
|
output fifoFull;
|
output fifoEmpty;
|
output fifoEmpty;
|
input forceEmpty;
|
input forceEmpty;
|
output [15:0]numElementsInFifo; //note that this implies a max fifo depth of 65536
|
output [15:0]numElementsInFifo; //note that this implies a max fifo depth of 65536
|
|
|
wire clk;
|
wire clk;
|
wire rst;
|
wire rst;
|
wire [FIFO_WIDTH-1:0] dataIn;
|
wire [FIFO_WIDTH-1:0] dataIn;
|
reg [FIFO_WIDTH-1:0] dataOut;
|
reg [FIFO_WIDTH-1:0] dataOut;
|
wire fifoWEn;
|
wire fifoWEn;
|
wire fifoREn;
|
wire fifoREn;
|
reg fifoFull;
|
reg fifoFull;
|
reg fifoEmpty;
|
reg fifoEmpty;
|
wire forceEmpty;
|
wire forceEmpty;
|
reg [15:0]numElementsInFifo;
|
reg [15:0]numElementsInFifo;
|
|
|
|
|
// local registers
|
// local registers
|
reg [ADDR_WIDTH-1:0]bufferInIndex;
|
reg [ADDR_WIDTH-1:0]bufferInIndex;
|
reg [ADDR_WIDTH-1:0]bufferOutIndex;
|
reg [ADDR_WIDTH-1:0]bufferOutIndex;
|
reg [ADDR_WIDTH:0]bufferCnt;
|
reg [ADDR_WIDTH:0]bufferCnt;
|
reg fifoREnDelayed;
|
reg fifoREnDelayed;
|
wire [FIFO_WIDTH-1:0] dataFromMem;
|
wire [FIFO_WIDTH-1:0] dataFromMem;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
begin
|
begin
|
if (rst == 1'b1 || forceEmpty == 1'b1)
|
if (rst == 1'b1 || forceEmpty == 1'b1)
|
begin
|
begin
|
bufferCnt <= 0;
|
bufferCnt <= 0;
|
fifoFull <= 1'b0;
|
fifoFull <= 1'b0;
|
fifoEmpty <= 1'b1;
|
fifoEmpty <= 1'b1;
|
bufferInIndex <= 0;
|
bufferInIndex <= 0;
|
bufferOutIndex <= 0;
|
bufferOutIndex <= 0;
|
fifoREnDelayed <= 1'b0;
|
fifoREnDelayed <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
|
if (fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
|
dataOut <= dataFromMem;
|
dataOut <= dataFromMem;
|
end
|
end
|
fifoREnDelayed <= fifoREn;
|
fifoREnDelayed <= fifoREn;
|
if (fifoWEn == 1'b1 && fifoREn == 1'b0) begin
|
if (fifoWEn == 1'b1 && fifoREn == 1'b0) begin
|
bufferCnt <= bufferCnt + 1;
|
bufferCnt <= bufferCnt + 1;
|
bufferInIndex <= bufferInIndex + 1;
|
bufferInIndex <= bufferInIndex + 1;
|
end
|
end
|
else if (fifoWEn == 1'b0 && fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
|
else if (fifoWEn == 1'b0 && fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
|
bufferCnt <= bufferCnt - 1;
|
bufferCnt <= bufferCnt - 1;
|
bufferOutIndex <= bufferOutIndex + 1;
|
bufferOutIndex <= bufferOutIndex + 1;
|
end
|
end
|
else if (fifoWEn == 1'b1 && fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
|
else if (fifoWEn == 1'b1 && fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
|
bufferOutIndex <= bufferOutIndex + 1;
|
bufferOutIndex <= bufferOutIndex + 1;
|
bufferInIndex <= bufferInIndex + 1;
|
bufferInIndex <= bufferInIndex + 1;
|
end
|
end
|
if (bufferCnt[ADDR_WIDTH] == 1'b1)
|
if (bufferCnt[ADDR_WIDTH] == 1'b1)
|
fifoFull <= 1'b1;
|
fifoFull <= 1'b1;
|
else
|
else
|
fifoFull <= 1'b0;
|
fifoFull <= 1'b0;
|
if (|bufferCnt == 1'b0)
|
if (|bufferCnt == 1'b0)
|
fifoEmpty <= 1'b1;
|
fifoEmpty <= 1'b1;
|
else
|
else
|
fifoEmpty <= 1'b0;
|
fifoEmpty <= 1'b0;
|
end
|
end
|
end
|
end
|
|
|
//pad bufferCnt with leading zeroes
|
//pad bufferCnt with leading zeroes
|
always @(bufferCnt) begin
|
always @(bufferCnt) begin
|
numElementsInFifo <= { {16-ADDR_WIDTH+1{1'b0}}, bufferCnt };
|
numElementsInFifo <= { {16-ADDR_WIDTH+1{1'b0}}, bufferCnt };
|
end
|
end
|
|
|
fifoMem #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH) u_fifoMem (
|
fifoMem #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH) u_fifoMem (
|
.addrIn(bufferInIndex),
|
.addrIn(bufferInIndex),
|
.addrOut(bufferOutIndex),
|
.addrOut(bufferOutIndex),
|
.clk(clk),
|
.clk(clk),
|
.dataIn(dataIn),
|
.dataIn(dataIn),
|
.writeEn(fifoWEn),
|
.writeEn(fifoWEn),
|
.readEn(fifoREn),
|
.readEn(fifoREn),
|
.dataOut(dataFromMem));
|
.dataOut(dataFromMem));
|
|
|
|
|