//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// USBHostControlBI.v ////
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//// USBHostControlBI.v ////
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//// ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// ////
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//// Module Description: ////
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//// Module Description: ////
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////
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////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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////
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////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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`timescale 1ns / 1ps
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`include "timescale.v"
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`include "usbHostControl_h.v"
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`include "usbHostControl_h.v"
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module USBHostControlBI (address, dataIn, dataOut, writeEn,
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module USBHostControlBI (address, dataIn, dataOut, writeEn,
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strobe_i,
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strobe_i,
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busClk,
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busClk,
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rstSyncToBusClk,
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rstSyncToBusClk,
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usbClk,
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usbClk,
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rstSyncToUsbClk,
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rstSyncToUsbClk,
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SOFSentIntOut, connEventIntOut, resumeIntOut, transDoneIntOut,
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SOFSentIntOut, connEventIntOut, resumeIntOut, transDoneIntOut,
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TxTransTypeReg, TxSOFEnableReg,
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TxTransTypeReg, TxSOFEnableReg,
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TxAddrReg, TxEndPReg, frameNumIn,
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TxAddrReg, TxEndPReg, frameNumIn,
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RxPktStatusIn, RxPIDIn,
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RxPktStatusIn, RxPIDIn,
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connectStateIn,
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connectStateIn,
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SOFSentIn, connEventIn, resumeIntIn, transDoneIn,
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SOFSentIn, connEventIn, resumeIntIn, transDoneIn,
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hostControlSelect,
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hostControlSelect,
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clrTransReq,
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clrTransReq,
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preambleEn,
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preambleEn,
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SOFSync,
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SOFSync,
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TxLineState,
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TxLineState,
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LineDirectControlEn,
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LineDirectControlEn,
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fullSpeedPol,
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fullSpeedPol,
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fullSpeedRate,
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fullSpeedRate,
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transReq,
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transReq,
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isoEn,
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isoEn,
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SOFTimer
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SOFTimer
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);
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);
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input [3:0] address;
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input [3:0] address;
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input [7:0] dataIn;
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input [7:0] dataIn;
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input writeEn;
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input writeEn;
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input strobe_i;
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input strobe_i;
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input busClk;
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input busClk;
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input rstSyncToBusClk;
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input rstSyncToBusClk;
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input usbClk;
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input usbClk;
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input rstSyncToUsbClk;
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input rstSyncToUsbClk;
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output [7:0] dataOut;
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output [7:0] dataOut;
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output SOFSentIntOut;
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output SOFSentIntOut;
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output connEventIntOut;
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output connEventIntOut;
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output resumeIntOut;
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output resumeIntOut;
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output transDoneIntOut;
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output transDoneIntOut;
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output [1:0] TxTransTypeReg;
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output [1:0] TxTransTypeReg;
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output TxSOFEnableReg;
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output TxSOFEnableReg;
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output [6:0] TxAddrReg;
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output [6:0] TxAddrReg;
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output [3:0] TxEndPReg;
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output [3:0] TxEndPReg;
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input [10:0] frameNumIn;
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input [10:0] frameNumIn;
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input [7:0] RxPktStatusIn;
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input [7:0] RxPktStatusIn;
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input [3:0] RxPIDIn;
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input [3:0] RxPIDIn;
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input [1:0] connectStateIn;
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input [1:0] connectStateIn;
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input SOFSentIn;
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input SOFSentIn;
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input connEventIn;
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input connEventIn;
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input resumeIntIn;
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input resumeIntIn;
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input transDoneIn;
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input transDoneIn;
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input hostControlSelect;
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input hostControlSelect;
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input clrTransReq;
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input clrTransReq;
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output preambleEn;
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output preambleEn;
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output SOFSync;
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output SOFSync;
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output [1:0] TxLineState;
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output [1:0] TxLineState;
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output LineDirectControlEn;
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output LineDirectControlEn;
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output fullSpeedPol;
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output fullSpeedPol;
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output fullSpeedRate;
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output fullSpeedRate;
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output transReq;
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output transReq;
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output isoEn; //enable isochronous mode
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output isoEn; //enable isochronous mode
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input [15:0] SOFTimer;
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input [15:0] SOFTimer;
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wire [3:0] address;
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wire [3:0] address;
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wire [7:0] dataIn;
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wire [7:0] dataIn;
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wire writeEn;
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wire writeEn;
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wire strobe_i;
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wire strobe_i;
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wire busClk;
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wire busClk;
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wire rstSyncToBusClk;
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wire rstSyncToBusClk;
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wire usbClk;
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wire usbClk;
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wire rstSyncToUsbClk;
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wire rstSyncToUsbClk;
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reg [7:0] dataOut;
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reg [7:0] dataOut;
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reg SOFSentIntOut;
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reg SOFSentIntOut;
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reg connEventIntOut;
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reg connEventIntOut;
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reg resumeIntOut;
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reg resumeIntOut;
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reg transDoneIntOut;
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reg transDoneIntOut;
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reg [1:0] TxTransTypeReg;
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reg [1:0] TxTransTypeReg;
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reg TxSOFEnableReg;
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reg TxSOFEnableReg;
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reg [6:0] TxAddrReg;
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reg [6:0] TxAddrReg;
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reg [3:0] TxEndPReg;
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reg [3:0] TxEndPReg;
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wire [10:0] frameNumIn;
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wire [10:0] frameNumIn;
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wire [7:0] RxPktStatusIn;
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wire [7:0] RxPktStatusIn;
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wire [3:0] RxPIDIn;
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wire [3:0] RxPIDIn;
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wire [1:0] connectStateIn;
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wire [1:0] connectStateIn;
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wire SOFSentIn;
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wire SOFSentIn;
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wire connEventIn;
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wire connEventIn;
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wire resumeIntIn;
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wire resumeIntIn;
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wire transDoneIn;
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wire transDoneIn;
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wire hostControlSelect;
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wire hostControlSelect;
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wire clrTransReq;
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wire clrTransReq;
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reg preambleEn;
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reg preambleEn;
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reg SOFSync;
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reg SOFSync;
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reg [1:0] TxLineState;
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reg [1:0] TxLineState;
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reg LineDirectControlEn;
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reg LineDirectControlEn;
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reg fullSpeedPol;
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reg fullSpeedPol;
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reg fullSpeedRate;
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reg fullSpeedRate;
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reg transReq;
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reg transReq;
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reg isoEn;
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reg isoEn;
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wire [15:0] SOFTimer;
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wire [15:0] SOFTimer;
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//internal wire and regs
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//internal wire and regs
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reg [1:0] TxControlReg;
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reg [1:0] TxControlReg;
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reg [4:0] TxLineControlReg;
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reg [4:0] TxLineControlReg;
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reg clrSOFReq;
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reg clrSOFReq;
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reg clrConnEvtReq;
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reg clrConnEvtReq;
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reg clrResInReq;
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reg clrResInReq;
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reg clrTransDoneReq;
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reg clrTransDoneReq;
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reg SOFSentInt;
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reg SOFSentInt;
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reg connEventInt;
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reg connEventInt;
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reg resumeInt;
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reg resumeInt;
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reg transDoneInt;
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reg transDoneInt;
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reg [3:0] interruptMaskReg;
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reg [3:0] interruptMaskReg;
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reg setTransReq;
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reg setTransReq;
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//clock domain crossing sync registers
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//clock domain crossing sync registers
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//STB = Sync To Busclk
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//STB = Sync To Busclk
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reg [1:0] TxTransTypeRegSTB;
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reg [1:0] TxTransTypeRegSTB;
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reg TxSOFEnableRegSTB;
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reg TxSOFEnableRegSTB;
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reg [6:0] TxAddrRegSTB;
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reg [6:0] TxAddrRegSTB;
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reg [3:0] TxEndPRegSTB;
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reg [3:0] TxEndPRegSTB;
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reg preambleEnSTB;
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reg preambleEnSTB;
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reg SOFSyncSTB;
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reg SOFSyncSTB;
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reg [1:0] TxLineStateSTB;
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reg [1:0] TxLineStateSTB;
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reg LineDirectControlEnSTB;
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reg LineDirectControlEnSTB;
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reg fullSpeedPolSTB;
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reg fullSpeedPolSTB;
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reg fullSpeedRateSTB;
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reg fullSpeedRateSTB;
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reg transReqSTB;
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reg transReqSTB;
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reg isoEnSTB;
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reg isoEnSTB;
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reg [10:0] frameNumInSTB;
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reg [10:0] frameNumInSTB;
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reg [7:0] RxPktStatusInSTB;
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reg [7:0] RxPktStatusInSTB;
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reg [3:0] RxPIDInSTB;
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reg [3:0] RxPIDInSTB;
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reg [1:0] connectStateInSTB;
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reg [1:0] connectStateInSTB;
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reg SOFSentInSTB;
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reg SOFSentInSTB;
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reg connEventInSTB;
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reg connEventInSTB;
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reg resumeIntInSTB;
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reg resumeIntInSTB;
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reg transDoneInSTB;
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reg transDoneInSTB;
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reg clrTransReqSTB;
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reg clrTransReqSTB;
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reg [15:0] SOFTimerSTB;
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reg [15:0] SOFTimerSTB;
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//sync write demux
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//sync write demux
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always @(posedge busClk)
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always @(posedge busClk)
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begin
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begin
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if (rstSyncToBusClk == 1'b1) begin
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if (rstSyncToBusClk == 1'b1) begin
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isoEnSTB <= 1'b0;
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isoEnSTB <= 1'b0;
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preambleEnSTB <= 1'b0;
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preambleEnSTB <= 1'b0;
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SOFSyncSTB <= 1'b0;
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SOFSyncSTB <= 1'b0;
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TxTransTypeRegSTB <= 2'b00;
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TxTransTypeRegSTB <= 2'b00;
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TxLineControlReg <= 5'h00;
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TxLineControlReg <= 5'h00;
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TxSOFEnableRegSTB <= 1'b0;
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TxSOFEnableRegSTB <= 1'b0;
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TxAddrRegSTB <= 7'h00;
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TxAddrRegSTB <= 7'h00;
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TxEndPRegSTB <= 4'h0;
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TxEndPRegSTB <= 4'h0;
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interruptMaskReg <= 4'h0;
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interruptMaskReg <= 4'h0;
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end
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end
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else begin
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else begin
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clrSOFReq <= 1'b0;
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clrSOFReq <= 1'b0;
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clrConnEvtReq <= 1'b0;
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clrConnEvtReq <= 1'b0;
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clrResInReq <= 1'b0;
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clrResInReq <= 1'b0;
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clrTransDoneReq <= 1'b0;
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clrTransDoneReq <= 1'b0;
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setTransReq <= 1'b0;
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setTransReq <= 1'b0;
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if (writeEn == 1'b1 && strobe_i == 1'b1 && hostControlSelect == 1'b1)
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if (writeEn == 1'b1 && strobe_i == 1'b1 && hostControlSelect == 1'b1)
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begin
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begin
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case (address)
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case (address)
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`TX_CONTROL_REG : begin
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`TX_CONTROL_REG : begin
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isoEnSTB <= dataIn[`ISO_ENABLE_BIT];
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isoEnSTB <= dataIn[`ISO_ENABLE_BIT];
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preambleEnSTB <= dataIn[`PREAMBLE_ENABLE_BIT];
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preambleEnSTB <= dataIn[`PREAMBLE_ENABLE_BIT];
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SOFSyncSTB <= dataIn[`SOF_SYNC_BIT];
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SOFSyncSTB <= dataIn[`SOF_SYNC_BIT];
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setTransReq <= dataIn[`TRANS_REQ_BIT];
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setTransReq <= dataIn[`TRANS_REQ_BIT];
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end
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end
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`TX_TRANS_TYPE_REG : TxTransTypeRegSTB <= dataIn[1:0];
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`TX_TRANS_TYPE_REG : TxTransTypeRegSTB <= dataIn[1:0];
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`TX_LINE_CONTROL_REG : TxLineControlReg <= dataIn[4:0];
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`TX_LINE_CONTROL_REG : TxLineControlReg <= dataIn[4:0];
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`TX_SOF_ENABLE_REG : TxSOFEnableRegSTB <= dataIn[`SOF_EN_BIT];
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`TX_SOF_ENABLE_REG : TxSOFEnableRegSTB <= dataIn[`SOF_EN_BIT];
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`TX_ADDR_REG : TxAddrRegSTB <= dataIn[6:0];
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`TX_ADDR_REG : TxAddrRegSTB <= dataIn[6:0];
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`TX_ENDP_REG : TxEndPRegSTB <= dataIn[3:0];
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`TX_ENDP_REG : TxEndPRegSTB <= dataIn[3:0];
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`INTERRUPT_STATUS_REG : begin
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`INTERRUPT_STATUS_REG : begin
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clrSOFReq <= dataIn[`SOF_SENT_BIT];
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clrSOFReq <= dataIn[`SOF_SENT_BIT];
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clrConnEvtReq <= dataIn[`CONNECTION_EVENT_BIT];
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clrConnEvtReq <= dataIn[`CONNECTION_EVENT_BIT];
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clrResInReq <= dataIn[`RESUME_INT_BIT];
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clrResInReq <= dataIn[`RESUME_INT_BIT];
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clrTransDoneReq <= dataIn[`TRANS_DONE_BIT];
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clrTransDoneReq <= dataIn[`TRANS_DONE_BIT];
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end
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end
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`INTERRUPT_MASK_REG : interruptMaskReg <= dataIn[3:0];
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`INTERRUPT_MASK_REG : interruptMaskReg <= dataIn[3:0];
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endcase
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endcase
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end
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end
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end
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end
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end
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end
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//interrupt control
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//interrupt control
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always @(posedge busClk)
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always @(posedge busClk)
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begin
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begin
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if (rstSyncToBusClk == 1'b1) begin
|
if (rstSyncToBusClk == 1'b1) begin
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SOFSentInt <= 1'b0;
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SOFSentInt <= 1'b0;
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connEventInt <= 1'b0;
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connEventInt <= 1'b0;
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resumeInt <= 1'b0;
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resumeInt <= 1'b0;
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transDoneInt <= 1'b0;
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transDoneInt <= 1'b0;
|
end
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end
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else begin
|
else begin
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if (SOFSentInSTB == 1'b1)
|
if (SOFSentInSTB == 1'b1)
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SOFSentInt <= 1'b1;
|
SOFSentInt <= 1'b1;
|
else if (clrSOFReq == 1'b1)
|
else if (clrSOFReq == 1'b1)
|
SOFSentInt <= 1'b0;
|
SOFSentInt <= 1'b0;
|
|
|
if (connEventInSTB == 1'b1)
|
if (connEventInSTB == 1'b1)
|
connEventInt <= 1'b1;
|
connEventInt <= 1'b1;
|
else if (clrConnEvtReq == 1'b1)
|
else if (clrConnEvtReq == 1'b1)
|
connEventInt <= 1'b0;
|
connEventInt <= 1'b0;
|
|
|
if (resumeIntInSTB == 1'b1)
|
if (resumeIntInSTB == 1'b1)
|
resumeInt <= 1'b1;
|
resumeInt <= 1'b1;
|
else if (clrResInReq == 1'b1)
|
else if (clrResInReq == 1'b1)
|
resumeInt <= 1'b0;
|
resumeInt <= 1'b0;
|
|
|
if (transDoneInSTB == 1'b1)
|
if (transDoneInSTB == 1'b1)
|
transDoneInt <= 1'b1;
|
transDoneInt <= 1'b1;
|
else if (clrTransDoneReq == 1'b1)
|
else if (clrTransDoneReq == 1'b1)
|
transDoneInt <= 1'b0;
|
transDoneInt <= 1'b0;
|
end
|
end
|
end
|
end
|
|
|
//mask interrupts
|
//mask interrupts
|
always @(interruptMaskReg or transDoneInt or resumeInt or connEventInt or SOFSentInt) begin
|
always @(interruptMaskReg or transDoneInt or resumeInt or connEventInt or SOFSentInt) begin
|
transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
|
transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
|
resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
|
resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
|
connEventIntOut <= connEventInt & interruptMaskReg[`CONNECTION_EVENT_BIT];
|
connEventIntOut <= connEventInt & interruptMaskReg[`CONNECTION_EVENT_BIT];
|
SOFSentIntOut <= SOFSentInt & interruptMaskReg[`SOF_SENT_BIT];
|
SOFSentIntOut <= SOFSentInt & interruptMaskReg[`SOF_SENT_BIT];
|
end
|
end
|
|
|
//transaction request set/clear
|
//transaction request set/clear
|
//Since 'busClk' can be a higher freq than 'usbClk',
|
//Since 'busClk' can be a higher freq than 'usbClk',
|
//'setTransReq' must be delayed with respect to other control signals, thus
|
//'setTransReq' must be delayed with respect to other control signals, thus
|
//ensuring that control signals have been clocked through to 'usbClk' clock
|
//ensuring that control signals have been clocked through to 'usbClk' clock
|
//domain before the transaction request is asserted.
|
//domain before the transaction request is asserted.
|
//Not sure this is required because there is at least two 'usbClk' ticks between
|
//Not sure this is required because there is at least two 'usbClk' ticks between
|
//detection of 'transReq' and sampling of related control signals.always @(posedge busClk)
|
//detection of 'transReq' and sampling of related control signals.always @(posedge busClk)
|
always @(posedge busClk)
|
always @(posedge busClk)
|
begin
|
begin
|
if (rstSyncToBusClk == 1'b1) begin
|
if (rstSyncToBusClk == 1'b1) begin
|
transReqSTB <= 1'b0;
|
transReqSTB <= 1'b0;
|
end
|
end
|
else begin
|
else begin
|
if (setTransReq == 1'b1)
|
if (setTransReq == 1'b1)
|
transReqSTB <= 1'b1;
|
transReqSTB <= 1'b1;
|
else if (clrTransReqSTB == 1'b1)
|
else if (clrTransReqSTB == 1'b1)
|
transReqSTB <= 1'b0;
|
transReqSTB <= 1'b0;
|
end
|
end
|
end
|
end
|
|
|
//break out control signals
|
//break out control signals
|
always @(TxControlReg or TxLineControlReg) begin
|
always @(TxControlReg or TxLineControlReg) begin
|
TxLineStateSTB <= TxLineControlReg[`TX_LINE_STATE_MSBIT:`TX_LINE_STATE_LSBIT];
|
TxLineStateSTB <= TxLineControlReg[`TX_LINE_STATE_MSBIT:`TX_LINE_STATE_LSBIT];
|
LineDirectControlEnSTB <= TxLineControlReg[`DIRECT_CONTROL_BIT];
|
LineDirectControlEnSTB <= TxLineControlReg[`DIRECT_CONTROL_BIT];
|
fullSpeedPolSTB <= TxLineControlReg[`FULL_SPEED_LINE_POLARITY_BIT];
|
fullSpeedPolSTB <= TxLineControlReg[`FULL_SPEED_LINE_POLARITY_BIT];
|
fullSpeedRateSTB <= TxLineControlReg[`FULL_SPEED_LINE_RATE_BIT];
|
fullSpeedRateSTB <= TxLineControlReg[`FULL_SPEED_LINE_RATE_BIT];
|
end
|
end
|
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// async read mux
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// async read mux
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always @(address or
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always @(address or
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TxControlReg or TxTransTypeRegSTB or TxLineControlReg or TxSOFEnableRegSTB or
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TxControlReg or TxTransTypeRegSTB or TxLineControlReg or TxSOFEnableRegSTB or
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TxAddrRegSTB or TxEndPRegSTB or frameNumInSTB or
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TxAddrRegSTB or TxEndPRegSTB or frameNumInSTB or
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SOFSentInt or connEventInt or resumeInt or transDoneInt or
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SOFSentInt or connEventInt or resumeInt or transDoneInt or
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interruptMaskReg or RxPktStatusInSTB or RxPIDInSTB or connectStateInSTB or
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interruptMaskReg or RxPktStatusInSTB or RxPIDInSTB or connectStateInSTB or
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preambleEnSTB or SOFSyncSTB or transReqSTB or isoEnSTB or SOFTimer)
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preambleEnSTB or SOFSyncSTB or transReqSTB or isoEnSTB or SOFTimerSTB)
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begin
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begin
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case (address)
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case (address)
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`TX_CONTROL_REG : dataOut <= {4'b0000, isoEnSTB, preambleEnSTB, SOFSyncSTB, transReqSTB} ;
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`TX_CONTROL_REG : dataOut <= {4'b0000, isoEnSTB, preambleEnSTB, SOFSyncSTB, transReqSTB} ;
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`TX_TRANS_TYPE_REG : dataOut <= {6'b000000, TxTransTypeRegSTB};
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`TX_TRANS_TYPE_REG : dataOut <= {6'b000000, TxTransTypeRegSTB};
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`TX_LINE_CONTROL_REG : dataOut <= {3'b000, TxLineControlReg};
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`TX_LINE_CONTROL_REG : dataOut <= {3'b000, TxLineControlReg};
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`TX_SOF_ENABLE_REG : dataOut <= {7'b0000000, TxSOFEnableRegSTB};
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`TX_SOF_ENABLE_REG : dataOut <= {7'b0000000, TxSOFEnableRegSTB};
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`TX_ADDR_REG : dataOut <= {1'b0, TxAddrRegSTB};
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`TX_ADDR_REG : dataOut <= {1'b0, TxAddrRegSTB};
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`TX_ENDP_REG : dataOut <= {4'h0, TxEndPRegSTB};
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`TX_ENDP_REG : dataOut <= {4'h0, TxEndPRegSTB};
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`FRAME_NUM_MSB_REG : dataOut <= {5'b00000, frameNumInSTB[10:8]};
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`FRAME_NUM_MSB_REG : dataOut <= {5'b00000, frameNumInSTB[10:8]};
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`FRAME_NUM_LSB_REG : dataOut <= frameNumInSTB[7:0];
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`FRAME_NUM_LSB_REG : dataOut <= frameNumInSTB[7:0];
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`INTERRUPT_STATUS_REG : dataOut <= {4'h0, SOFSentInt, connEventInt, resumeInt, transDoneInt};
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`INTERRUPT_STATUS_REG : dataOut <= {4'h0, SOFSentInt, connEventInt, resumeInt, transDoneInt};
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`INTERRUPT_MASK_REG : dataOut <= {4'h0, interruptMaskReg};
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`INTERRUPT_MASK_REG : dataOut <= {4'h0, interruptMaskReg};
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`RX_STATUS_REG : dataOut <= RxPktStatusInSTB;
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`RX_STATUS_REG : dataOut <= RxPktStatusInSTB;
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`RX_PID_REG : dataOut <= {4'b0000, RxPIDInSTB};
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`RX_PID_REG : dataOut <= {4'b0000, RxPIDInSTB};
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`RX_CONNECT_STATE_REG : dataOut <= {6'b000000, connectStateInSTB};
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`RX_CONNECT_STATE_REG : dataOut <= {6'b000000, connectStateInSTB};
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`HOST_SOF_TIMER_MSB_REG : dataOut <= SOFTimer[15:8];
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`HOST_SOF_TIMER_MSB_REG : dataOut <= SOFTimerSTB[15:8];
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default: dataOut <= 8'h00;
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default: dataOut <= 8'h00;
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endcase
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endcase
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end
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end
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//re-sync from busClk to usbClk.
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//re-sync from busClk to usbClk.
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always @(posedge usbClk) begin
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always @(posedge usbClk) begin
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if (rstSyncToUsbClk == 1'b1) begin
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if (rstSyncToUsbClk == 1'b1) begin
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isoEn <= 1'b0;
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isoEn <= 1'b0;
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preambleEn <= 1'b0;
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preambleEn <= 1'b0;
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SOFSync <= 1'b0;
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SOFSync <= 1'b0;
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TxTransTypeReg <= 2'b00;
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TxTransTypeReg <= 2'b00;
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TxSOFEnableReg <= 1'b0;
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TxSOFEnableReg <= 1'b0;
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TxAddrReg <= 7'h00;
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TxAddrReg <= 7'h00;
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TxEndPReg <= 4'h0;
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TxEndPReg <= 4'h0;
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TxLineState <= 2'b00;
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TxLineState <= 2'b00;
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LineDirectControlEn <= 1'b0;
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LineDirectControlEn <= 1'b0;
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fullSpeedPol <= 1'b0;
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fullSpeedPol <= 1'b0;
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fullSpeedRate <= 1'b0;
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fullSpeedRate <= 1'b0;
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transReq <= 1'b0;
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transReq <= 1'b0;
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end
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end
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else begin
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else begin
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isoEn <= isoEnSTB;
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isoEn <= isoEnSTB;
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preambleEn <= preambleEnSTB;
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preambleEn <= preambleEnSTB;
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SOFSync <= SOFSyncSTB;
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SOFSync <= SOFSyncSTB;
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TxTransTypeReg <= TxTransTypeRegSTB;
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TxTransTypeReg <= TxTransTypeRegSTB;
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TxSOFEnableReg <= TxSOFEnableRegSTB;
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TxSOFEnableReg <= TxSOFEnableRegSTB;
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TxAddrReg <= TxAddrRegSTB;
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TxAddrReg <= TxAddrRegSTB;
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TxEndPReg <= TxEndPRegSTB;
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TxEndPReg <= TxEndPRegSTB;
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TxLineState <= TxLineStateSTB;
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TxLineState <= TxLineStateSTB;
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LineDirectControlEn <= LineDirectControlEnSTB;
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LineDirectControlEn <= LineDirectControlEnSTB;
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fullSpeedPol <= fullSpeedPolSTB;
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fullSpeedPol <= fullSpeedPolSTB;
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fullSpeedRate <= fullSpeedRateSTB;
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fullSpeedRate <= fullSpeedRateSTB;
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transReq <= transReqSTB;
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transReq <= transReqSTB;
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end
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end
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end
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end
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|
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//re-sync from usbClk to busClk. Since 'clrTransReq', 'transDoneIn' etc are only asserted
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//re-sync from usbClk to busClk. Since 'clrTransReq', 'transDoneIn' etc are only asserted
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//for one 'usbClk' tick, busClk freq must be greater than or equal to usbClk freq
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//for one 'usbClk' tick, busClk freq must be greater than or equal to usbClk freq
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always @(posedge busClk) begin
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always @(posedge busClk) begin
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frameNumInSTB <= frameNumIn;
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frameNumInSTB <= frameNumIn;
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RxPktStatusInSTB <= RxPktStatusIn;
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RxPktStatusInSTB <= RxPktStatusIn;
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RxPIDInSTB <= RxPIDIn;
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RxPIDInSTB <= RxPIDIn;
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connectStateInSTB <= connectStateIn;
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connectStateInSTB <= connectStateIn;
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SOFSentInSTB <= SOFSentIn;
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SOFSentInSTB <= SOFSentIn;
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connEventInSTB <= connEventIn;
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connEventInSTB <= connEventIn;
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resumeIntInSTB <= resumeIntIn;
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resumeIntInSTB <= resumeIntIn;
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transDoneInSTB <= transDoneIn;
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transDoneInSTB <= transDoneIn;
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clrTransReqSTB <= clrTransReq;
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clrTransReqSTB <= clrTransReq;
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//FIXME. It is not safe to pass 'SOFTimer' multi-bit signal between clock domains this way
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//All the other multi-bit signals will be static at the time that they are
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//read, but 'SOFTimer' will not be static.
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SOFTimerSTB <= SOFTimer;
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SOFTimerSTB <= SOFTimer;
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end
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end
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endmodule
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endmodule
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