//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// USBHostControlBI.v ////
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//// USBHostControlBI.v ////
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//// ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// ////
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//// Module Description: ////
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//// Module Description: ////
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////
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////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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////
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////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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`include "timescale.v"
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`include "timescale.v"
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`include "usbHostControl_h.v"
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`include "usbHostControl_h.v"
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module USBHostControlBI (address, dataIn, dataOut, writeEn,
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module USBHostControlBI (address, dataIn, dataOut, writeEn,
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strobe_i,
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strobe_i,
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busClk,
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busClk,
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rstSyncToBusClk,
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rstSyncToBusClk,
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usbClk,
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usbClk,
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rstSyncToUsbClk,
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rstSyncToUsbClk,
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SOFSentIntOut, connEventIntOut, resumeIntOut, transDoneIntOut,
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SOFSentIntOut, connEventIntOut, resumeIntOut, transDoneIntOut,
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TxTransTypeReg, TxSOFEnableReg,
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TxTransTypeReg, TxSOFEnableReg,
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TxAddrReg, TxEndPReg, frameNumIn,
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TxAddrReg, TxEndPReg, frameNumIn,
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RxPktStatusIn, RxPIDIn,
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RxPktStatusIn, RxPIDIn,
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connectStateIn,
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connectStateIn,
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SOFSentIn, connEventIn, resumeIntIn, transDoneIn,
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SOFSentIn, connEventIn, resumeIntIn, transDoneIn,
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hostControlSelect,
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hostControlSelect,
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clrTransReq,
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clrTransReq,
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preambleEn,
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preambleEn,
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SOFSync,
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SOFSync,
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TxLineState,
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TxLineState,
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LineDirectControlEn,
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LineDirectControlEn,
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fullSpeedPol,
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fullSpeedPol,
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fullSpeedRate,
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fullSpeedRate,
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transReq,
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transReq,
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isoEn,
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isoEn,
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SOFTimer
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SOFTimer
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);
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);
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input [3:0] address;
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input [3:0] address;
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input [7:0] dataIn;
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input [7:0] dataIn;
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input writeEn;
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input writeEn;
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input strobe_i;
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input strobe_i;
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input busClk;
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input busClk;
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input rstSyncToBusClk;
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input rstSyncToBusClk;
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input usbClk;
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input usbClk;
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input rstSyncToUsbClk;
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input rstSyncToUsbClk;
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output [7:0] dataOut;
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output [7:0] dataOut;
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output SOFSentIntOut;
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output SOFSentIntOut;
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output connEventIntOut;
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output connEventIntOut;
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output resumeIntOut;
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output resumeIntOut;
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output transDoneIntOut;
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output transDoneIntOut;
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|
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output [1:0] TxTransTypeReg;
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output [1:0] TxTransTypeReg;
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output TxSOFEnableReg;
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output TxSOFEnableReg;
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output [6:0] TxAddrReg;
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output [6:0] TxAddrReg;
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output [3:0] TxEndPReg;
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output [3:0] TxEndPReg;
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input [10:0] frameNumIn;
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input [10:0] frameNumIn;
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input [7:0] RxPktStatusIn;
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input [7:0] RxPktStatusIn;
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input [3:0] RxPIDIn;
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input [3:0] RxPIDIn;
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input [1:0] connectStateIn;
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input [1:0] connectStateIn;
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input SOFSentIn;
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input SOFSentIn;
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input connEventIn;
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input connEventIn;
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input resumeIntIn;
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input resumeIntIn;
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input transDoneIn;
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input transDoneIn;
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input hostControlSelect;
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input hostControlSelect;
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input clrTransReq;
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input clrTransReq;
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output preambleEn;
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output preambleEn;
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output SOFSync;
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output SOFSync;
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output [1:0] TxLineState;
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output [1:0] TxLineState;
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output LineDirectControlEn;
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output LineDirectControlEn;
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output fullSpeedPol;
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output fullSpeedPol;
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output fullSpeedRate;
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output fullSpeedRate;
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output transReq;
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output transReq;
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output isoEn; //enable isochronous mode
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output isoEn; //enable isochronous mode
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input [15:0] SOFTimer;
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input [15:0] SOFTimer;
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|
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wire [3:0] address;
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wire [3:0] address;
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wire [7:0] dataIn;
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wire [7:0] dataIn;
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wire writeEn;
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wire writeEn;
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wire strobe_i;
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wire strobe_i;
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wire busClk;
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wire busClk;
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wire rstSyncToBusClk;
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wire rstSyncToBusClk;
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wire usbClk;
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wire usbClk;
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wire rstSyncToUsbClk;
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wire rstSyncToUsbClk;
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reg [7:0] dataOut;
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reg [7:0] dataOut;
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|
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reg SOFSentIntOut;
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reg SOFSentIntOut;
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reg connEventIntOut;
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reg connEventIntOut;
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reg resumeIntOut;
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reg resumeIntOut;
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reg transDoneIntOut;
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reg transDoneIntOut;
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reg [1:0] TxTransTypeReg;
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reg [1:0] TxTransTypeReg;
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reg [1:0] TxTransTypeReg_reg1;
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reg [1:0] TxTransTypeReg_reg1;
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reg TxSOFEnableReg;
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reg TxSOFEnableReg;
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reg TxSOFEnableReg_reg1;
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reg TxSOFEnableReg_reg1;
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reg [6:0] TxAddrReg;
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reg [6:0] TxAddrReg;
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reg [6:0] TxAddrReg_reg1;
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reg [6:0] TxAddrReg_reg1;
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reg [3:0] TxEndPReg;
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reg [3:0] TxEndPReg;
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reg [3:0] TxEndPReg_reg1;
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reg [3:0] TxEndPReg_reg1;
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wire [10:0] frameNumIn;
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wire [10:0] frameNumIn;
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wire [7:0] RxPktStatusIn;
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wire [7:0] RxPktStatusIn;
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wire [3:0] RxPIDIn;
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wire [3:0] RxPIDIn;
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wire [1:0] connectStateIn;
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wire [1:0] connectStateIn;
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wire SOFSentIn;
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wire SOFSentIn;
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wire connEventIn;
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wire connEventIn;
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wire resumeIntIn;
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wire resumeIntIn;
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wire transDoneIn;
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wire transDoneIn;
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wire hostControlSelect;
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wire hostControlSelect;
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wire clrTransReq;
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wire clrTransReq;
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reg preambleEn;
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reg preambleEn;
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reg preambleEn_reg1;
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reg preambleEn_reg1;
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reg SOFSync;
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reg SOFSync;
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reg SOFSync_reg1;
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reg SOFSync_reg1;
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reg [1:0] TxLineState;
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reg [1:0] TxLineState;
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reg [1:0] TxLineState_reg1;
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reg [1:0] TxLineState_reg1;
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reg LineDirectControlEn;
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reg LineDirectControlEn;
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reg LineDirectControlEn_reg1;
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reg LineDirectControlEn_reg1;
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reg fullSpeedPol;
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reg fullSpeedPol;
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reg fullSpeedPol_reg1;
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reg fullSpeedPol_reg1;
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reg fullSpeedRate;
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reg fullSpeedRate;
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reg fullSpeedRate_reg1;
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reg fullSpeedRate_reg1;
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reg transReq;
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reg transReq;
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reg transReq_reg1;
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reg transReq_reg1;
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reg isoEn;
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reg isoEn;
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reg isoEn_reg1;
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reg isoEn_reg1;
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wire [15:0] SOFTimer;
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wire [15:0] SOFTimer;
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//internal wire and regs
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//internal wire and regs
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reg [1:0] TxControlReg;
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reg [1:0] TxControlReg;
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reg [4:0] TxLineControlReg;
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reg [4:0] TxLineControlReg;
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reg clrSOFReq;
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reg clrSOFReq;
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reg clrConnEvtReq;
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reg clrConnEvtReq;
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reg clrResInReq;
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reg clrResInReq;
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reg clrTransDoneReq;
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reg clrTransDoneReq;
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reg SOFSentInt;
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reg SOFSentInt;
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reg connEventInt;
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reg connEventInt;
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reg resumeInt;
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reg resumeInt;
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reg transDoneInt;
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reg transDoneInt;
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reg [3:0] interruptMaskReg;
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reg [3:0] interruptMaskReg;
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reg setTransReq;
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reg setTransReq;
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reg [2:0] resumeIntInExtend;
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reg [2:0] resumeIntInExtend;
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reg [2:0] transDoneInExtend;
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reg [2:0] transDoneInExtend;
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reg [2:0] connEventInExtend;
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reg [2:0] connEventInExtend;
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reg [2:0] SOFSentInExtend;
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reg [2:0] SOFSentInExtend;
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reg [2:0] clrTransReqExtend;
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reg [2:0] clrTransReqExtend;
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//clock domain crossing sync registers
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//clock domain crossing sync registers
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//STB = Sync To Busclk
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//STB = Sync To Busclk
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reg [1:0] TxTransTypeRegSTB;
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reg [1:0] TxTransTypeRegSTB;
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reg TxSOFEnableRegSTB;
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reg TxSOFEnableRegSTB;
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reg [6:0] TxAddrRegSTB;
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reg [6:0] TxAddrRegSTB;
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reg [3:0] TxEndPRegSTB;
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reg [3:0] TxEndPRegSTB;
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reg preambleEnSTB;
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reg preambleEnSTB;
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reg SOFSyncSTB;
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reg SOFSyncSTB;
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reg [1:0] TxLineStateSTB;
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reg [1:0] TxLineStateSTB;
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reg LineDirectControlEnSTB;
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reg LineDirectControlEnSTB;
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reg fullSpeedPolSTB;
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reg fullSpeedPolSTB;
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reg fullSpeedRateSTB;
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reg fullSpeedRateSTB;
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reg transReqSTB;
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reg transReqSTB;
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reg isoEnSTB;
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reg isoEnSTB;
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reg [10:0] frameNumInSTB;
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reg [10:0] frameNumInSTB;
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reg [10:0] frameNumInSTB_reg1;
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reg [10:0] frameNumInSTB_reg1;
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reg [7:0] RxPktStatusInSTB;
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reg [7:0] RxPktStatusInSTB;
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reg [7:0] RxPktStatusInSTB_reg1;
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reg [7:0] RxPktStatusInSTB_reg1;
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reg [3:0] RxPIDInSTB;
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reg [3:0] RxPIDInSTB;
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reg [3:0] RxPIDInSTB_reg1;
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reg [3:0] RxPIDInSTB_reg1;
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reg [1:0] connectStateInSTB;
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reg [1:0] connectStateInSTB;
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reg [1:0] connectStateInSTB_reg1;
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reg [1:0] connectStateInSTB_reg1;
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reg [2:0] SOFSentInSTB;
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reg [2:0] SOFSentInSTB;
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reg [2:0] connEventInSTB;
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reg [2:0] connEventInSTB;
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reg [2:0] resumeIntInSTB;
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reg [2:0] resumeIntInSTB;
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reg [2:0] transDoneInSTB;
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reg [2:0] transDoneInSTB;
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reg [2:0] clrTransReqSTB;
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reg [2:0] clrTransReqSTB;
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reg [15:0] SOFTimerSTB;
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reg [15:0] SOFTimerSTB;
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reg [15:0] SOFTimerSTB_reg1;
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reg [15:0] SOFTimerSTB_reg1;
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//sync write demux
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//sync write demux
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always @(posedge busClk)
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always @(posedge busClk)
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begin
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begin
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if (rstSyncToBusClk == 1'b1) begin
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if (rstSyncToBusClk == 1'b1) begin
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isoEnSTB <= 1'b0;
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isoEnSTB <= 1'b0;
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preambleEnSTB <= 1'b0;
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preambleEnSTB <= 1'b0;
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SOFSyncSTB <= 1'b0;
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SOFSyncSTB <= 1'b0;
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TxTransTypeRegSTB <= 2'b00;
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TxTransTypeRegSTB <= 2'b00;
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TxLineControlReg <= 5'h00;
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TxLineControlReg <= 5'h00;
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TxSOFEnableRegSTB <= 1'b0;
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TxSOFEnableRegSTB <= 1'b0;
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TxAddrRegSTB <= 7'h00;
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TxAddrRegSTB <= 7'h00;
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TxEndPRegSTB <= 4'h0;
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TxEndPRegSTB <= 4'h0;
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interruptMaskReg <= 4'h0;
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interruptMaskReg <= 4'h0;
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end
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end
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else begin
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else begin
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clrSOFReq <= 1'b0;
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clrSOFReq <= 1'b0;
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clrConnEvtReq <= 1'b0;
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clrConnEvtReq <= 1'b0;
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clrResInReq <= 1'b0;
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clrResInReq <= 1'b0;
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clrTransDoneReq <= 1'b0;
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clrTransDoneReq <= 1'b0;
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setTransReq <= 1'b0;
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setTransReq <= 1'b0;
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if (writeEn == 1'b1 && strobe_i == 1'b1 && hostControlSelect == 1'b1)
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if (writeEn == 1'b1 && strobe_i == 1'b1 && hostControlSelect == 1'b1)
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begin
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begin
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case (address)
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case (address)
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`TX_CONTROL_REG : begin
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`TX_CONTROL_REG : begin
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isoEnSTB <= dataIn[`ISO_ENABLE_BIT];
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isoEnSTB <= dataIn[`ISO_ENABLE_BIT];
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preambleEnSTB <= dataIn[`PREAMBLE_ENABLE_BIT];
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preambleEnSTB <= dataIn[`PREAMBLE_ENABLE_BIT];
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SOFSyncSTB <= dataIn[`SOF_SYNC_BIT];
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SOFSyncSTB <= dataIn[`SOF_SYNC_BIT];
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setTransReq <= dataIn[`TRANS_REQ_BIT];
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setTransReq <= dataIn[`TRANS_REQ_BIT];
|
end
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end
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`TX_TRANS_TYPE_REG : TxTransTypeRegSTB <= dataIn[1:0];
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`TX_TRANS_TYPE_REG : TxTransTypeRegSTB <= dataIn[1:0];
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`TX_LINE_CONTROL_REG : TxLineControlReg <= dataIn[4:0];
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`TX_LINE_CONTROL_REG : TxLineControlReg <= dataIn[4:0];
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`TX_SOF_ENABLE_REG : TxSOFEnableRegSTB <= dataIn[`SOF_EN_BIT];
|
`TX_SOF_ENABLE_REG : TxSOFEnableRegSTB <= dataIn[`SOF_EN_BIT];
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`TX_ADDR_REG : TxAddrRegSTB <= dataIn[6:0];
|
`TX_ADDR_REG : TxAddrRegSTB <= dataIn[6:0];
|
`TX_ENDP_REG : TxEndPRegSTB <= dataIn[3:0];
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`TX_ENDP_REG : TxEndPRegSTB <= dataIn[3:0];
|
`INTERRUPT_STATUS_REG : begin
|
`INTERRUPT_STATUS_REG : begin
|
clrSOFReq <= dataIn[`SOF_SENT_BIT];
|
clrSOFReq <= dataIn[`SOF_SENT_BIT];
|
clrConnEvtReq <= dataIn[`CONNECTION_EVENT_BIT];
|
clrConnEvtReq <= dataIn[`CONNECTION_EVENT_BIT];
|
clrResInReq <= dataIn[`RESUME_INT_BIT];
|
clrResInReq <= dataIn[`RESUME_INT_BIT];
|
clrTransDoneReq <= dataIn[`TRANS_DONE_BIT];
|
clrTransDoneReq <= dataIn[`TRANS_DONE_BIT];
|
end
|
end
|
`INTERRUPT_MASK_REG : interruptMaskReg <= dataIn[3:0];
|
`INTERRUPT_MASK_REG : interruptMaskReg <= dataIn[3:0];
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
//interrupt control
|
//interrupt control
|
always @(posedge busClk)
|
always @(posedge busClk)
|
begin
|
begin
|
if (rstSyncToBusClk == 1'b1) begin
|
if (rstSyncToBusClk == 1'b1) begin
|
SOFSentInt <= 1'b0;
|
SOFSentInt <= 1'b0;
|
connEventInt <= 1'b0;
|
connEventInt <= 1'b0;
|
resumeInt <= 1'b0;
|
resumeInt <= 1'b0;
|
transDoneInt <= 1'b0;
|
transDoneInt <= 1'b0;
|
end
|
end
|
else begin
|
else begin
|
if (SOFSentInSTB[1] == 1'b1 && SOFSentInSTB[0] == 1'b0)
|
if (SOFSentInSTB[1] == 1'b1 && SOFSentInSTB[0] == 1'b0)
|
SOFSentInt <= 1'b1;
|
SOFSentInt <= 1'b1;
|
else if (clrSOFReq == 1'b1)
|
else if (clrSOFReq == 1'b1)
|
SOFSentInt <= 1'b0;
|
SOFSentInt <= 1'b0;
|
|
|
if (connEventInSTB[1] == 1'b1 && connEventInSTB[0] == 1'b0)
|
if (connEventInSTB[1] == 1'b1 && connEventInSTB[0] == 1'b0)
|
connEventInt <= 1'b1;
|
connEventInt <= 1'b1;
|
else if (clrConnEvtReq == 1'b1)
|
else if (clrConnEvtReq == 1'b1)
|
connEventInt <= 1'b0;
|
connEventInt <= 1'b0;
|
|
|
if (resumeIntInSTB[1] == 1'b1 && resumeIntInSTB[0] == 1'b0)
|
if (resumeIntInSTB[1] == 1'b1 && resumeIntInSTB[0] == 1'b0)
|
resumeInt <= 1'b1;
|
resumeInt <= 1'b1;
|
else if (clrResInReq == 1'b1)
|
else if (clrResInReq == 1'b1)
|
resumeInt <= 1'b0;
|
resumeInt <= 1'b0;
|
|
|
if (transDoneInSTB[1] == 1'b1 && transDoneInSTB[0] == 1'b0)
|
if (transDoneInSTB[1] == 1'b1 && transDoneInSTB[0] == 1'b0)
|
transDoneInt <= 1'b1;
|
transDoneInt <= 1'b1;
|
else if (clrTransDoneReq == 1'b1)
|
else if (clrTransDoneReq == 1'b1)
|
transDoneInt <= 1'b0;
|
transDoneInt <= 1'b0;
|
end
|
end
|
end
|
end
|
|
|
//mask interrupts
|
//mask interrupts
|
always @(*) begin
|
always @(*) begin
|
transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
|
transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
|
resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
|
resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
|
connEventIntOut <= connEventInt & interruptMaskReg[`CONNECTION_EVENT_BIT];
|
connEventIntOut <= connEventInt & interruptMaskReg[`CONNECTION_EVENT_BIT];
|
SOFSentIntOut <= SOFSentInt & interruptMaskReg[`SOF_SENT_BIT];
|
SOFSentIntOut <= SOFSentInt & interruptMaskReg[`SOF_SENT_BIT];
|
end
|
end
|
|
|
//transaction request set/clear
|
//transaction request set/clear
|
//Since 'busClk' can be a higher freq than 'usbClk',
|
//Since 'busClk' can be a higher freq than 'usbClk',
|
//'setTransReq' must be delayed with respect to other control signals, thus
|
//'setTransReq' must be delayed with respect to other control signals, thus
|
//ensuring that control signals have been clocked through to 'usbClk' clock
|
//ensuring that control signals have been clocked through to 'usbClk' clock
|
//domain before the transaction request is asserted.
|
//domain before the transaction request is asserted.
|
//Not sure this is required because there is at least two 'usbClk' ticks between
|
//Not sure this is required because there is at least two 'usbClk' ticks between
|
//detection of 'transReq' and sampling of related control signals.
|
//detection of 'transReq' and sampling of related control signals.
|
always @(posedge busClk)
|
always @(posedge busClk)
|
begin
|
begin
|
if (rstSyncToBusClk == 1'b1) begin
|
if (rstSyncToBusClk == 1'b1) begin
|
transReqSTB <= 1'b0;
|
transReqSTB <= 1'b0;
|
end
|
end
|
else begin
|
else begin
|
if (setTransReq == 1'b1)
|
if (setTransReq == 1'b1)
|
transReqSTB <= 1'b1;
|
transReqSTB <= 1'b1;
|
else if (clrTransReqSTB[1] == 1'b1 && clrTransReqSTB[0] == 1'b0)
|
else if (clrTransReqSTB[1] == 1'b1 && clrTransReqSTB[0] == 1'b0)
|
transReqSTB <= 1'b0;
|
transReqSTB <= 1'b0;
|
end
|
end
|
end
|
end
|
|
|
//break out control signals
|
//break out control signals
|
always @(*) begin
|
always @(*) begin
|
TxLineStateSTB <= TxLineControlReg[`TX_LINE_STATE_MSBIT:`TX_LINE_STATE_LSBIT];
|
TxLineStateSTB <= TxLineControlReg[`TX_LINE_STATE_MSBIT:`TX_LINE_STATE_LSBIT];
|
LineDirectControlEnSTB <= TxLineControlReg[`DIRECT_CONTROL_BIT];
|
LineDirectControlEnSTB <= TxLineControlReg[`DIRECT_CONTROL_BIT];
|
fullSpeedPolSTB <= TxLineControlReg[`FULL_SPEED_LINE_POLARITY_BIT];
|
fullSpeedPolSTB <= TxLineControlReg[`FULL_SPEED_LINE_POLARITY_BIT];
|
fullSpeedRateSTB <= TxLineControlReg[`FULL_SPEED_LINE_RATE_BIT];
|
fullSpeedRateSTB <= TxLineControlReg[`FULL_SPEED_LINE_RATE_BIT];
|
end
|
end
|
|
|
// async read mux
|
// async read mux
|
always @(*)
|
always @(*)
|
begin
|
begin
|
case (address)
|
case (address)
|
`TX_CONTROL_REG : dataOut <= {4'b0000, isoEnSTB, preambleEnSTB, SOFSyncSTB, transReqSTB} ;
|
`TX_CONTROL_REG : dataOut <= {4'b0000, isoEnSTB, preambleEnSTB, SOFSyncSTB, transReqSTB} ;
|
`TX_TRANS_TYPE_REG : dataOut <= {6'b000000, TxTransTypeRegSTB};
|
`TX_TRANS_TYPE_REG : dataOut <= {6'b000000, TxTransTypeRegSTB};
|
`TX_LINE_CONTROL_REG : dataOut <= {3'b000, TxLineControlReg};
|
`TX_LINE_CONTROL_REG : dataOut <= {3'b000, TxLineControlReg};
|
`TX_SOF_ENABLE_REG : dataOut <= {7'b0000000, TxSOFEnableRegSTB};
|
`TX_SOF_ENABLE_REG : dataOut <= {7'b0000000, TxSOFEnableRegSTB};
|
`TX_ADDR_REG : dataOut <= {1'b0, TxAddrRegSTB};
|
`TX_ADDR_REG : dataOut <= {1'b0, TxAddrRegSTB};
|
`TX_ENDP_REG : dataOut <= {4'h0, TxEndPRegSTB};
|
`TX_ENDP_REG : dataOut <= {4'h0, TxEndPRegSTB};
|
`FRAME_NUM_MSB_REG : dataOut <= {5'b00000, frameNumInSTB[10:8]};
|
`FRAME_NUM_MSB_REG : dataOut <= {5'b00000, frameNumInSTB[10:8]};
|
`FRAME_NUM_LSB_REG : dataOut <= frameNumInSTB[7:0];
|
`FRAME_NUM_LSB_REG : dataOut <= frameNumInSTB[7:0];
|
`INTERRUPT_STATUS_REG : dataOut <= {4'h0, SOFSentInt, connEventInt, resumeInt, transDoneInt};
|
`INTERRUPT_STATUS_REG : dataOut <= {4'h0, SOFSentInt, connEventInt, resumeInt, transDoneInt};
|
`INTERRUPT_MASK_REG : dataOut <= {4'h0, interruptMaskReg};
|
`INTERRUPT_MASK_REG : dataOut <= {4'h0, interruptMaskReg};
|
`RX_STATUS_REG : dataOut <= RxPktStatusInSTB;
|
`RX_STATUS_REG : dataOut <= RxPktStatusInSTB;
|
`RX_PID_REG : dataOut <= {4'b0000, RxPIDInSTB};
|
`RX_PID_REG : dataOut <= {4'b0000, RxPIDInSTB};
|
`RX_CONNECT_STATE_REG : dataOut <= {6'b000000, connectStateInSTB};
|
`RX_CONNECT_STATE_REG : dataOut <= {6'b000000, connectStateInSTB};
|
`HOST_SOF_TIMER_MSB_REG : dataOut <= SOFTimerSTB[15:8];
|
`HOST_SOF_TIMER_MSB_REG : dataOut <= SOFTimerSTB[15:8];
|
default: dataOut <= 8'h00;
|
default: dataOut <= 8'h00;
|
endcase
|
endcase
|
end
|
end
|
|
|
//re-sync from busClk to usbClk.
|
//re-sync from busClk to usbClk.
|
always @(posedge usbClk) begin
|
always @(posedge usbClk) begin
|
if (rstSyncToUsbClk == 1'b1) begin
|
if (rstSyncToUsbClk == 1'b1) begin
|
isoEn <= 1'b0;
|
isoEn <= 1'b0;
|
isoEn_reg1 <= 1'b0;
|
isoEn_reg1 <= 1'b0;
|
preambleEn <= 1'b0;
|
preambleEn <= 1'b0;
|
preambleEn_reg1 <= 1'b0;
|
preambleEn_reg1 <= 1'b0;
|
SOFSync <= 1'b0;
|
SOFSync <= 1'b0;
|
SOFSync_reg1 <= 1'b0;
|
SOFSync_reg1 <= 1'b0;
|
TxTransTypeReg <= 2'b00;
|
TxTransTypeReg <= 2'b00;
|
TxTransTypeReg_reg1 <= 2'b00;
|
TxTransTypeReg_reg1 <= 2'b00;
|
TxSOFEnableReg <= 1'b0;
|
TxSOFEnableReg <= 1'b0;
|
TxSOFEnableReg_reg1 <= 1'b0;
|
TxSOFEnableReg_reg1 <= 1'b0;
|
TxAddrReg <= {7{1'b0}};
|
TxAddrReg <= {7{1'b0}};
|
TxAddrReg_reg1 <= {7{1'b0}};
|
TxAddrReg_reg1 <= {7{1'b0}};
|
TxEndPReg <= 4'h0;
|
TxEndPReg <= 4'h0;
|
TxEndPReg_reg1 <= 4'h0;
|
TxEndPReg_reg1 <= 4'h0;
|
TxLineState <= 2'b00;
|
TxLineState <= 2'b00;
|
TxLineState_reg1 <= 2'b00;
|
TxLineState_reg1 <= 2'b00;
|
LineDirectControlEn <= 1'b0;
|
LineDirectControlEn <= 1'b0;
|
LineDirectControlEn_reg1 <= 1'b0;
|
LineDirectControlEn_reg1 <= 1'b0;
|
fullSpeedPol <= 1'b0;
|
fullSpeedPol <= 1'b0;
|
fullSpeedPol_reg1 <= 1'b0;
|
fullSpeedPol_reg1 <= 1'b0;
|
fullSpeedRate <= 1'b0;
|
fullSpeedRate <= 1'b0;
|
fullSpeedRate_reg1 <= 1'b0;
|
fullSpeedRate_reg1 <= 1'b0;
|
transReq <= 1'b0;
|
transReq <= 1'b0;
|
transReq_reg1 <= 1'b0;
|
transReq_reg1 <= 1'b0;
|
end
|
end
|
else begin
|
else begin
|
isoEn_reg1 <= isoEnSTB;
|
isoEn_reg1 <= isoEnSTB;
|
isoEn <= isoEn_reg1;
|
isoEn <= isoEn_reg1;
|
preambleEn_reg1 <= preambleEnSTB;
|
preambleEn_reg1 <= preambleEnSTB;
|
preambleEn <= preambleEn_reg1;
|
preambleEn <= preambleEn_reg1;
|
SOFSync_reg1 <= SOFSyncSTB;
|
SOFSync_reg1 <= SOFSyncSTB;
|
SOFSync <= SOFSync_reg1;
|
SOFSync <= SOFSync_reg1;
|
TxTransTypeReg_reg1 <= TxTransTypeRegSTB;
|
TxTransTypeReg_reg1 <= TxTransTypeRegSTB;
|
TxTransTypeReg <= TxTransTypeReg_reg1;
|
TxTransTypeReg <= TxTransTypeReg_reg1;
|
TxSOFEnableReg_reg1 <= TxSOFEnableRegSTB;
|
TxSOFEnableReg_reg1 <= TxSOFEnableRegSTB;
|
TxSOFEnableReg <= TxSOFEnableReg_reg1;
|
TxSOFEnableReg <= TxSOFEnableReg_reg1;
|
TxAddrReg_reg1 <= TxAddrRegSTB;
|
TxAddrReg_reg1 <= TxAddrRegSTB;
|
TxAddrReg <= TxAddrReg_reg1;
|
TxAddrReg <= TxAddrReg_reg1;
|
TxEndPReg_reg1 <= TxEndPRegSTB;
|
TxEndPReg_reg1 <= TxEndPRegSTB;
|
TxEndPReg <= TxEndPReg_reg1;
|
TxEndPReg <= TxEndPReg_reg1;
|
TxLineState_reg1 <= TxLineStateSTB;
|
TxLineState_reg1 <= TxLineStateSTB;
|
TxLineState <= TxLineState_reg1;
|
TxLineState <= TxLineState_reg1;
|
LineDirectControlEn_reg1 <= LineDirectControlEnSTB;
|
LineDirectControlEn_reg1 <= LineDirectControlEnSTB;
|
LineDirectControlEn <= LineDirectControlEn_reg1;
|
LineDirectControlEn <= LineDirectControlEn_reg1;
|
fullSpeedPol_reg1 <= fullSpeedPolSTB;
|
fullSpeedPol_reg1 <= fullSpeedPolSTB;
|
fullSpeedPol <= fullSpeedPol_reg1;
|
fullSpeedPol <= fullSpeedPol_reg1;
|
fullSpeedRate_reg1 <= fullSpeedRateSTB;
|
fullSpeedRate_reg1 <= fullSpeedRateSTB;
|
fullSpeedRate <= fullSpeedRate_reg1;
|
fullSpeedRate <= fullSpeedRate_reg1;
|
transReq_reg1 <= transReqSTB;
|
transReq_reg1 <= transReqSTB;
|
transReq <= transReq_reg1;
|
transReq <= transReq_reg1;
|
end
|
end
|
end
|
end
|
|
|
//Extend resumeIntIn etc from 1 tick to 3 ticks
|
//Extend resumeIntIn etc from 1 tick to 3 ticks
|
always @(posedge usbClk) begin
|
always @(posedge usbClk) begin
|
if (rstSyncToUsbClk == 1'b1) begin
|
if (rstSyncToUsbClk == 1'b1) begin
|
resumeIntInExtend <= 3'b000;
|
resumeIntInExtend <= 3'b000;
|
transDoneInExtend <= 3'b000;
|
transDoneInExtend <= 3'b000;
|
connEventInExtend <= 3'b000;
|
connEventInExtend <= 3'b000;
|
SOFSentInExtend <= 3'b000;
|
SOFSentInExtend <= 3'b000;
|
clrTransReqExtend <= 3'b000;
|
clrTransReqExtend <= 3'b000;
|
end
|
end
|
else begin
|
else begin
|
if (resumeIntIn == 1'b1)
|
if (resumeIntIn == 1'b1)
|
resumeIntInExtend <= 3'b111;
|
resumeIntInExtend <= 3'b111;
|
else
|
else
|
resumeIntInExtend <= {1'b0, resumeIntInExtend[2:1]};
|
resumeIntInExtend <= {1'b0, resumeIntInExtend[2:1]};
|
if (transDoneIn == 1'b1)
|
if (transDoneIn == 1'b1)
|
transDoneInExtend <= 3'b111;
|
transDoneInExtend <= 3'b111;
|
else
|
else
|
transDoneInExtend <= {1'b0, transDoneInExtend[2:1]};
|
transDoneInExtend <= {1'b0, transDoneInExtend[2:1]};
|
if (connEventIn == 1'b1)
|
if (connEventIn == 1'b1)
|
connEventInExtend <= 3'b111;
|
connEventInExtend <= 3'b111;
|
else
|
else
|
connEventInExtend <= {1'b0, connEventInExtend[2:1]};
|
connEventInExtend <= {1'b0, connEventInExtend[2:1]};
|
if (SOFSentIn == 1'b1)
|
if (SOFSentIn == 1'b1)
|
SOFSentInExtend <= 3'b111;
|
SOFSentInExtend <= 3'b111;
|
else
|
else
|
SOFSentInExtend <= {1'b0, SOFSentInExtend[2:1]};
|
SOFSentInExtend <= {1'b0, SOFSentInExtend[2:1]};
|
if (clrTransReq == 1'b1)
|
if (clrTransReq == 1'b1)
|
clrTransReqExtend <= 3'b111;
|
clrTransReqExtend <= 3'b111;
|
else
|
else
|
clrTransReqExtend <= {1'b0, clrTransReqExtend[2:1]};
|
clrTransReqExtend <= {1'b0, clrTransReqExtend[2:1]};
|
end
|
end
|
end
|
end
|
|
|
//re-sync from usbClk to busClk. Since 'clrTransReq', 'transDoneIn' etc are only asserted
|
//re-sync from usbClk to busClk. Since 'clrTransReq', 'transDoneIn' etc are only asserted
|
//for 3 'usbClk' ticks, busClk freq must be greater than or equal to usbClk/3 freq
|
//for 3 'usbClk' ticks, busClk freq must be greater than or equal to usbClk/3 freq
|
always @(posedge busClk) begin
|
always @(posedge busClk) begin
|
if (rstSyncToBusClk == 1'b1) begin
|
if (rstSyncToBusClk == 1'b1) begin
|
SOFSentInSTB <= 3'b000;
|
SOFSentInSTB <= 3'b000;
|
connEventInSTB <= 3'b000;
|
connEventInSTB <= 3'b000;
|
resumeIntInSTB <= 3'b000;
|
resumeIntInSTB <= 3'b000;
|
transDoneInSTB <= 3'b000;
|
transDoneInSTB <= 3'b000;
|
clrTransReqSTB <= 3'b000;
|
clrTransReqSTB <= 3'b000;
|
frameNumInSTB <= {11{1'b0}};
|
frameNumInSTB <= {11{1'b0}};
|
frameNumInSTB_reg1 <= {11{1'b0}};
|
frameNumInSTB_reg1 <= {11{1'b0}};
|
RxPktStatusInSTB <= 8'h00;
|
RxPktStatusInSTB <= 8'h00;
|
RxPktStatusInSTB_reg1 <= 8'h00;
|
RxPktStatusInSTB_reg1 <= 8'h00;
|
RxPIDInSTB <= 4'h0;
|
RxPIDInSTB <= 4'h0;
|
RxPIDInSTB_reg1 <= 4'h0;
|
RxPIDInSTB_reg1 <= 4'h0;
|
connectStateInSTB <= 2'b00;
|
connectStateInSTB <= 2'b00;
|
connectStateInSTB_reg1 <= 2'b00;
|
connectStateInSTB_reg1 <= 2'b00;
|
SOFTimerSTB <= 16'h0000;
|
SOFTimerSTB <= 16'h0000;
|
SOFTimerSTB_reg1 <= 16'h0000;
|
SOFTimerSTB_reg1 <= 16'h0000;
|
end
|
end
|
else begin
|
else begin
|
frameNumInSTB_reg1 <= frameNumIn;
|
frameNumInSTB_reg1 <= frameNumIn;
|
frameNumInSTB <= frameNumInSTB_reg1;
|
frameNumInSTB <= frameNumInSTB_reg1;
|
RxPktStatusInSTB_reg1 <= RxPktStatusIn;
|
RxPktStatusInSTB_reg1 <= RxPktStatusIn;
|
RxPktStatusInSTB <= RxPktStatusInSTB_reg1;
|
RxPktStatusInSTB <= RxPktStatusInSTB_reg1;
|
RxPIDInSTB_reg1 <= RxPIDIn;
|
RxPIDInSTB_reg1 <= RxPIDIn;
|
RxPIDInSTB <= RxPIDInSTB_reg1;
|
RxPIDInSTB <= RxPIDInSTB_reg1;
|
connectStateInSTB_reg1 <= connectStateIn;
|
connectStateInSTB_reg1 <= connectStateIn;
|
connectStateInSTB <= connectStateInSTB_reg1;
|
connectStateInSTB <= connectStateInSTB_reg1;
|
SOFSentInSTB <= {SOFSentInExtend[0], SOFSentInSTB[2:1]};
|
SOFSentInSTB <= {SOFSentInExtend[0], SOFSentInSTB[2:1]};
|
connEventInSTB <= {connEventInExtend[0], connEventInSTB[2:1]};
|
connEventInSTB <= {connEventInExtend[0], connEventInSTB[2:1]};
|
resumeIntInSTB <= {resumeIntInExtend[0], resumeIntInSTB[2:1]};
|
resumeIntInSTB <= {resumeIntInExtend[0], resumeIntInSTB[2:1]};
|
transDoneInSTB <= {transDoneInExtend[0], transDoneInSTB[2:1]};
|
transDoneInSTB <= {transDoneInExtend[0], transDoneInSTB[2:1]};
|
clrTransReqSTB <= {clrTransReqExtend[0], clrTransReqSTB[2:1]};
|
clrTransReqSTB <= {clrTransReqExtend[0], clrTransReqSTB[2:1]};
|
//FIXME. It is not safe to pass 'SOFTimer' multi-bit signal between clock domains this way
|
//FIXME. It is not safe to pass 'SOFTimer' multi-bit signal between clock domains this way
|
//All the other multi-bit signals will be static at the time that they are
|
//All the other multi-bit signals will be static at the time that they are
|
//read, but 'SOFTimer' will not be static.
|
//read, but 'SOFTimer' will not be static.
|
SOFTimerSTB_reg1 <= SOFTimer;
|
SOFTimerSTB_reg1 <= SOFTimer;
|
SOFTimerSTB <= SOFTimerSTB_reg1;
|
SOFTimerSTB <= SOFTimerSTB_reg1;
|
end
|
end
|
end
|
end
|
|
|
|
|
endmodule
|
endmodule
|
|
|