|
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// hostController
|
//// hostController
|
//// ////
|
//// ////
|
//// This file is part of the usbhostslave opencores effort.
|
//// This file is part of the usbhostslave opencores effort.
|
//// http://www.opencores.org/cores/usbhostslave/ ////
|
//// http://www.opencores.org/cores/usbhostslave/ ////
|
//// ////
|
//// ////
|
//// Module Description: ////
|
//// Module Description: ////
|
////
|
////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
////
|
////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Steve Fielding, sfielding@base2designs.com ////
|
//// - Steve Fielding, sfielding@base2designs.com ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
|
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// $Id: hostcontroller.v,v 1.2 2004-12-18 14:36:10 sfielding Exp $
|
// $Id: hostcontroller.v,v 1.3 2004-12-31 14:40:41 sfielding Exp $
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
//
|
//
|
`timescale 1ns / 1ps
|
`timescale 1ns / 1ps
|
`include "usbHostControl_h.v"
|
`include "usbHostControl_h.v"
|
`include "usbConstants_h.v"
|
`include "usbConstants_h.v"
|
|
|
|
|
module hostcontroller (clearTXReq, clk, getPacketRdy, getPacketREn, rst, RXStatus, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);
|
module hostcontroller (clearTXReq, clk, getPacketRdy, getPacketREn, rst, RXStatus, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);
|
input clk;
|
input clk;
|
input getPacketRdy;
|
input getPacketRdy;
|
input rst;
|
input rst;
|
input [7:0]RXStatus;
|
input [7:0]RXStatus;
|
input sendPacketArbiterGnt;
|
input sendPacketArbiterGnt;
|
input sendPacketRdy;
|
input sendPacketRdy;
|
input transReq;
|
input transReq;
|
input [1:0]transType;
|
input [1:0]transType;
|
output clearTXReq;
|
output clearTXReq;
|
output getPacketREn;
|
output getPacketREn;
|
output sendPacketArbiterReq;
|
output sendPacketArbiterReq;
|
output [3:0]sendPacketPID;
|
output [3:0]sendPacketPID;
|
output sendPacketWEn;
|
output sendPacketWEn;
|
output transDone;
|
output transDone;
|
|
|
reg clearTXReq, next_clearTXReq;
|
reg clearTXReq, next_clearTXReq;
|
wire clk;
|
wire clk;
|
wire getPacketRdy;
|
wire getPacketRdy;
|
reg getPacketREn, next_getPacketREn;
|
reg getPacketREn, next_getPacketREn;
|
wire rst;
|
wire rst;
|
wire [7:0]RXStatus;
|
wire [7:0]RXStatus;
|
wire sendPacketArbiterGnt;
|
wire sendPacketArbiterGnt;
|
reg sendPacketArbiterReq, next_sendPacketArbiterReq;
|
reg sendPacketArbiterReq, next_sendPacketArbiterReq;
|
reg [3:0]sendPacketPID, next_sendPacketPID;
|
reg [3:0]sendPacketPID, next_sendPacketPID;
|
wire sendPacketRdy;
|
wire sendPacketRdy;
|
reg sendPacketWEn, next_sendPacketWEn;
|
reg sendPacketWEn, next_sendPacketWEn;
|
reg transDone, next_transDone;
|
reg transDone, next_transDone;
|
wire transReq;
|
wire transReq;
|
wire [1:0]transType;
|
wire [1:0]transType;
|
|
|
// BINARY ENCODED state machine: hstCntrl
|
// BINARY ENCODED state machine: hstCntrl
|
// State codes definitions:
|
// State codes definitions:
|
`define START_HC 5'b00000
|
`define START_HC 5'b00000
|
`define TX_REQ 5'b00001
|
`define TX_REQ 5'b00001
|
`define CHK_TYPE 5'b00010
|
`define CHK_TYPE 5'b00010
|
`define FLAG 5'b00011
|
`define FLAG 5'b00011
|
`define IN_WAIT_DATA_RXED 5'b00100
|
`define IN_WAIT_DATA_RXED 5'b00100
|
`define IN_CHK_FOR_ERROR 5'b00101
|
`define IN_CHK_FOR_ERROR 5'b00101
|
`define IN_CLR_SP_WEN2 5'b00110
|
`define IN_CLR_SP_WEN2 5'b00110
|
`define SETUP_CLR_SP_WEN1 5'b00111
|
`define SETUP_CLR_SP_WEN1 5'b00111
|
`define SETUP_CLR_SP_WEN2 5'b01000
|
`define SETUP_CLR_SP_WEN2 5'b01000
|
`define FIN 5'b01001
|
`define FIN 5'b01001
|
`define WAIT_GNT 5'b01010
|
`define WAIT_GNT 5'b01010
|
`define SETUP_WAIT_PKT_RXED 5'b01011
|
`define SETUP_WAIT_PKT_RXED 5'b01011
|
`define IN_WAIT_IN_SENT 5'b01100
|
`define IN_WAIT_IN_SENT 5'b01100
|
`define OUT0_WAIT_RX_DATA 5'b01101
|
`define OUT0_WAIT_RX_DATA 5'b01101
|
`define OUT0_WAIT_DATA0_SENT 5'b01110
|
`define OUT0_WAIT_DATA0_SENT 5'b01110
|
`define OUT0_WAIT_OUT_SENT 5'b01111
|
`define OUT0_WAIT_OUT_SENT 5'b01111
|
`define SETUP_HC_WAIT_RDY 5'b10000
|
`define SETUP_HC_WAIT_RDY 5'b10000
|
`define IN_WAIT_SP_RDY1 5'b10001
|
`define IN_WAIT_SP_RDY1 5'b10001
|
`define IN_WAIT_SP_RDY2 5'b10010
|
`define IN_WAIT_SP_RDY2 5'b10010
|
`define OUT0_WAIT_SP_RDY1 5'b10011
|
`define OUT0_WAIT_SP_RDY1 5'b10011
|
`define SETUP_WAIT_SETUP_SENT 5'b10100
|
`define SETUP_WAIT_SETUP_SENT 5'b10100
|
`define SETUP_WAIT_DATA_SENT 5'b10101
|
`define SETUP_WAIT_DATA_SENT 5'b10101
|
`define IN_CLR_SP_WEN1 5'b10110
|
`define IN_CLR_SP_WEN1 5'b10110
|
`define IN_WAIT_ACK_SENT 5'b10111
|
`define IN_WAIT_ACK_SENT 5'b10111
|
`define OUT0_CLR_WEN1 5'b11000
|
`define OUT0_CLR_WEN1 5'b11000
|
`define OUT0_CLR_WEN2 5'b11001
|
`define OUT0_CLR_WEN2 5'b11001
|
`define OUT1_WAIT_RX_DATA 5'b11010
|
`define OUT1_WAIT_RX_DATA 5'b11010
|
`define OUT1_WAIT_OUT_SENT 5'b11011
|
`define OUT1_WAIT_OUT_SENT 5'b11011
|
`define OUT1_WAIT_DATA1_SENT 5'b11100
|
`define OUT1_WAIT_DATA1_SENT 5'b11100
|
`define OUT1_WAIT_SP_RDY1 5'b11101
|
`define OUT1_WAIT_SP_RDY1 5'b11101
|
`define OUT1_CLR_WEN1 5'b11110
|
`define OUT1_CLR_WEN1 5'b11110
|
`define OUT1_CLR_WEN2 5'b11111
|
`define OUT1_CLR_WEN2 5'b11111
|
|
|
reg [4:0]CurrState_hstCntrl, NextState_hstCntrl;
|
reg [4:0]CurrState_hstCntrl, NextState_hstCntrl;
|
|
|
|
|
// Machine: hstCntrl
|
// Machine: hstCntrl
|
|
|
// NextState logic (combinatorial)
|
// NextState logic (combinatorial)
|
always @ (transReq or transType or getPacketRdy or RXStatus or sendPacketArbiterGnt or sendPacketRdy or transDone or clearTXReq or getPacketREn or sendPacketArbiterReq or sendPacketPID or sendPacketWEn or CurrState_hstCntrl)
|
always @ (transReq or transType or getPacketRdy or RXStatus or sendPacketArbiterGnt or sendPacketRdy or transDone or clearTXReq or getPacketREn or sendPacketArbiterReq or sendPacketPID or sendPacketWEn or CurrState_hstCntrl)
|
begin
|
begin
|
NextState_hstCntrl <= CurrState_hstCntrl;
|
NextState_hstCntrl <= CurrState_hstCntrl;
|
// Set default values for outputs and signals
|
// Set default values for outputs and signals
|
next_transDone <= transDone;
|
next_transDone <= transDone;
|
next_clearTXReq <= clearTXReq;
|
next_clearTXReq <= clearTXReq;
|
next_getPacketREn <= getPacketREn;
|
next_getPacketREn <= getPacketREn;
|
next_sendPacketArbiterReq <= sendPacketArbiterReq;
|
next_sendPacketArbiterReq <= sendPacketArbiterReq;
|
next_sendPacketPID <= sendPacketPID;
|
next_sendPacketPID <= sendPacketPID;
|
next_sendPacketWEn <= sendPacketWEn;
|
next_sendPacketWEn <= sendPacketWEn;
|
case (CurrState_hstCntrl) // synopsys parallel_case full_case
|
case (CurrState_hstCntrl) // synopsys parallel_case full_case
|
`START_HC:
|
`START_HC:
|
begin
|
begin
|
NextState_hstCntrl <= `TX_REQ;
|
NextState_hstCntrl <= `TX_REQ;
|
end
|
end
|
`TX_REQ:
|
`TX_REQ:
|
begin
|
begin
|
if (transReq == 1'b1)
|
if (transReq == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `WAIT_GNT;
|
NextState_hstCntrl <= `WAIT_GNT;
|
next_sendPacketArbiterReq <= 1'b1;
|
next_sendPacketArbiterReq <= 1'b1;
|
end
|
end
|
end
|
end
|
`CHK_TYPE:
|
`CHK_TYPE:
|
begin
|
begin
|
if (transType == `IN_TRANS)
|
if (transType == `OUTDATA0_TRANS)
|
begin
|
|
NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
|
|
end
|
|
else if (transType == `OUTDATA0_TRANS)
|
|
begin
|
begin
|
NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
|
NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
|
end
|
end
|
else if (transType == `OUTDATA1_TRANS)
|
else if (transType == `IN_TRANS)
|
begin
|
begin
|
NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
|
NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
|
end
|
end
|
else if (transType == `SETUP_TRANS)
|
else if (transType == `SETUP_TRANS)
|
begin
|
begin
|
NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
|
NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
|
end
|
end
|
|
else if (transType == `OUTDATA1_TRANS)
|
|
begin
|
|
NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
|
|
end
|
end
|
end
|
`FLAG:
|
`FLAG:
|
begin
|
begin
|
next_transDone <= 1'b1;
|
next_transDone <= 1'b1;
|
next_clearTXReq <= 1'b1;
|
next_clearTXReq <= 1'b1;
|
next_sendPacketArbiterReq <= 1'b0;
|
next_sendPacketArbiterReq <= 1'b0;
|
NextState_hstCntrl <= `FIN;
|
NextState_hstCntrl <= `FIN;
|
end
|
end
|
`FIN:
|
`FIN:
|
begin
|
begin
|
next_transDone <= 1'b0;
|
next_transDone <= 1'b0;
|
next_clearTXReq <= 1'b0;
|
next_clearTXReq <= 1'b0;
|
NextState_hstCntrl <= `TX_REQ;
|
NextState_hstCntrl <= `TX_REQ;
|
end
|
end
|
`WAIT_GNT:
|
`WAIT_GNT:
|
begin
|
begin
|
if (sendPacketArbiterGnt == 1'b1)
|
if (sendPacketArbiterGnt == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `CHK_TYPE;
|
NextState_hstCntrl <= `CHK_TYPE;
|
end
|
end
|
end
|
end
|
`SETUP_CLR_SP_WEN1:
|
`SETUP_CLR_SP_WEN1:
|
begin
|
begin
|
next_sendPacketWEn <= 1'b0;
|
next_sendPacketWEn <= 1'b0;
|
NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
|
NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
|
end
|
end
|
`SETUP_CLR_SP_WEN2:
|
`SETUP_CLR_SP_WEN2:
|
begin
|
begin
|
next_sendPacketWEn <= 1'b0;
|
next_sendPacketWEn <= 1'b0;
|
NextState_hstCntrl <= `SETUP_WAIT_DATA_SENT;
|
NextState_hstCntrl <= `SETUP_WAIT_DATA_SENT;
|
end
|
end
|
`SETUP_WAIT_PKT_RXED:
|
`SETUP_WAIT_PKT_RXED:
|
begin
|
begin
|
next_getPacketREn <= 1'b0;
|
next_getPacketREn <= 1'b0;
|
if (getPacketRdy == 1'b1)
|
if (getPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `FLAG;
|
NextState_hstCntrl <= `FLAG;
|
end
|
end
|
end
|
end
|
`SETUP_HC_WAIT_RDY:
|
`SETUP_HC_WAIT_RDY:
|
begin
|
begin
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
|
NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketPID <= `SETUP;
|
next_sendPacketPID <= `SETUP;
|
end
|
end
|
end
|
end
|
`SETUP_WAIT_SETUP_SENT:
|
`SETUP_WAIT_SETUP_SENT:
|
begin
|
begin
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
|
NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketPID <= `DATA0;
|
next_sendPacketPID <= `DATA0;
|
end
|
end
|
end
|
end
|
`SETUP_WAIT_DATA_SENT:
|
`SETUP_WAIT_DATA_SENT:
|
begin
|
begin
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
|
NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
|
next_getPacketREn <= 1'b1;
|
next_getPacketREn <= 1'b1;
|
end
|
end
|
end
|
end
|
`IN_WAIT_DATA_RXED:
|
`IN_WAIT_DATA_RXED:
|
begin
|
begin
|
next_getPacketREn <= 1'b0;
|
next_getPacketREn <= 1'b0;
|
if (getPacketRdy == 1'b1)
|
if (getPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
|
NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
|
end
|
end
|
end
|
end
|
`IN_CHK_FOR_ERROR:
|
`IN_CHK_FOR_ERROR:
|
begin
|
begin
|
if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
|
if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
|
RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
|
RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
|
RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
|
RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
|
RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
|
RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
|
RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
|
RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
|
RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)
|
RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)
|
begin
|
begin
|
NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
|
NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
NextState_hstCntrl <= `FLAG;
|
NextState_hstCntrl <= `FLAG;
|
end
|
end
|
end
|
end
|
`IN_CLR_SP_WEN2:
|
`IN_CLR_SP_WEN2:
|
begin
|
begin
|
next_sendPacketWEn <= 1'b0;
|
next_sendPacketWEn <= 1'b0;
|
NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
|
NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
|
end
|
end
|
`IN_WAIT_IN_SENT:
|
`IN_WAIT_IN_SENT:
|
begin
|
begin
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
|
NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
|
next_getPacketREn <= 1'b1;
|
next_getPacketREn <= 1'b1;
|
end
|
end
|
end
|
end
|
`IN_WAIT_SP_RDY1:
|
`IN_WAIT_SP_RDY1:
|
begin
|
begin
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `IN_CLR_SP_WEN1;
|
NextState_hstCntrl <= `IN_CLR_SP_WEN1;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketPID <= `IN;
|
next_sendPacketPID <= `IN;
|
end
|
end
|
end
|
end
|
`IN_WAIT_SP_RDY2:
|
`IN_WAIT_SP_RDY2:
|
begin
|
begin
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `IN_CLR_SP_WEN2;
|
NextState_hstCntrl <= `IN_CLR_SP_WEN2;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketPID <= `ACK;
|
next_sendPacketPID <= `ACK;
|
end
|
end
|
end
|
end
|
`IN_CLR_SP_WEN1:
|
`IN_CLR_SP_WEN1:
|
begin
|
begin
|
next_sendPacketWEn <= 1'b0;
|
next_sendPacketWEn <= 1'b0;
|
NextState_hstCntrl <= `IN_WAIT_IN_SENT;
|
NextState_hstCntrl <= `IN_WAIT_IN_SENT;
|
end
|
end
|
`IN_WAIT_ACK_SENT:
|
`IN_WAIT_ACK_SENT:
|
begin
|
begin
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `FLAG;
|
NextState_hstCntrl <= `FLAG;
|
end
|
end
|
end
|
end
|
`OUT0_WAIT_RX_DATA:
|
`OUT0_WAIT_RX_DATA:
|
begin
|
begin
|
next_getPacketREn <= 1'b0;
|
next_getPacketREn <= 1'b0;
|
if (getPacketRdy == 1'b1)
|
if (getPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `FLAG;
|
NextState_hstCntrl <= `FLAG;
|
end
|
end
|
end
|
end
|
`OUT0_WAIT_DATA0_SENT:
|
`OUT0_WAIT_DATA0_SENT:
|
begin
|
begin
|
next_sendPacketWEn <= 1'b0;
|
next_sendPacketWEn <= 1'b0;
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
|
NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
|
next_getPacketREn <= 1'b1;
|
next_getPacketREn <= 1'b1;
|
end
|
end
|
end
|
end
|
`OUT0_WAIT_OUT_SENT:
|
`OUT0_WAIT_OUT_SENT:
|
begin
|
begin
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `OUT0_CLR_WEN2;
|
NextState_hstCntrl <= `OUT0_CLR_WEN2;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketPID <= `DATA0;
|
next_sendPacketPID <= `DATA0;
|
end
|
end
|
end
|
end
|
`OUT0_WAIT_SP_RDY1:
|
`OUT0_WAIT_SP_RDY1:
|
begin
|
begin
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `OUT0_CLR_WEN1;
|
NextState_hstCntrl <= `OUT0_CLR_WEN1;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketPID <= `OUT;
|
next_sendPacketPID <= `OUT;
|
end
|
end
|
end
|
end
|
`OUT0_CLR_WEN1:
|
`OUT0_CLR_WEN1:
|
begin
|
begin
|
next_sendPacketWEn <= 1'b0;
|
next_sendPacketWEn <= 1'b0;
|
NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
|
NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
|
end
|
end
|
`OUT0_CLR_WEN2:
|
`OUT0_CLR_WEN2:
|
begin
|
begin
|
next_sendPacketWEn <= 1'b0;
|
next_sendPacketWEn <= 1'b0;
|
NextState_hstCntrl <= `OUT0_WAIT_DATA0_SENT;
|
NextState_hstCntrl <= `OUT0_WAIT_DATA0_SENT;
|
end
|
end
|
`OUT1_WAIT_RX_DATA:
|
`OUT1_WAIT_RX_DATA:
|
begin
|
begin
|
next_getPacketREn <= 1'b0;
|
next_getPacketREn <= 1'b0;
|
if (getPacketRdy == 1'b1)
|
if (getPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `FLAG;
|
NextState_hstCntrl <= `FLAG;
|
end
|
end
|
end
|
end
|
`OUT1_WAIT_OUT_SENT:
|
`OUT1_WAIT_OUT_SENT:
|
begin
|
begin
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `OUT1_CLR_WEN2;
|
NextState_hstCntrl <= `OUT1_CLR_WEN2;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketPID <= `DATA1;
|
next_sendPacketPID <= `DATA1;
|
end
|
end
|
end
|
end
|
`OUT1_WAIT_DATA1_SENT:
|
`OUT1_WAIT_DATA1_SENT:
|
begin
|
begin
|
next_sendPacketWEn <= 1'b0;
|
next_sendPacketWEn <= 1'b0;
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
|
NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
|
next_getPacketREn <= 1'b1;
|
next_getPacketREn <= 1'b1;
|
end
|
end
|
end
|
end
|
`OUT1_WAIT_SP_RDY1:
|
`OUT1_WAIT_SP_RDY1:
|
begin
|
begin
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `OUT1_CLR_WEN1;
|
NextState_hstCntrl <= `OUT1_CLR_WEN1;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketPID <= `OUT;
|
next_sendPacketPID <= `OUT;
|
end
|
end
|
end
|
end
|
`OUT1_CLR_WEN1:
|
`OUT1_CLR_WEN1:
|
begin
|
begin
|
next_sendPacketWEn <= 1'b0;
|
next_sendPacketWEn <= 1'b0;
|
NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
|
NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
|
end
|
end
|
`OUT1_CLR_WEN2:
|
`OUT1_CLR_WEN2:
|
begin
|
begin
|
next_sendPacketWEn <= 1'b0;
|
next_sendPacketWEn <= 1'b0;
|
NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
|
NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
// Current State Logic (sequential)
|
// Current State Logic (sequential)
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
CurrState_hstCntrl <= `START_HC;
|
CurrState_hstCntrl <= `START_HC;
|
else
|
else
|
CurrState_hstCntrl <= NextState_hstCntrl;
|
CurrState_hstCntrl <= NextState_hstCntrl;
|
end
|
end
|
|
|
// Registered outputs logic
|
// Registered outputs logic
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
begin
|
begin
|
transDone <= 1'b0;
|
transDone <= 1'b0;
|
clearTXReq <= 1'b0;
|
clearTXReq <= 1'b0;
|
getPacketREn <= 1'b0;
|
getPacketREn <= 1'b0;
|
sendPacketArbiterReq <= 1'b0;
|
sendPacketArbiterReq <= 1'b0;
|
sendPacketPID <= 4'b0;
|
sendPacketPID <= 4'b0;
|
sendPacketWEn <= 1'b0;
|
sendPacketWEn <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
transDone <= next_transDone;
|
transDone <= next_transDone;
|
clearTXReq <= next_clearTXReq;
|
clearTXReq <= next_clearTXReq;
|
getPacketREn <= next_getPacketREn;
|
getPacketREn <= next_getPacketREn;
|
sendPacketArbiterReq <= next_sendPacketArbiterReq;
|
sendPacketArbiterReq <= next_sendPacketArbiterReq;
|
sendPacketPID <= next_sendPacketPID;
|
sendPacketPID <= next_sendPacketPID;
|
sendPacketWEn <= next_sendPacketWEn;
|
sendPacketWEn <= next_sendPacketWEn;
|
end
|
end
|
end
|
end
|
|
|
|
|