//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// rxStatusMonitor.v ////
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//// rxStatusMonitor.v ////
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//// ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// ////
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//// Module Description: ////
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//// Module Description: ////
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////
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////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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////
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////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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`timescale 1ns / 1ps
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`include "timescale.v"
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module rxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, connectionEventOut, resumeIntOut, clk, rst);
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module rxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, connectionEventOut, resumeIntOut, clk, rst);
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input [1:0] connectStateIn;
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input [1:0] connectStateIn;
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input resumeDetectedIn;
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input resumeDetectedIn;
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input clk;
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input clk;
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input rst;
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input rst;
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output connectionEventOut;
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output connectionEventOut;
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output [1:0] connectStateOut;
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output [1:0] connectStateOut;
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output resumeIntOut;
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output resumeIntOut;
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wire [1:0] connectStateIn;
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wire [1:0] connectStateIn;
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wire resumeDetectedIn;
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wire resumeDetectedIn;
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reg connectionEventOut;
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reg connectionEventOut;
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reg [1:0] connectStateOut;
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reg [1:0] connectStateOut;
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reg resumeIntOut;
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reg resumeIntOut;
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wire clk;
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wire clk;
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wire rst;
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wire rst;
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reg [1:0]oldConnectState;
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reg [1:0]oldConnectState;
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reg oldResumeDetected;
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reg oldResumeDetected;
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always @(connectStateIn)
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always @(connectStateIn)
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begin
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begin
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connectStateOut <= connectStateIn;
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connectStateOut <= connectStateIn;
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end
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end
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if (rst == 1'b1)
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if (rst == 1'b1)
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begin
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begin
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oldConnectState <= connectStateIn;
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oldConnectState <= connectStateIn;
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oldResumeDetected <= resumeDetectedIn;
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oldResumeDetected <= resumeDetectedIn;
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end
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end
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else
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else
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begin
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begin
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oldConnectState <= connectStateIn;
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oldConnectState <= connectStateIn;
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oldResumeDetected <= resumeDetectedIn;
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oldResumeDetected <= resumeDetectedIn;
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if (oldConnectState != connectStateIn)
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if (oldConnectState != connectStateIn)
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connectionEventOut <= 1'b1;
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connectionEventOut <= 1'b1;
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else
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else
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connectionEventOut <= 1'b0;
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connectionEventOut <= 1'b0;
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if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
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if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
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resumeIntOut <= 1'b1;
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resumeIntOut <= 1'b1;
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else
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else
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resumeIntOut <= 1'b0;
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resumeIntOut <= 1'b0;
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end
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end
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end
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end
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endmodule
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endmodule
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