VERSION=1.15
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VERSION=1.15
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HEADER
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HEADER
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FILE="sendpacketcheckpreamble.asf"
|
FILE="sendpacketcheckpreamble.asf"
|
FID=4061fc61
|
FID=4061fc61
|
LANGUAGE=VERILOG
|
LANGUAGE=VERILOG
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ENTITY="sendPacketCheckPreamble"
|
ENTITY="sendPacketCheckPreamble"
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FRAMES=ON
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FRAMES=ON
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FREEOID=161
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FREEOID=161
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"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// sendpacketcheckpreamble\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbConstants_h.v\"\n"
|
"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// sendpacketcheckpreamble\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbConstants_h.v\"\n"
|
END
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END
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BUNDLES
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OBJECTS
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OBJECTS
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C 73 39 0 TEXT "Conditions" | 145852,37243 1 0 0 "sendPacketRdy == 1'b1"
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I 85 0 2 Builtin InPort | 31234,242140 "" ""
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A 119 109 4 TEXT "Actions" | 116106,190635 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= sendPacketCPPID;"
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A 119 109 4 TEXT "Actions" | 116106,190635 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= sendPacketCPPID;"
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|
A 133 17 16 TEXT "Actions" | 115300,141513 1 0 0 "sendPacketCPReady <= 1'b0;"
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A 133 17 16 TEXT "Actions" | 115300,141513 1 0 0 "sendPacketCPReady <= 1'b0;"
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L 134 135 0 TEXT "State Labels" | 115950,65625 1 0 0 "READY\n/11/"
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|
L 142 143 0 TEXT "Labels" | 198551,245909 1 0 0 "rst"
|
L 142 143 0 TEXT "Labels" | 198551,245909 1 0 0 "rst"
|
I 143 0 2 Builtin InPort | 192551,245909 "" ""
|
I 143 0 2 Builtin InPort | 192551,245909 "" ""
|
I 151 0 2 Builtin InPort | 34428,222262 "" ""
|
I 151 0 2 Builtin InPort | 34428,222262 "" ""
|
L 150 151 0 TEXT "Labels" | 40428,222262 1 0 0 "preAmbleEnable"
|
L 150 151 0 TEXT "Labels" | 40428,222262 1 0 0 "preAmbleEnable"
|
L 148 147 0 TEXT "Labels" | 147295,224322 1 0 0 "sendPacketRdy"
|
L 148 147 0 TEXT "Labels" | 147295,224322 1 0 0 "sendPacketRdy"
|
I 147 0 2 Builtin InPort | 141295,224322 "" ""
|
I 147 0 2 Builtin InPort | 141295,224322 "" ""
|
C 144 15 0 TEXT "Conditions" | 95870,191427 1 0 0 "rst"
|
C 144 15 0 TEXT "Conditions" | 95870,191427 1 0 0 "rst"
|
A 145 9 2 TEXT "Actions" | 136081,193747 1 0 0 "sendPacketWEn <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketCPReady <= 1'b1;"
|
A 145 9 2 TEXT "Actions" | 136081,193747 1 0 0 "sendPacketWEn <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketCPReady <= 1'b1;"
|
A 152 116 4 TEXT "Actions" | 116610,159800 1 0 0 "sendPacketWEn <= 1'b0;"
|
A 152 116 4 TEXT "Actions" | 116610,159800 1 0 0 "sendPacketWEn <= 1'b0;"
|
A 153 55 4 TEXT "Actions" | 107648,155030 1 0 0 "sendPacketWEn <= 1'b0;"
|
A 153 55 4 TEXT "Actions" | 107648,155030 1 0 0 "sendPacketWEn <= 1'b0;"
|
A 154 68 4 TEXT "Actions" | 110643,60458 1 0 0 "sendPacketWEn <= 1'b0;"
|
A 154 68 4 TEXT "Actions" | 110643,60458 1 0 0 "sendPacketWEn <= 1'b0;"
|
L 155 156 0 TEXT "State Labels" | 56256,124044 1 0 0 "WAIT_RDY2\n/12/"
|
L 155 156 0 TEXT "State Labels" | 56256,124044 1 0 0 "WAIT_RDY2\n/12/"
|
S 156 33 53248 ELLIPSE "States" | 56256,124044 6500 6500
|
S 156 33 53248 ELLIPSE "States" | 56256,124044 6500 6500
|
L 157 158 0 TEXT "State Labels" | 111700,39052 1 0 0 "WAIT_RDY3\n/13/"
|
L 157 158 0 TEXT "State Labels" | 111700,39052 1 0 0 "WAIT_RDY3\n/13/"
|
S 158 33 57344 ELLIPSE "States" | 111700,39052 6500 6500
|
S 158 33 57344 ELLIPSE "States" | 111700,39052 6500 6500
|
W 159 33 0 55 156 BEZIER "Transitions" | 82977,149448 77086,144036 66423,134323 60447,129011
|
W 159 33 0 55 156 BEZIER "Transitions" | 82977,149448 77086,144036 66423,134323 60447,129011
|
W 160 33 0 68 158 BEZIER "Transitions" | 95503,53062 98906,50738 103474,45732 106877,43408
|
W 160 33 0 68 158 BEZIER "Transitions" | 95503,53062 98906,50738 103474,45732 106877,43408
|
END
|
END
|
|
|
