|
|
|
// File : ../RTL/hostController/softransmit.v
|
|
// Generated : 10/06/06 19:35:27
|
|
// From : ../RTL/hostController/softransmit.asf
|
|
// By : FSM2VHDL ver. 5.0.0.9
|
|
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// softransmit
|
//// softransmit
|
//// ////
|
//// ////
|
//// This file is part of the usbhostslave opencores effort.
|
//// This file is part of the usbhostslave opencores effort.
|
//// http://www.opencores.org/cores/usbhostslave/ ////
|
//// http://www.opencores.org/cores/usbhostslave/ ////
|
//// ////
|
//// ////
|
//// Module Description: ////
|
//// Module Description: ////
|
////
|
////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
////
|
////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Steve Fielding, sfielding@base2designs.com ////
|
//// - Steve Fielding, sfielding@base2designs.com ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
|
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
`timescale 1ns / 1ps
|
`include "timescale.v"
|
`include "usbHostControl_h.v"
|
`include "usbHostControl_h.v"
|
|
|
|
|
module SOFTransmit (clk, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketRdy, sendPacketWEn, SOFEnable, SOFSent, SOFSyncEn, SOFTimer, SOFTimerClr);
|
module SOFTransmit (SOFEnable, SOFSent, SOFSyncEn, SOFTimerClr, SOFTimer, clk, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketRdy, sendPacketWEn);
|
|
input SOFEnable; // After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn
|
|
input SOFSyncEn;
|
|
input [15:0] SOFTimer;
|
input clk;
|
input clk;
|
input rst;
|
input rst;
|
input sendPacketArbiterGnt;
|
input sendPacketArbiterGnt;
|
input sendPacketRdy;
|
input sendPacketRdy;
|
input SOFEnable; // After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn
|
|
input SOFSyncEn;
|
|
input [15:0]SOFTimer;
|
|
output sendPacketArbiterReq;
|
|
output sendPacketWEn;
|
|
output SOFSent; // single cycle pulse
|
output SOFSent; // single cycle pulse
|
output SOFTimerClr; // Single cycle pulse
|
output SOFTimerClr; // Single cycle pulse
|
|
output sendPacketArbiterReq;
|
|
output sendPacketWEn;
|
|
|
|
wire SOFEnable;
|
|
reg SOFSent, next_SOFSent;
|
|
wire SOFSyncEn;
|
|
reg SOFTimerClr, next_SOFTimerClr;
|
|
wire [15:0] SOFTimer;
|
wire clk;
|
wire clk;
|
wire rst;
|
wire rst;
|
wire sendPacketArbiterGnt;
|
wire sendPacketArbiterGnt;
|
reg sendPacketArbiterReq, next_sendPacketArbiterReq;
|
reg sendPacketArbiterReq, next_sendPacketArbiterReq;
|
wire sendPacketRdy;
|
wire sendPacketRdy;
|
reg sendPacketWEn, next_sendPacketWEn;
|
reg sendPacketWEn, next_sendPacketWEn;
|
wire SOFEnable;
|
|
reg SOFSent, next_SOFSent;
|
|
wire SOFSyncEn;
|
|
wire [15:0]SOFTimer;
|
|
reg SOFTimerClr, next_SOFTimerClr;
|
|
|
|
// diagram signals declarations
|
// diagram signals declarations
|
reg [7:0]i, next_i;
|
reg [7:0]i, next_i;
|
|
|
// BINARY ENCODED state machine: SOFTx
|
// BINARY ENCODED state machine: SOFTx
|
// State codes definitions:
|
// State codes definitions:
|
`define START_STX 3'b000
|
`define START_STX 3'b000
|
`define WAIT_SOF_NEAR 3'b001
|
`define WAIT_SOF_NEAR 3'b001
|
`define WAIT_SP_GNT 3'b010
|
`define WAIT_SP_GNT 3'b010
|
`define WAIT_SOF_NOW 3'b011
|
`define WAIT_SOF_NOW 3'b011
|
`define SOF_FIN 3'b100
|
`define SOF_FIN 3'b100
|
`define DLY_SOF_CHK1 3'b101
|
`define DLY_SOF_CHK1 3'b101
|
`define DLY_SOF_CHK2 3'b110
|
`define DLY_SOF_CHK2 3'b110
|
|
|
reg [2:0]CurrState_SOFTx, NextState_SOFTx;
|
reg [2:0] CurrState_SOFTx;
|
|
reg [2:0] NextState_SOFTx;
|
|
|
|
|
|
//--------------------------------------------------------------------
|
// Machine: SOFTx
|
// Machine: SOFTx
|
|
//--------------------------------------------------------------------
|
// NextState logic (combinatorial)
|
//----------------------------------
|
always @ (SOFTimer or SOFSyncEn or SOFEnable or sendPacketArbiterGnt or sendPacketRdy or i or SOFSent or SOFTimerClr or sendPacketArbiterReq or sendPacketWEn or CurrState_SOFTx)
|
// Next State Logic (combinatorial)
|
begin
|
//----------------------------------
|
|
always @ (i or SOFTimer or SOFSyncEn or SOFEnable or sendPacketArbiterGnt or sendPacketRdy or sendPacketArbiterReq or sendPacketWEn or SOFTimerClr or SOFSent or CurrState_SOFTx)
|
|
begin : SOFTx_NextState
|
NextState_SOFTx <= CurrState_SOFTx;
|
NextState_SOFTx <= CurrState_SOFTx;
|
// Set default values for outputs and signals
|
// Set default values for outputs and signals
|
next_SOFSent <= SOFSent;
|
|
next_SOFTimerClr <= SOFTimerClr;
|
|
next_sendPacketArbiterReq <= sendPacketArbiterReq;
|
next_sendPacketArbiterReq <= sendPacketArbiterReq;
|
next_sendPacketWEn <= sendPacketWEn;
|
next_sendPacketWEn <= sendPacketWEn;
|
|
next_SOFTimerClr <= SOFTimerClr;
|
|
next_SOFSent <= SOFSent;
|
next_i <= i;
|
next_i <= i;
|
case (CurrState_SOFTx) // synopsys parallel_case full_case
|
case (CurrState_SOFTx)
|
`START_STX:
|
`START_STX:
|
begin
|
|
NextState_SOFTx <= `WAIT_SOF_NEAR;
|
NextState_SOFTx <= `WAIT_SOF_NEAR;
|
end
|
|
`WAIT_SOF_NEAR:
|
`WAIT_SOF_NEAR:
|
begin
|
|
if (SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||
|
if (SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||
|
(SOFSyncEn == 1'b1 &&
|
(SOFSyncEn == 1'b1 &&
|
SOFEnable == 1'b1))
|
SOFEnable == 1'b1))
|
begin
|
begin
|
NextState_SOFTx <= `WAIT_SP_GNT;
|
NextState_SOFTx <= `WAIT_SP_GNT;
|
next_sendPacketArbiterReq <= 1'b1;
|
next_sendPacketArbiterReq <= 1'b1;
|
end
|
end
|
end
|
|
`WAIT_SP_GNT:
|
`WAIT_SP_GNT:
|
begin
|
|
if (sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1)
|
if (sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1)
|
begin
|
|
NextState_SOFTx <= `WAIT_SOF_NOW;
|
NextState_SOFTx <= `WAIT_SOF_NOW;
|
end
|
|
end
|
|
`WAIT_SOF_NOW:
|
`WAIT_SOF_NOW:
|
begin
|
|
if (SOFTimer >= `SOF_TX_TIME)
|
if (SOFTimer >= `SOF_TX_TIME)
|
begin
|
begin
|
NextState_SOFTx <= `SOF_FIN;
|
NextState_SOFTx <= `SOF_FIN;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketWEn <= 1'b1;
|
next_SOFTimerClr <= 1'b1;
|
next_SOFTimerClr <= 1'b1;
|
next_SOFSent <= 1'b1;
|
next_SOFSent <= 1'b1;
|
end
|
end
|
else if (SOFEnable == 1'b0)
|
else if (SOFEnable == 1'b0)
|
begin
|
begin
|
NextState_SOFTx <= `SOF_FIN;
|
NextState_SOFTx <= `SOF_FIN;
|
next_SOFTimerClr <= 1'b1;
|
next_SOFTimerClr <= 1'b1;
|
end
|
end
|
end
|
|
`SOF_FIN:
|
`SOF_FIN:
|
begin
|
begin
|
next_sendPacketWEn <= 1'b0;
|
next_sendPacketWEn <= 1'b0;
|
next_SOFTimerClr <= 1'b0;
|
next_SOFTimerClr <= 1'b0;
|
next_SOFSent <= 1'b0;
|
next_SOFSent <= 1'b0;
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_SOFTx <= `DLY_SOF_CHK1;
|
NextState_SOFTx <= `DLY_SOF_CHK1;
|
next_i <= 8'h00;
|
next_i <= 8'h00;
|
end
|
end
|
end
|
end
|
`DLY_SOF_CHK1:
|
`DLY_SOF_CHK1:
|
begin
|
begin
|
next_i <= i + 1'b1;
|
next_i <= i + 1'b1;
|
if (i==8'hff)
|
if (i==8'hff)
|
begin
|
begin
|
NextState_SOFTx <= `DLY_SOF_CHK2;
|
NextState_SOFTx <= `DLY_SOF_CHK2;
|
next_sendPacketArbiterReq <= 1'b0;
|
next_sendPacketArbiterReq <= 1'b0;
|
next_i <= 8'h00;
|
next_i <= 8'h00;
|
end
|
end
|
end
|
end
|
`DLY_SOF_CHK2:
|
`DLY_SOF_CHK2:
|
begin
|
begin
|
next_i <= i + 1'b1;
|
next_i <= i + 1'b1;
|
if (i==8'hff)
|
if (i==8'hff)
|
begin
|
|
NextState_SOFTx <= `WAIT_SOF_NEAR;
|
NextState_SOFTx <= `WAIT_SOF_NEAR;
|
end
|
end
|
end
|
|
endcase
|
endcase
|
end
|
end
|
|
|
|
//----------------------------------
|
// Current State Logic (sequential)
|
// Current State Logic (sequential)
|
|
//----------------------------------
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin : SOFTx_CurrentState
|
if (rst)
|
if (rst)
|
CurrState_SOFTx <= `START_STX;
|
CurrState_SOFTx <= `START_STX;
|
else
|
else
|
CurrState_SOFTx <= NextState_SOFTx;
|
CurrState_SOFTx <= NextState_SOFTx;
|
end
|
end
|
|
|
|
//----------------------------------
|
// Registered outputs logic
|
// Registered outputs logic
|
|
//----------------------------------
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin : SOFTx_RegOutput
|
if (rst)
|
if (rst)
|
begin
|
begin
|
|
i <= 8'h00;
|
SOFSent <= 1'b0;
|
SOFSent <= 1'b0;
|
SOFTimerClr <= 1'b0;
|
SOFTimerClr <= 1'b0;
|
sendPacketArbiterReq <= 1'b0;
|
sendPacketArbiterReq <= 1'b0;
|
sendPacketWEn <= 1'b0;
|
sendPacketWEn <= 1'b0;
|
i <= 8'h00;
|
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
i <= next_i;
|
SOFSent <= next_SOFSent;
|
SOFSent <= next_SOFSent;
|
SOFTimerClr <= next_SOFTimerClr;
|
SOFTimerClr <= next_SOFTimerClr;
|
sendPacketArbiterReq <= next_sendPacketArbiterReq;
|
sendPacketArbiterReq <= next_sendPacketArbiterReq;
|
sendPacketWEn <= next_sendPacketWEn;
|
sendPacketWEn <= next_sendPacketWEn;
|
i <= next_i;
|
|
end
|
end
|
end
|
end
|
|
|
|
|
