Subversion Repositories usbhostslave

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//// hostSlaveMux.v                                               ////

//// hostSlaveMux.v                                               ////

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//// This file is part of the usbhostslave opencores effort.

//// This file is part of the usbhostslave opencores effort.

//// <http://www.opencores.org/cores//>                           ////

//// <http://www.opencores.org/cores//>                           ////

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//// Module Description:                                          ////

//// Module Description:                                          ////

//// 

//// 

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//// To Do:                                                       ////

//// To Do:                                                       ////

//// 

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//// Author(s):                                                   ////

//// Author(s):                                                   ////

//// - Steve Fielding, sfielding@base2designs.com                 ////

//// - Steve Fielding, sfielding@base2designs.com                 ////

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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////

//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////

////                                                              ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

//// later version.                                               ////

////                                                              ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE. See the GNU Lesser General Public License for more  ////

//// PURPOSE. See the GNU Lesser General Public License for more  ////

//// details.                                                     ////

//// details.                                                     ////

////                                                              ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// Public License along with this source; if not, download it   ////

//// from <http://www.opencores.org/lgpl.shtml>                   ////

//// from <http://www.opencores.org/lgpl.shtml>                   ////

////                                                              ////

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//

//

module hostSlaveMux (

module hostSlaveMux (

  SIEPortCtrlInToSIE,

  SIEPortCtrlInToSIE,

  SIEPortCtrlInFromHost,

  SIEPortCtrlInFromHost,

  SIEPortCtrlInFromSlave,

  SIEPortCtrlInFromSlave,

  SIEPortDataInToSIE,

  SIEPortDataInToSIE,

  SIEPortDataInFromHost,

  SIEPortDataInFromHost,

  SIEPortDataInFromSlave,

  SIEPortDataInFromSlave,

  SIEPortWEnToSIE,

  SIEPortWEnToSIE,

  SIEPortWEnFromHost,

  SIEPortWEnFromHost,

  SIEPortWEnFromSlave,

  SIEPortWEnFromSlave,

  fullSpeedPolarityToSIE,

  fullSpeedPolarityToSIE,

  fullSpeedPolarityFromHost,

  fullSpeedPolarityFromHost,

  fullSpeedPolarityFromSlave,

  fullSpeedPolarityFromSlave,

  fullSpeedBitRateToSIE,

  fullSpeedBitRateToSIE,

  fullSpeedBitRateFromHost,

  fullSpeedBitRateFromHost,

  fullSpeedBitRateFromSlave,

  fullSpeedBitRateFromSlave,

  dataIn,

  dataIn,

  dataOut,

  dataOut,

  writeEn,

  writeEn,

  strobe_i,

  strobe_i,

  clk,

  clk,

  rst,

  rst,

  hostSlaveMuxSel  );

  hostSlaveMuxSel  );

output [7:0] SIEPortCtrlInToSIE;

output [7:0] SIEPortCtrlInToSIE;

input [7:0] SIEPortCtrlInFromHost;

input [7:0] SIEPortCtrlInFromHost;

input [7:0] SIEPortCtrlInFromSlave;

input [7:0] SIEPortCtrlInFromSlave;

output [7:0] SIEPortDataInToSIE;

output [7:0] SIEPortDataInToSIE;

input [7:0] SIEPortDataInFromHost;

input [7:0] SIEPortDataInFromHost;

input [7:0] SIEPortDataInFromSlave;

input [7:0] SIEPortDataInFromSlave;

output SIEPortWEnToSIE;

output SIEPortWEnToSIE;

input SIEPortWEnFromHost;

input SIEPortWEnFromHost;

input SIEPortWEnFromSlave;

input SIEPortWEnFromSlave;

output fullSpeedPolarityToSIE;

output fullSpeedPolarityToSIE;

input fullSpeedPolarityFromHost;

input fullSpeedPolarityFromHost;

input fullSpeedPolarityFromSlave;

input fullSpeedPolarityFromSlave;

output fullSpeedBitRateToSIE;

output fullSpeedBitRateToSIE;

input fullSpeedBitRateFromHost;

input fullSpeedBitRateFromHost;

input fullSpeedBitRateFromSlave;

input fullSpeedBitRateFromSlave;

//hostSlaveMuxBI

//hostSlaveMuxBI

input [7:0] dataIn;

input [7:0] dataIn;

input writeEn;

input writeEn;

input strobe_i;

input strobe_i;

input clk;

input clk;

input rst;

input rst;

output [7:0] dataOut;

output [7:0] dataOut;

input hostSlaveMuxSel;

input hostSlaveMuxSel;

reg [7:0] SIEPortCtrlInToSIE;

reg [7:0] SIEPortCtrlInToSIE;

wire [7:0] SIEPortCtrlInFromHost;

wire [7:0] SIEPortCtrlInFromHost;

wire [7:0] SIEPortCtrlInFromSlave;

wire [7:0] SIEPortCtrlInFromSlave;

reg [7:0] SIEPortDataInToSIE;

reg [7:0] SIEPortDataInToSIE;

wire [7:0] SIEPortDataInFromHost;

wire [7:0] SIEPortDataInFromHost;

wire [7:0] SIEPortDataInFromSlave;

wire [7:0] SIEPortDataInFromSlave;

reg SIEPortWEnToSIE;

reg SIEPortWEnToSIE;

wire SIEPortWEnFromHost;

wire SIEPortWEnFromHost;

wire SIEPortWEnFromSlave;

wire SIEPortWEnFromSlave;

reg fullSpeedPolarityToSIE;

reg fullSpeedPolarityToSIE;

wire fullSpeedPolarityFromHost;

wire fullSpeedPolarityFromHost;

wire fullSpeedPolarityFromSlave;

wire fullSpeedPolarityFromSlave;

reg fullSpeedBitRateToSIE;

reg fullSpeedBitRateToSIE;

wire fullSpeedBitRateFromHost;

wire fullSpeedBitRateFromHost;

wire fullSpeedBitRateFromSlave;

wire fullSpeedBitRateFromSlave;

//hostSlaveMuxBI

//hostSlaveMuxBI

wire [7:0] dataIn;

wire [7:0] dataIn;

wire writeEn;

wire writeEn;

wire strobe_i;

wire strobe_i;

wire clk;

wire clk;

wire rst;

wire rst;

wire [7:0] dataOut;

wire [7:0] dataOut;

wire hostSlaveMuxSel;

wire hostSlaveMuxSel;

//internal wires and regs

//internal wires and regs

wire hostMode;

wire hostMode;

always @(hostMode or

always @(hostMode or

  SIEPortCtrlInFromHost or

  SIEPortCtrlInFromHost or

  SIEPortCtrlInFromSlave or

  SIEPortCtrlInFromSlave or

  SIEPortDataInFromHost or

  SIEPortDataInFromHost or

  SIEPortDataInFromSlave or

  SIEPortDataInFromSlave or

  SIEPortWEnFromHost or

  SIEPortWEnFromHost or

  SIEPortWEnFromSlave or

  SIEPortWEnFromSlave or

  fullSpeedPolarityFromHost or

  fullSpeedPolarityFromHost or

  fullSpeedPolarityFromSlave or

  fullSpeedPolarityFromSlave or

  fullSpeedBitRateFromHost or

  fullSpeedBitRateFromHost or

  fullSpeedBitRateFromSlave)

  fullSpeedBitRateFromSlave)

begin

begin

  if (hostMode == 1'b1)

  if (hostMode == 1'b1)

  begin

  begin

    SIEPortCtrlInToSIE <= SIEPortCtrlInFromHost;

    SIEPortCtrlInToSIE <= SIEPortCtrlInFromHost;

    SIEPortDataInToSIE <=  SIEPortDataInFromHost;

    SIEPortDataInToSIE <=  SIEPortDataInFromHost;

    SIEPortWEnToSIE <= SIEPortWEnFromHost;

    SIEPortWEnToSIE <= SIEPortWEnFromHost;

    fullSpeedPolarityToSIE <= fullSpeedPolarityFromHost;

    fullSpeedPolarityToSIE <= fullSpeedPolarityFromHost;

    fullSpeedBitRateToSIE <= fullSpeedBitRateFromHost;

    fullSpeedBitRateToSIE <= fullSpeedBitRateFromHost;

  end

  end

  else

  else

  begin

  begin

    SIEPortCtrlInToSIE <= SIEPortCtrlInFromSlave;

    SIEPortCtrlInToSIE <= SIEPortCtrlInFromSlave;

    SIEPortDataInToSIE <=  SIEPortDataInFromSlave;

    SIEPortDataInToSIE <=  SIEPortDataInFromSlave;

    SIEPortWEnToSIE <= SIEPortWEnFromSlave;

    SIEPortWEnToSIE <= SIEPortWEnFromSlave;

    fullSpeedPolarityToSIE <= fullSpeedPolarityFromSlave;

    fullSpeedPolarityToSIE <= fullSpeedPolarityFromSlave;

    fullSpeedBitRateToSIE <= fullSpeedBitRateFromSlave;

    fullSpeedBitRateToSIE <= fullSpeedBitRateFromSlave;

  end

  end

end

end

hostSlaveMuxBI u_hostSlaveMuxBI (

hostSlaveMuxBI u_hostSlaveMuxBI (

  .dataIn(dataIn),

  .dataIn(dataIn),

  .dataOut(dataOut),

  .dataOut(dataOut),

  .writeEn(writeEn),

  .writeEn(writeEn),

  .strobe_i(strobe_i),

  .strobe_i(strobe_i),

  .clk(clk),

  .clk(clk),

  .rst(rst),

  .rst(rst),

  .hostMode(hostMode),

  .hostMode(hostMode),

  .hostSlaveMuxSel(hostSlaveMuxSel)  );

  .hostSlaveMuxSel(hostSlaveMuxSel)  );