|
|
// File : ../RTL/serialInterfaceEngine/processRxBit.v
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// File : ../RTL/serialInterfaceEngine/processRxBit.v
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// Generated : 10/06/06 19:35:28
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// Generated : 10/15/06 20:31:21
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// From : ../RTL/serialInterfaceEngine/processRxBit.asf
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// From : ../RTL/serialInterfaceEngine/processRxBit.asf
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// By : FSM2VHDL ver. 5.0.0.9
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// By : FSM2VHDL ver. 5.0.0.9
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|
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// processrxbit
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//// processrxbit
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//// ////
|
//// ////
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//// This file is part of the usbhostslave opencores effort.
|
//// This file is part of the usbhostslave opencores effort.
|
//// http://www.opencores.org/cores/usbhostslave/ ////
|
//// http://www.opencores.org/cores/usbhostslave/ ////
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//// ////
|
//// ////
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//// Module Description: ////
|
//// Module Description: ////
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////
|
////
|
//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
|
////
|
////
|
//// ////
|
//// ////
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//// Author(s): ////
|
//// Author(s): ////
|
//// - Steve Fielding, sfielding@base2designs.com ////
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//// - Steve Fielding, sfielding@base2designs.com ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
|
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
`include "timescale.v"
|
`include "timescale.v"
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbSerialInterfaceEngine_h.v"
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module processRxBit (JBit, KBit, RxBitsIn, RxCtrlOut, RxDataOut, RxWireActive, clk, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst);
|
module processRxBit (JBit, KBit, RxBitsIn, RxCtrlOut, RxDataOut, RxWireActive, clk, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst);
|
input [1:0] JBit;
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input [1:0] JBit;
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input [1:0] KBit;
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input [1:0] KBit;
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input [1:0] RxBitsIn;
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input [1:0] RxBitsIn;
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input RxWireActive;
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input RxWireActive;
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input clk;
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input clk;
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input processRxBitsWEn;
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input processRxBitsWEn;
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input processRxByteRdy;
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input processRxByteRdy;
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input rst;
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input rst;
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output [7:0] RxCtrlOut;
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output [7:0] RxCtrlOut;
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output [7:0] RxDataOut;
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output [7:0] RxDataOut;
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output processRxBitRdy;
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output processRxBitRdy;
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output processRxByteWEn;
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output processRxByteWEn;
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output resumeDetected;
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output resumeDetected;
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|
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wire [1:0] JBit;
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wire [1:0] JBit;
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wire [1:0] KBit;
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wire [1:0] KBit;
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wire [1:0] RxBitsIn;
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wire [1:0] RxBitsIn;
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reg [7:0] RxCtrlOut, next_RxCtrlOut;
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reg [7:0] RxCtrlOut, next_RxCtrlOut;
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reg [7:0] RxDataOut, next_RxDataOut;
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reg [7:0] RxDataOut, next_RxDataOut;
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wire RxWireActive;
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wire RxWireActive;
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wire clk;
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wire clk;
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reg processRxBitRdy, next_processRxBitRdy;
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reg processRxBitRdy, next_processRxBitRdy;
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wire processRxBitsWEn;
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wire processRxBitsWEn;
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wire processRxByteRdy;
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wire processRxByteRdy;
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reg processRxByteWEn, next_processRxByteWEn;
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reg processRxByteWEn, next_processRxByteWEn;
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reg resumeDetected, next_resumeDetected;
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reg resumeDetected, next_resumeDetected;
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wire rst;
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wire rst;
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|
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// diagram signals declarations
|
// diagram signals declarations
|
reg [3:0]RXBitCount, next_RXBitCount;
|
reg [3:0]RXBitCount, next_RXBitCount;
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reg [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;
|
reg [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;
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reg [7:0]RXByte, next_RXByte;
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reg [7:0]RXByte, next_RXByte;
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reg [3:0]RXSameBitCount, next_RXSameBitCount;
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reg [3:0]RXSameBitCount, next_RXSameBitCount;
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reg [1:0]RxBits, next_RxBits;
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reg [1:0]RxBits, next_RxBits;
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reg bitStuffError, next_bitStuffError;
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reg bitStuffError, next_bitStuffError;
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reg [1:0]oldRXBits, next_oldRXBits;
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reg [1:0]oldRXBits, next_oldRXBits;
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reg [4:0]resumeWaitCnt, next_resumeWaitCnt;
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reg [4:0]resumeWaitCnt, next_resumeWaitCnt;
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|
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// BINARY ENCODED state machine: prRxBit
|
// BINARY ENCODED state machine: prRxBit
|
// State codes definitions:
|
// State codes definitions:
|
`define START 4'b0000
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`define START 4'b0000
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`define IDLE_FIRST_BIT 4'b0001
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`define IDLE_FIRST_BIT 4'b0001
|
`define WAIT_BITS 4'b0010
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`define WAIT_BITS 4'b0010
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`define IDLE_CHK_KBIT 4'b0011
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`define IDLE_CHK_KBIT 4'b0011
|
`define DATA_RX_LAST_BIT 4'b0100
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`define DATA_RX_LAST_BIT 4'b0100
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`define DATA_RX_CHK_SE0 4'b0101
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`define DATA_RX_CHK_SE0 4'b0101
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`define DATA_RX_DATA_DESTUFF 4'b0110
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`define DATA_RX_DATA_DESTUFF 4'b0110
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`define DATA_RX_BYTE_SEND2 4'b0111
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`define DATA_RX_BYTE_SEND2 4'b0111
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`define DATA_RX_BYTE_WAIT_RDY 4'b1000
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`define DATA_RX_BYTE_WAIT_RDY 4'b1000
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`define RES_RX_CHK 4'b1001
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`define RES_RX_CHK 4'b1001
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`define DATA_RX_ERROR_CHK_RES 4'b1010
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`define DATA_RX_ERROR_CHK_RES 4'b1010
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`define RES_END_CHK1 4'b1011
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`define RES_END_CHK1 4'b1011
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`define IDLE_WAIT_PRB_RDY 4'b1100
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`define IDLE_WAIT_PRB_RDY 4'b1100
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`define DATA_RX_WAIT_PRB_RDY 4'b1101
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`define DATA_RX_WAIT_PRB_RDY 4'b1101
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`define DATA_RX_ERROR_WAIT_RDY 4'b1110
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`define DATA_RX_ERROR_WAIT_RDY 4'b1110
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reg [3:0] CurrState_prRxBit;
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reg [3:0] CurrState_prRxBit;
|
reg [3:0] NextState_prRxBit;
|
reg [3:0] NextState_prRxBit;
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|
|
|
|
//--------------------------------------------------------------------
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//--------------------------------------------------------------------
|
// Machine: prRxBit
|
// Machine: prRxBit
|
//--------------------------------------------------------------------
|
//--------------------------------------------------------------------
|
//----------------------------------
|
//----------------------------------
|
// Next State Logic (combinatorial)
|
// Next State Logic (combinatorial)
|
//----------------------------------
|
//----------------------------------
|
always @ (RxBitsIn or RxBits or oldRXBits or RXSameBitCount or RXBitCount or RXByte or JBit or KBit or resumeWaitCnt or processRxBitsWEn or RXBitStMachCurrState or RxWireActive or processRxByteRdy or bitStuffError or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or processRxBitRdy or CurrState_prRxBit)
|
always @ (RxBitsIn or RxBits or oldRXBits or RXSameBitCount or RXBitCount or RXByte or JBit or KBit or resumeWaitCnt or processRxBitsWEn or RXBitStMachCurrState or RxWireActive or processRxByteRdy or bitStuffError or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or processRxBitRdy or CurrState_prRxBit)
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begin : prRxBit_NextState
|
begin : prRxBit_NextState
|
NextState_prRxBit <= CurrState_prRxBit;
|
NextState_prRxBit <= CurrState_prRxBit;
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// Set default values for outputs and signals
|
// Set default values for outputs and signals
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next_processRxByteWEn <= processRxByteWEn;
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next_processRxByteWEn <= processRxByteWEn;
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next_RxCtrlOut <= RxCtrlOut;
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next_RxCtrlOut <= RxCtrlOut;
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next_RxDataOut <= RxDataOut;
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next_RxDataOut <= RxDataOut;
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next_resumeDetected <= resumeDetected;
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next_resumeDetected <= resumeDetected;
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next_RXBitStMachCurrState <= RXBitStMachCurrState;
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next_RXBitStMachCurrState <= RXBitStMachCurrState;
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next_RxBits <= RxBits;
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next_RxBits <= RxBits;
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next_RXSameBitCount <= RXSameBitCount;
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next_RXSameBitCount <= RXSameBitCount;
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next_RXBitCount <= RXBitCount;
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next_RXBitCount <= RXBitCount;
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next_oldRXBits <= oldRXBits;
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next_oldRXBits <= oldRXBits;
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next_RXByte <= RXByte;
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next_RXByte <= RXByte;
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next_bitStuffError <= bitStuffError;
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next_bitStuffError <= bitStuffError;
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next_resumeWaitCnt <= resumeWaitCnt;
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next_resumeWaitCnt <= resumeWaitCnt;
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next_processRxBitRdy <= processRxBitRdy;
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next_processRxBitRdy <= processRxBitRdy;
|
case (CurrState_prRxBit)
|
case (CurrState_prRxBit)
|
`START:
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`START:
|
begin
|
begin
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next_processRxByteWEn <= 1'b0;
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next_processRxByteWEn <= 1'b0;
|
next_RxCtrlOut <= 8'h00;
|
next_RxCtrlOut <= 8'h00;
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next_RxDataOut <= 8'h00;
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next_RxDataOut <= 8'h00;
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next_resumeDetected <= 1'b0;
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next_resumeDetected <= 1'b0;
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next_RXBitStMachCurrState <= `IDLE_BIT_ST;
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next_RXBitStMachCurrState <= `IDLE_BIT_ST;
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next_RxBits <= 2'b00;
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next_RxBits <= 2'b00;
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next_RXSameBitCount <= 4'h0;
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next_RXSameBitCount <= 4'h0;
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next_RXBitCount <= 4'h0;
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next_RXBitCount <= 4'h0;
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next_oldRXBits <= 2'b00;
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next_oldRXBits <= 2'b00;
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next_RXByte <= 8'h00;
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next_RXByte <= 8'h00;
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next_bitStuffError <= 1'b0;
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next_bitStuffError <= 1'b0;
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next_resumeWaitCnt <= 5'h0;
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next_resumeWaitCnt <= 5'h0;
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next_processRxBitRdy <= 1'b1;
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next_processRxBitRdy <= 1'b1;
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NextState_prRxBit <= `WAIT_BITS;
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NextState_prRxBit <= `WAIT_BITS;
|
end
|
end
|
`WAIT_BITS:
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`WAIT_BITS:
|
if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))
|
if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))
|
begin
|
begin
|
NextState_prRxBit <= `RES_RX_CHK;
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NextState_prRxBit <= `RES_RX_CHK;
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next_RxBits <= RxBitsIn;
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next_RxBits <= RxBitsIn;
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next_processRxBitRdy <= 1'b0;
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next_processRxBitRdy <= 1'b0;
|
end
|
end
|
else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))
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else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))
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begin
|
begin
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NextState_prRxBit <= `DATA_RX_CHK_SE0;
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NextState_prRxBit <= `DATA_RX_CHK_SE0;
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next_RxBits <= RxBitsIn;
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next_RxBits <= RxBitsIn;
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next_processRxBitRdy <= 1'b0;
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next_processRxBitRdy <= 1'b0;
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end
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end
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else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))
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else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))
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begin
|
begin
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NextState_prRxBit <= `IDLE_CHK_KBIT;
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NextState_prRxBit <= `IDLE_CHK_KBIT;
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next_RxBits <= RxBitsIn;
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next_RxBits <= RxBitsIn;
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next_processRxBitRdy <= 1'b0;
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next_processRxBitRdy <= 1'b0;
|
end
|
end
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else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))
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else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))
|
begin
|
begin
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NextState_prRxBit <= `RES_END_CHK1;
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NextState_prRxBit <= `RES_END_CHK1;
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next_RxBits <= RxBitsIn;
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next_RxBits <= RxBitsIn;
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next_processRxBitRdy <= 1'b0;
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next_processRxBitRdy <= 1'b0;
|
end
|
end
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`IDLE_FIRST_BIT:
|
`IDLE_FIRST_BIT:
|
begin
|
begin
|
next_processRxByteWEn <= 1'b0;
|
next_processRxByteWEn <= 1'b0;
|
next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
|
next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
|
next_RXSameBitCount <= 4'h0;
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next_RXSameBitCount <= 4'h0;
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next_RXBitCount <= 4'h1;
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next_RXBitCount <= 4'h1;
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next_oldRXBits <= RxBits;
|
next_oldRXBits <= RxBits;
|
//zero is always the first RZ data bit of a new packet
|
//zero is always the first RZ data bit of a new packet
|
next_RXByte <= 8'h00;
|
next_RXByte <= 8'h00;
|
NextState_prRxBit <= `WAIT_BITS;
|
NextState_prRxBit <= `WAIT_BITS;
|
next_processRxBitRdy <= 1'b1;
|
next_processRxBitRdy <= 1'b1;
|
end
|
end
|
`IDLE_CHK_KBIT:
|
`IDLE_CHK_KBIT:
|
if ((RxBits == KBit) && (RxWireActive == 1'b1))
|
if ((RxBits == KBit) && (RxWireActive == 1'b1))
|
NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
|
NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
|
else
|
else
|
begin
|
begin
|
NextState_prRxBit <= `WAIT_BITS;
|
NextState_prRxBit <= `WAIT_BITS;
|
next_processRxBitRdy <= 1'b1;
|
next_processRxBitRdy <= 1'b1;
|
end
|
end
|
`IDLE_WAIT_PRB_RDY:
|
`IDLE_WAIT_PRB_RDY:
|
if (processRxByteRdy == 1'b1)
|
if (processRxByteRdy == 1'b1)
|
begin
|
begin
|
NextState_prRxBit <= `IDLE_FIRST_BIT;
|
NextState_prRxBit <= `IDLE_FIRST_BIT;
|
next_RxDataOut <= 8'h00;
|
next_RxDataOut <= 8'h00;
|
//redundant data
|
//redundant data
|
next_RxCtrlOut <= `DATA_START;
|
next_RxCtrlOut <= `DATA_START;
|
//start of packet
|
//start of packet
|
next_processRxByteWEn <= 1'b1;
|
next_processRxByteWEn <= 1'b1;
|
end
|
end
|
`DATA_RX_LAST_BIT:
|
`DATA_RX_LAST_BIT:
|
begin
|
begin
|
next_processRxByteWEn <= 1'b0;
|
next_processRxByteWEn <= 1'b0;
|
next_RXBitStMachCurrState <= `IDLE_BIT_ST;
|
next_RXBitStMachCurrState <= `IDLE_BIT_ST;
|
NextState_prRxBit <= `WAIT_BITS;
|
NextState_prRxBit <= `WAIT_BITS;
|
next_processRxBitRdy <= 1'b1;
|
next_processRxBitRdy <= 1'b1;
|
end
|
end
|
`DATA_RX_CHK_SE0:
|
`DATA_RX_CHK_SE0:
|
begin
|
begin
|
next_bitStuffError <= 1'b0;
|
next_bitStuffError <= 1'b0;
|
if (RxBits == `SE0)
|
if (RxBits == `SE0)
|
NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
|
NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
|
else
|
else
|
begin
|
begin
|
NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
|
NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
|
if (RxBits == oldRXBits) //if the current 'RxBits' are the same as the old 'RxBits', then
|
if (RxBits == oldRXBits) //if the current 'RxBits' are the same as the old 'RxBits', then
|
begin
|
begin
|
next_RXSameBitCount <= RXSameBitCount + 1'b1;
|
next_RXSameBitCount <= RXSameBitCount + 1'b1;
|
//inc 'RXSameBitCount'
|
//inc 'RXSameBitCount'
|
if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 6 there has been a bit stuff error
|
if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 6 there has been a bit stuff error
|
next_bitStuffError <= 1'b1;
|
next_bitStuffError <= 1'b1;
|
//flag 'bitStuffError'
|
//flag 'bitStuffError'
|
else //else no bit stuffing error
|
else //else no bit stuffing error
|
begin
|
begin
|
next_RXBitCount <= RXBitCount + 1'b1;
|
next_RXBitCount <= RXBitCount + 1'b1;
|
if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin
|
if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin
|
next_processRxBitRdy <= 1'b1;
|
next_processRxBitRdy <= 1'b1;
|
//early indication of ready
|
//early indication of ready
|
end
|
end
|
next_RXByte <= { 1'b1, RXByte[7:1]};
|
next_RXByte <= { 1'b1, RXByte[7:1]};
|
//RZ bit = 1 (ie no change in 'RxBits')
|
//RZ bit = 1 (ie no change in 'RxBits')
|
end
|
end
|
end
|
end
|
else //else current 'RxBits' are different from old 'RxBits'
|
else //else current 'RxBits' are different from old 'RxBits'
|
begin
|
begin
|
if (RXSameBitCount != `MAX_CONSEC_SAME_BITS) //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
|
if (RXSameBitCount != `MAX_CONSEC_SAME_BITS) //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
|
begin
|
begin
|
next_RXBitCount <= RXBitCount + 1'b1;
|
next_RXBitCount <= RXBitCount + 1'b1;
|
if (RXBitCount != 4'h7) begin
|
if (RXBitCount != 4'h7) begin
|
next_processRxBitRdy <= 1'b1;
|
next_processRxBitRdy <= 1'b1;
|
//early indication of ready
|
//early indication of ready
|
end
|
end
|
next_RXByte <= {1'b0, RXByte[7:1]};
|
next_RXByte <= {1'b0, RXByte[7:1]};
|
//RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')
|
//RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')
|
end
|
end
|
next_RXSameBitCount <= 4'h0;
|
next_RXSameBitCount <= 4'h0;
|
//reset 'RXSameBitCount'
|
//reset 'RXSameBitCount'
|
end
|
end
|
next_oldRXBits <= RxBits;
|
next_oldRXBits <= RxBits;
|
end
|
end
|
end
|
end
|
`DATA_RX_WAIT_PRB_RDY:
|
`DATA_RX_WAIT_PRB_RDY:
|
if (processRxByteRdy == 1'b1)
|
if (processRxByteRdy == 1'b1)
|
begin
|
begin
|
NextState_prRxBit <= `DATA_RX_LAST_BIT;
|
NextState_prRxBit <= `DATA_RX_LAST_BIT;
|
next_RxDataOut <= 8'h00;
|
next_RxDataOut <= 8'h00;
|
//redundant data
|
//redundant data
|
next_RxCtrlOut <= `DATA_STOP;
|
next_RxCtrlOut <= `DATA_STOP;
|
//end of packet
|
//end of packet
|
next_processRxByteWEn <= 1'b1;
|
next_processRxByteWEn <= 1'b1;
|
end
|
end
|
`DATA_RX_DATA_DESTUFF:
|
`DATA_RX_DATA_DESTUFF:
|
if (RXBitCount == 4'h8 & bitStuffError == 1'b0)
|
if (RXBitCount == 4'h8 & bitStuffError == 1'b0)
|
NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
|
NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
|
else if (bitStuffError == 1'b1)
|
else if (bitStuffError == 1'b1)
|
NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
|
NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
|
else
|
else
|
begin
|
begin
|
NextState_prRxBit <= `WAIT_BITS;
|
NextState_prRxBit <= `WAIT_BITS;
|
next_processRxBitRdy <= 1'b1;
|
next_processRxBitRdy <= 1'b1;
|
end
|
end
|
`DATA_RX_BYTE_SEND2:
|
`DATA_RX_BYTE_SEND2:
|
begin
|
begin
|
next_processRxByteWEn <= 1'b0;
|
next_processRxByteWEn <= 1'b0;
|
NextState_prRxBit <= `WAIT_BITS;
|
NextState_prRxBit <= `WAIT_BITS;
|
next_processRxBitRdy <= 1'b1;
|
next_processRxBitRdy <= 1'b1;
|
end
|
end
|
`DATA_RX_BYTE_WAIT_RDY:
|
`DATA_RX_BYTE_WAIT_RDY:
|
if (processRxByteRdy == 1'b1)
|
if (processRxByteRdy == 1'b1)
|
begin
|
begin
|
NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
|
NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
|
next_RXBitCount <= 4'h0;
|
next_RXBitCount <= 4'h0;
|
next_RxDataOut <= RXByte;
|
next_RxDataOut <= RXByte;
|
next_RxCtrlOut <= `DATA_STREAM;
|
next_RxCtrlOut <= `DATA_STREAM;
|
next_processRxByteWEn <= 1'b1;
|
next_processRxByteWEn <= 1'b1;
|
end
|
end
|
`DATA_RX_ERROR_CHK_RES:
|
`DATA_RX_ERROR_CHK_RES:
|
begin
|
begin
|
next_processRxByteWEn <= 1'b0;
|
next_processRxByteWEn <= 1'b0;
|
if (RxBits == JBit) //if current bit is a JBit, then
|
if (RxBits == JBit) //if current bit is a JBit, then
|
next_RXBitStMachCurrState <= `IDLE_BIT_ST;
|
next_RXBitStMachCurrState <= `IDLE_BIT_ST;
|
//next state is idle
|
//next state is idle
|
else //else
|
else //else
|
begin
|
begin
|
next_RXBitStMachCurrState <= `WAIT_RESUME_ST;
|
next_RXBitStMachCurrState <= `WAIT_RESUME_ST;
|
//check for resume
|
//check for resume
|
next_resumeWaitCnt <= 5'h0;
|
next_resumeWaitCnt <= 5'h0;
|
end
|
end
|
NextState_prRxBit <= `WAIT_BITS;
|
NextState_prRxBit <= `WAIT_BITS;
|
next_processRxBitRdy <= 1'b1;
|
next_processRxBitRdy <= 1'b1;
|
end
|
end
|
`DATA_RX_ERROR_WAIT_RDY:
|
`DATA_RX_ERROR_WAIT_RDY:
|
if (processRxByteRdy == 1'b1)
|
if (processRxByteRdy == 1'b1)
|
begin
|
begin
|
NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
|
NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
|
next_RxDataOut <= 8'h00;
|
next_RxDataOut <= 8'h00;
|
//redundant data
|
//redundant data
|
next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
|
next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
|
next_processRxByteWEn <= 1'b1;
|
next_processRxByteWEn <= 1'b1;
|
end
|
end
|
`RES_RX_CHK:
|
`RES_RX_CHK:
|
begin
|
begin
|
if (RxBits != KBit) //can only be a resume if line remains in Kbit state
|
if (RxBits != KBit) //can only be a resume if line remains in Kbit state
|
next_RXBitStMachCurrState <= `IDLE_BIT_ST;
|
next_RXBitStMachCurrState <= `IDLE_BIT_ST;
|
else
|
else
|
begin
|
begin
|
next_resumeWaitCnt <= resumeWaitCnt + 1'b1;
|
next_resumeWaitCnt <= resumeWaitCnt + 1'b1;
|
//if we've waited long enough, then
|
//if we've waited long enough, then
|
if (resumeWaitCnt == `RESUME_RX_WAIT_TIME)
|
if (resumeWaitCnt == `RESUME_RX_WAIT_TIME)
|
begin
|
begin
|
next_RXBitStMachCurrState <= `RESUME_END_WAIT_ST;
|
next_RXBitStMachCurrState <= `RESUME_END_WAIT_ST;
|
next_resumeDetected <= 1'b1;
|
next_resumeDetected <= 1'b1;
|
//report resume detected
|
//report resume detected
|
end
|
end
|
end
|
end
|
NextState_prRxBit <= `WAIT_BITS;
|
NextState_prRxBit <= `WAIT_BITS;
|
next_processRxBitRdy <= 1'b1;
|
next_processRxBitRdy <= 1'b1;
|
end
|
end
|
`RES_END_CHK1:
|
`RES_END_CHK1:
|
begin
|
begin
|
if (RxBits != KBit) //line must leave KBit state for the end of resume
|
if (RxBits != KBit) //line must leave KBit state for the end of resume
|
begin
|
begin
|
next_RXBitStMachCurrState <= `IDLE_BIT_ST;
|
next_RXBitStMachCurrState <= `IDLE_BIT_ST;
|
next_resumeDetected <= 1'b0;
|
next_resumeDetected <= 1'b0;
|
//clear resume detected flag
|
//clear resume detected flag
|
end
|
end
|
NextState_prRxBit <= `WAIT_BITS;
|
NextState_prRxBit <= `WAIT_BITS;
|
next_processRxBitRdy <= 1'b1;
|
next_processRxBitRdy <= 1'b1;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
//----------------------------------
|
//----------------------------------
|
// Current State Logic (sequential)
|
// Current State Logic (sequential)
|
//----------------------------------
|
//----------------------------------
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin : prRxBit_CurrentState
|
begin : prRxBit_CurrentState
|
if (rst)
|
if (rst)
|
CurrState_prRxBit <= `START;
|
CurrState_prRxBit <= `START;
|
else
|
else
|
CurrState_prRxBit <= NextState_prRxBit;
|
CurrState_prRxBit <= NextState_prRxBit;
|
end
|
end
|
|
|
//----------------------------------
|
//----------------------------------
|
// Registered outputs logic
|
// Registered outputs logic
|
//----------------------------------
|
//----------------------------------
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin : prRxBit_RegOutput
|
begin : prRxBit_RegOutput
|
if (rst)
|
if (rst)
|
begin
|
begin
|
RXBitStMachCurrState <= `IDLE_BIT_ST;
|
RXBitStMachCurrState <= `IDLE_BIT_ST;
|
RxBits <= 2'b00;
|
RxBits <= 2'b00;
|
RXSameBitCount <= 4'h0;
|
RXSameBitCount <= 4'h0;
|
RXBitCount <= 4'h0;
|
RXBitCount <= 4'h0;
|
oldRXBits <= 2'b00;
|
oldRXBits <= 2'b00;
|
RXByte <= 8'h00;
|
RXByte <= 8'h00;
|
bitStuffError <= 1'b0;
|
bitStuffError <= 1'b0;
|
resumeWaitCnt <= 5'h0;
|
resumeWaitCnt <= 5'h0;
|
processRxByteWEn <= 1'b0;
|
processRxByteWEn <= 1'b0;
|
RxCtrlOut <= 8'h00;
|
RxCtrlOut <= 8'h00;
|
RxDataOut <= 8'h00;
|
RxDataOut <= 8'h00;
|
resumeDetected <= 1'b0;
|
resumeDetected <= 1'b0;
|
processRxBitRdy <= 1'b1;
|
processRxBitRdy <= 1'b1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
RXBitStMachCurrState <= next_RXBitStMachCurrState;
|
RXBitStMachCurrState <= next_RXBitStMachCurrState;
|
RxBits <= next_RxBits;
|
RxBits <= next_RxBits;
|
RXSameBitCount <= next_RXSameBitCount;
|
RXSameBitCount <= next_RXSameBitCount;
|
RXBitCount <= next_RXBitCount;
|
RXBitCount <= next_RXBitCount;
|
oldRXBits <= next_oldRXBits;
|
oldRXBits <= next_oldRXBits;
|
RXByte <= next_RXByte;
|
RXByte <= next_RXByte;
|
bitStuffError <= next_bitStuffError;
|
bitStuffError <= next_bitStuffError;
|
resumeWaitCnt <= next_resumeWaitCnt;
|
resumeWaitCnt <= next_resumeWaitCnt;
|
processRxByteWEn <= next_processRxByteWEn;
|
processRxByteWEn <= next_processRxByteWEn;
|
RxCtrlOut <= next_RxCtrlOut;
|
RxCtrlOut <= next_RxCtrlOut;
|
RxDataOut <= next_RxDataOut;
|
RxDataOut <= next_RxDataOut;
|
resumeDetected <= next_resumeDetected;
|
resumeDetected <= next_resumeDetected;
|
processRxBitRdy <= next_processRxBitRdy;
|
processRxBitRdy <= next_processRxBitRdy;
|
end
|
end
|
end
|
end
|
|
|
|
|
