//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// readUSBWireData.v ////
|
//// readUSBWireData.v ////
|
//// ////
|
//// ////
|
//// This file is part of the usbhostslave opencores effort.
|
//// This file is part of the usbhostslave opencores effort.
|
//// <http://www.opencores.org/cores//> ////
|
//// <http://www.opencores.org/cores//> ////
|
//// ////
|
//// ////
|
//// Module Description: ////
|
//// Module Description: ////
|
//// This module reads data from the differential USB data lines
|
//// This module reads data from the differential USB data lines
|
//// and writes into a 4 entry FIFO. The data is read from
|
//// and writes into a 4 entry FIFO. The data is read from
|
//// the fifo and output from the module when the higher level
|
//// the fifo and output from the module when the higher level
|
//// state machine is ready to receive the data.
|
//// state machine is ready to receive the data.
|
//// This module must recover the clock phase from the incoming
|
//// This module must recover the clock phase from the incoming
|
//// USB data. 'sampleCnt' is reset to zero whenever a RX data
|
//// USB data. 'sampleCnt' is reset to zero whenever a RX data
|
//// edge is detected. Note that due to metastability the data
|
//// edge is detected. Note that due to metastability the data
|
//// at the edge may not be registered correctly, but this does
|
//// at the edge may not be registered correctly, but this does
|
//// not matter. All that matters is that an edge was detected. The
|
//// not matter. All that matters is that an edge was detected. The
|
//// data will be accurately sampled in the middle of the USB bit
|
//// data will be accurately sampled in the middle of the USB bit
|
//// period without metastability issues.
|
//// period without metastability issues.
|
//// After the edge detect, 'sampleCnt' is incremented at every clock
|
//// After the edge detect, 'sampleCnt' is incremented at every clock
|
//// tick, and when it indicates the middle of a USB bit period
|
//// tick, and when it indicates the middle of a USB bit period
|
//// the RX data is sampled and written to the input buffer.
|
//// the RX data is sampled and written to the input buffer.
|
//// Single clock tick adjustments to 'sampleCnt' can be made at
|
//// Single clock tick adjustments to 'sampleCnt' can be made at
|
//// every RX data edge detect without double sampling the incoming
|
//// every RX data edge detect without double sampling the incoming
|
//// data. However, the first RX data bit in a packet may cause
|
//// data. However, the first RX data bit in a packet may cause
|
//// 'sampleCnt' to be adjusted by a value greater than a single
|
//// 'sampleCnt' to be adjusted by a value greater than a single
|
//// clock tick, and this can result in double sampling of the
|
//// clock tick, and this can result in double sampling of the
|
//// first data bit a RX packet. This
|
//// first data bit a RX packet. This
|
//// double sampled data must be rejected by the higher level module.
|
//// double sampled data must be rejected by the higher level module.
|
//// This is achieved by
|
//// This is achieved by
|
//// qualifying the outgoing data with 'RxWireActive'. Thus
|
//// qualifying the outgoing data with 'RxWireActive'. Thus
|
//// the first data bit in a RX packet may be double sampled
|
//// the first data bit in a RX packet may be double sampled
|
//// as the clock recovery mechanism synchronizes to 'RxBitsIn'
|
//// as the clock recovery mechanism synchronizes to 'RxBitsIn'
|
//// but the double sampled data will be rejected by the higher
|
//// but the double sampled data will be rejected by the higher
|
//// level module.
|
//// level module.
|
////
|
////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
////
|
////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Steve Fielding, sfielding@base2designs.com ////
|
//// - Steve Fielding, sfielding@base2designs.com ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
|
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from <http://www.opencores.org/lgpl.shtml> ////
|
//// from <http://www.opencores.org/lgpl.shtml> ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
`include "timescale.v"
|
`include "timescale.v"
|
`include "usbSerialInterfaceEngine_h.v"
|
`include "usbSerialInterfaceEngine_h.v"
|
|
|
module readUSBWireData (RxBitsIn, RxDataInTick, RxBitsOut, SIERxRdyIn, SIERxWEn, fullSpeedRate, TxWireActiveDrive, clk, rst, noActivityTimeOut, RxWireActive, noActivityTimeOutEnable);
|
module readUSBWireData (RxBitsIn, RxDataInTick, RxBitsOut, SIERxRdyIn, SIERxWEn, fullSpeedRate, TxWireActiveDrive, clk, rst, noActivityTimeOut, RxWireActive, noActivityTimeOutEnable);
|
input [1:0] RxBitsIn;
|
input [1:0] RxBitsIn;
|
output RxDataInTick;
|
output RxDataInTick;
|
input SIERxRdyIn;
|
input SIERxRdyIn;
|
input clk;
|
input clk;
|
input fullSpeedRate;
|
input fullSpeedRate;
|
input rst;
|
input rst;
|
input TxWireActiveDrive;
|
input TxWireActiveDrive;
|
output [1:0] RxBitsOut;
|
output [1:0] RxBitsOut;
|
output SIERxWEn;
|
output SIERxWEn;
|
output noActivityTimeOut;
|
output noActivityTimeOut;
|
output RxWireActive;
|
output RxWireActive;
|
input noActivityTimeOutEnable;
|
input noActivityTimeOutEnable;
|
|
|
wire [1:0] RxBitsIn;
|
wire [1:0] RxBitsIn;
|
reg RxDataInTick;
|
reg RxDataInTick;
|
wire SIERxRdyIn;
|
wire SIERxRdyIn;
|
wire clk;
|
wire clk;
|
wire fullSpeedRate;
|
wire fullSpeedRate;
|
wire rst;
|
wire rst;
|
reg [1:0] RxBitsOut;
|
reg [1:0] RxBitsOut;
|
reg SIERxWEn;
|
reg SIERxWEn;
|
reg noActivityTimeOut;
|
reg noActivityTimeOut;
|
reg RxWireActive;
|
reg RxWireActive;
|
wire noActivityTimeOutEnable;
|
wire noActivityTimeOutEnable;
|
|
|
// local registers
|
// local registers
|
reg [2:0]buffer0;
|
reg [2:0]buffer0;
|
reg [2:0]buffer1;
|
reg [2:0]buffer1;
|
reg [2:0]buffer2;
|
reg [2:0]buffer2;
|
reg [2:0]buffer3;
|
reg [2:0]buffer3;
|
reg [2:0]bufferCnt;
|
reg [2:0]bufferCnt;
|
reg [1:0]bufferInIndex;
|
reg [1:0]bufferInIndex;
|
reg [1:0]bufferOutIndex;
|
reg [1:0]bufferOutIndex;
|
reg decBufferCnt;
|
reg decBufferCnt;
|
reg [4:0]sampleCnt;
|
reg [4:0]sampleCnt;
|
reg incBufferCnt;
|
reg incBufferCnt;
|
reg [1:0]oldRxBitsIn;
|
reg [1:0]oldRxBitsIn;
|
reg [1:0] RxBitsInReg;
|
reg [1:0] RxBitsInReg;
|
reg [15:0] timeOutCnt;
|
reg [15:0] timeOutCnt;
|
reg [7:0] rxActiveCnt;
|
reg [7:0] rxActiveCnt;
|
reg RxWireEdgeDetect;
|
reg RxWireEdgeDetect;
|
reg RxWireActiveReg;
|
reg RxWireActiveReg;
|
reg RxWireActiveReg2;
|
reg RxWireActiveReg2;
|
reg [1:0] RxBitsInSyncReg1;
|
reg [1:0] RxBitsInSyncReg1;
|
reg [1:0] RxBitsInSyncReg2;
|
reg [1:0] RxBitsInSyncReg2;
|
|
|
// buffer output state machine state codes:
|
// buffer output state machine state codes:
|
`define WAIT_BUFFER_NOT_EMPTY 2'b00
|
`define WAIT_BUFFER_NOT_EMPTY 2'b00
|
`define WAIT_SIE_RX_READY 2'b01
|
`define WAIT_SIE_RX_READY 2'b01
|
`define SIE_RX_WRITE 2'b10
|
`define SIE_RX_WRITE 2'b10
|
|
|
// re-synchronize incoming bits
|
// re-synchronize incoming bits
|
always @(posedge clk) begin
|
always @(posedge clk) begin
|
RxBitsInSyncReg1 <= RxBitsIn;
|
RxBitsInSyncReg1 <= RxBitsIn;
|
RxBitsInSyncReg2 <= RxBitsInSyncReg1;
|
RxBitsInSyncReg2 <= RxBitsInSyncReg1;
|
end
|
end
|
|
|
reg [1:0] bufferOutStMachCurrState;
|
reg [1:0] bufferOutStMachCurrState;
|
|
|
|
|
always @(posedge clk) begin
|
always @(posedge clk) begin
|
if (rst == 1'b1)
|
if (rst == 1'b1)
|
begin
|
begin
|
bufferCnt <= 3'b000;
|
bufferCnt <= 3'b000;
|
end
|
end
|
else begin
|
else begin
|
if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
|
if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
|
bufferCnt <= bufferCnt + 1'b1;
|
bufferCnt <= bufferCnt + 1'b1;
|
else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
|
else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
|
bufferCnt <= bufferCnt - 1'b1;
|
bufferCnt <= bufferCnt - 1'b1;
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
//Perform line rate clock recovery
|
//Perform line rate clock recovery
|
//Recover the wire data, and store data to buffer
|
//Recover the wire data, and store data to buffer
|
always @(posedge clk) begin
|
always @(posedge clk) begin
|
if (rst == 1'b1)
|
if (rst == 1'b1)
|
begin
|
begin
|
sampleCnt <= 5'b00000;
|
sampleCnt <= 5'b00000;
|
incBufferCnt <= 1'b0;
|
incBufferCnt <= 1'b0;
|
bufferInIndex <= 2'b00;
|
bufferInIndex <= 2'b00;
|
buffer0 <= 3'b000;
|
buffer0 <= 3'b000;
|
buffer1 <= 3'b000;
|
buffer1 <= 3'b000;
|
buffer2 <= 3'b000;
|
buffer2 <= 3'b000;
|
buffer3 <= 3'b000;
|
buffer3 <= 3'b000;
|
RxDataInTick <= 1'b0;
|
RxDataInTick <= 1'b0;
|
RxWireEdgeDetect <= 1'b0;
|
RxWireEdgeDetect <= 1'b0;
|
RxWireActiveReg <= 1'b0;
|
RxWireActiveReg <= 1'b0;
|
RxWireActiveReg2 <= 1'b0;
|
RxWireActiveReg2 <= 1'b0;
|
end
|
end
|
else begin
|
else begin
|
RxWireActiveReg2 <= RxWireActiveReg; //Delay 'RxWireActiveReg' until after 'sampleCnt' has been reset
|
RxWireActiveReg2 <= RxWireActiveReg; //Delay 'RxWireActiveReg' until after 'sampleCnt' has been reset
|
RxBitsInReg <= RxBitsInSyncReg2;
|
RxBitsInReg <= RxBitsInSyncReg2;
|
oldRxBitsIn <= RxBitsInReg;
|
oldRxBitsIn <= RxBitsInReg;
|
incBufferCnt <= 1'b0; //default value
|
incBufferCnt <= 1'b0; //default value
|
if ( (TxWireActiveDrive == 1'b0) && (RxBitsInSyncReg2 != RxBitsInReg)) begin //if edge detected then
|
if ( (TxWireActiveDrive == 1'b0) && (RxBitsInSyncReg2 != RxBitsInReg)) begin //if edge detected then
|
sampleCnt <= 5'b00000;
|
sampleCnt <= 5'b00000;
|
RxWireEdgeDetect <= 1'b1; // flag receive activity
|
RxWireEdgeDetect <= 1'b1; // flag receive activity
|
RxWireActiveReg <= 1'b1;
|
RxWireActiveReg <= 1'b1;
|
rxActiveCnt <= 8'h00;
|
rxActiveCnt <= 8'h00;
|
end
|
end
|
else begin
|
else begin
|
sampleCnt <= sampleCnt + 1'b1;
|
sampleCnt <= sampleCnt + 1'b1;
|
RxWireEdgeDetect <= 1'b0;
|
RxWireEdgeDetect <= 1'b0;
|
rxActiveCnt <= rxActiveCnt + 1'b1;
|
rxActiveCnt <= rxActiveCnt + 1'b1;
|
//clear 'RxWireActiveReg' if no RX transitions for RX_EDGE_DET_TOUT USB bit periods
|
//clear 'RxWireActiveReg' if no RX transitions for RX_EDGE_DET_TOUT USB bit periods
|
if ( (fullSpeedRate == 1'b1 && rxActiveCnt == `RX_EDGE_DET_TOUT * `FS_OVER_SAMPLE_RATE)
|
if ( (fullSpeedRate == 1'b1 && rxActiveCnt == `RX_EDGE_DET_TOUT * `FS_OVER_SAMPLE_RATE)
|
|| (fullSpeedRate == 1'b0 && rxActiveCnt == `RX_EDGE_DET_TOUT * `LS_OVER_SAMPLE_RATE) )
|
|| (fullSpeedRate == 1'b0 && rxActiveCnt == `RX_EDGE_DET_TOUT * `LS_OVER_SAMPLE_RATE) )
|
RxWireActiveReg <= 1'b0;
|
RxWireActiveReg <= 1'b0;
|
end
|
end
|
if ( (fullSpeedRate == 1'b1 && sampleCnt[1:0] == 2'b10) || (fullSpeedRate == 1'b0 && sampleCnt == 5'b10000) )
|
if ( (fullSpeedRate == 1'b1 && sampleCnt[1:0] == 2'b10) || (fullSpeedRate == 1'b0 && sampleCnt == 5'b10000) )
|
begin
|
begin
|
RxDataInTick <= !RxDataInTick;
|
RxDataInTick <= !RxDataInTick;
|
if (TxWireActiveDrive != 1'b1) //do not read wire data when transmitter is active
|
if (TxWireActiveDrive != 1'b1) //do not read wire data when transmitter is active
|
begin
|
begin
|
incBufferCnt <= 1'b1;
|
incBufferCnt <= 1'b1;
|
bufferInIndex <= bufferInIndex + 1'b1;
|
bufferInIndex <= bufferInIndex + 1'b1;
|
case (bufferInIndex)
|
case (bufferInIndex)
|
2'b00 : buffer0 <= {RxWireActiveReg2, oldRxBitsIn};
|
2'b00 : buffer0 <= {RxWireActiveReg2, oldRxBitsIn};
|
2'b01 : buffer1 <= {RxWireActiveReg2, oldRxBitsIn};
|
2'b01 : buffer1 <= {RxWireActiveReg2, oldRxBitsIn};
|
2'b10 : buffer2 <= {RxWireActiveReg2, oldRxBitsIn};
|
2'b10 : buffer2 <= {RxWireActiveReg2, oldRxBitsIn};
|
2'b11 : buffer3 <= {RxWireActiveReg2, oldRxBitsIn};
|
2'b11 : buffer3 <= {RxWireActiveReg2, oldRxBitsIn};
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
//read from buffer, and output to SIEReceiver
|
//read from buffer, and output to SIEReceiver
|
always @(posedge clk) begin
|
always @(posedge clk) begin
|
if (rst == 1'b1)
|
if (rst == 1'b1)
|
begin
|
begin
|
decBufferCnt <= 1'b0;
|
decBufferCnt <= 1'b0;
|
bufferOutIndex <= 2'b00;
|
bufferOutIndex <= 2'b00;
|
RxBitsOut <= 2'b00;
|
RxBitsOut <= 2'b00;
|
SIERxWEn <= 1'b0;
|
SIERxWEn <= 1'b0;
|
bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
|
bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
|
end
|
end
|
else begin
|
else begin
|
case (bufferOutStMachCurrState)
|
case (bufferOutStMachCurrState)
|
`WAIT_BUFFER_NOT_EMPTY:
|
`WAIT_BUFFER_NOT_EMPTY:
|
begin
|
begin
|
if (bufferCnt != 3'b000)
|
if (bufferCnt != 3'b000)
|
bufferOutStMachCurrState <= `WAIT_SIE_RX_READY;
|
bufferOutStMachCurrState <= `WAIT_SIE_RX_READY;
|
end
|
end
|
`WAIT_SIE_RX_READY:
|
`WAIT_SIE_RX_READY:
|
begin
|
begin
|
if (SIERxRdyIn == 1'b1)
|
if (SIERxRdyIn == 1'b1)
|
begin
|
begin
|
SIERxWEn <= 1'b1;
|
SIERxWEn <= 1'b1;
|
bufferOutStMachCurrState <= `SIE_RX_WRITE;
|
bufferOutStMachCurrState <= `SIE_RX_WRITE;
|
decBufferCnt <= 1'b1;
|
decBufferCnt <= 1'b1;
|
bufferOutIndex <= bufferOutIndex + 1'b1;
|
bufferOutIndex <= bufferOutIndex + 1'b1;
|
case (bufferOutIndex)
|
case (bufferOutIndex)
|
2'b00 : begin RxBitsOut <= buffer0[1:0]; RxWireActive <= buffer0[2]; end
|
2'b00 : begin RxBitsOut <= buffer0[1:0]; RxWireActive <= buffer0[2]; end
|
2'b01 : begin RxBitsOut <= buffer1[1:0]; RxWireActive <= buffer1[2]; end
|
2'b01 : begin RxBitsOut <= buffer1[1:0]; RxWireActive <= buffer1[2]; end
|
2'b10 : begin RxBitsOut <= buffer2[1:0]; RxWireActive <= buffer2[2]; end
|
2'b10 : begin RxBitsOut <= buffer2[1:0]; RxWireActive <= buffer2[2]; end
|
2'b11 : begin RxBitsOut <= buffer3[1:0]; RxWireActive <= buffer3[2]; end
|
2'b11 : begin RxBitsOut <= buffer3[1:0]; RxWireActive <= buffer3[2]; end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
`SIE_RX_WRITE:
|
`SIE_RX_WRITE:
|
begin
|
begin
|
SIERxWEn <= 1'b0;
|
SIERxWEn <= 1'b0;
|
decBufferCnt <= 1'b0;
|
decBufferCnt <= 1'b0;
|
bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
|
bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
//generate 'noActivityTimeOut' pulse if no tx or rx activity for RX_PACKET_TOUT USB bit periods
|
//generate 'noActivityTimeOut' pulse if no tx or rx activity for RX_PACKET_TOUT USB bit periods
|
//'noActivityTimeOut' pulse can only be generated when the host or slave getPacket
|
//'noActivityTimeOut' pulse can only be generated when the host or slave getPacket
|
//process enables via 'noActivityTimeOutEnable' signal
|
//process enables via 'noActivityTimeOutEnable' signal
|
//'noActivityTimeOut' pulse is used by host and slave getPacket processes to determine if
|
//'noActivityTimeOut' pulse is used by host and slave getPacket processes to determine if
|
//there has been a response time out.
|
//there has been a response time out.
|
always @(posedge clk) begin
|
always @(posedge clk) begin
|
if (rst) begin
|
if (rst) begin
|
timeOutCnt <= 16'h0000;
|
timeOutCnt <= 16'h0000;
|
noActivityTimeOut <= 1'b0;
|
noActivityTimeOut <= 1'b0;
|
end
|
end
|
else begin
|
else begin
|
if (TxWireActiveDrive == 1'b1 || RxWireEdgeDetect == 1'b1 || noActivityTimeOutEnable == 1'b0)
|
if (TxWireActiveDrive == 1'b1 || RxWireEdgeDetect == 1'b1 || noActivityTimeOutEnable == 1'b0)
|
timeOutCnt <= 16'h0000;
|
timeOutCnt <= 16'h0000;
|
else
|
else
|
timeOutCnt <= timeOutCnt + 1'b1;
|
timeOutCnt <= timeOutCnt + 1'b1;
|
if ( (fullSpeedRate == 1'b1 && timeOutCnt == `RX_PACKET_TOUT * `FS_OVER_SAMPLE_RATE)
|
if ( (fullSpeedRate == 1'b1 && timeOutCnt == `RX_PACKET_TOUT * `FS_OVER_SAMPLE_RATE)
|
|| (fullSpeedRate == 1'b0 && timeOutCnt == `RX_PACKET_TOUT * `LS_OVER_SAMPLE_RATE) )
|
|| (fullSpeedRate == 1'b0 && timeOutCnt == `RX_PACKET_TOUT * `LS_OVER_SAMPLE_RATE) )
|
noActivityTimeOut <= 1'b1;
|
noActivityTimeOut <= 1'b1;
|
else
|
else
|
noActivityTimeOut <= 1'b0;
|
noActivityTimeOut <= 1'b0;
|
end
|
end
|
end
|
end
|
|
|
|
|
endmodule
|
endmodule
|
|
|