//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// USBSlaveControlBI.v ////
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//// USBSlaveControlBI.v ////
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//// ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// ////
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//// Module Description: ////
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//// Module Description: ////
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////
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////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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////
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////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// $Id: USBSlaveControlBI.v,v 1.2 2004-12-18 14:36:17 sfielding Exp $
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`timescale 1ns / 1ps
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1 2004/10/11 04:01:10 sfielding
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// Created
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//
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//
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`include "usbSlaveControl_h.v"
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`include "usbSlaveControl_h.v"
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|
|
module USBSlaveControlBI (address, dataIn, dataOut, writeEn,
|
module USBSlaveControlBI (address, dataIn, dataOut, writeEn,
|
strobe_i,
|
strobe_i,
|
clk, rst,
|
clk, rst,
|
SOFRxedIntOut, resetEventIntOut, resumeIntOut, transDoneIntOut, NAKSentIntOut,
|
SOFRxedIntOut, resetEventIntOut, resumeIntOut, transDoneIntOut, NAKSentIntOut,
|
endP0TransTypeReg, endP0NAKTransTypeReg,
|
endP0TransTypeReg, endP0NAKTransTypeReg,
|
endP1TransTypeReg, endP1NAKTransTypeReg,
|
endP1TransTypeReg, endP1NAKTransTypeReg,
|
endP2TransTypeReg, endP2NAKTransTypeReg,
|
endP2TransTypeReg, endP2NAKTransTypeReg,
|
endP3TransTypeReg, endP3NAKTransTypeReg,
|
endP3TransTypeReg, endP3NAKTransTypeReg,
|
endP0ControlReg,
|
endP0ControlReg,
|
endP1ControlReg,
|
endP1ControlReg,
|
endP2ControlReg,
|
endP2ControlReg,
|
endP3ControlReg,
|
endP3ControlReg,
|
EP0StatusReg,
|
EP0StatusReg,
|
EP1StatusReg,
|
EP1StatusReg,
|
EP2StatusReg,
|
EP2StatusReg,
|
EP3StatusReg,
|
EP3StatusReg,
|
SCAddrReg, frameNum,
|
SCAddrReg, frameNum,
|
connectStateIn,
|
connectStateIn,
|
SOFRxedIn, resetEventIn, resumeIntIn, transDoneIn, NAKSentIn,
|
SOFRxedIn, resetEventIn, resumeIntIn, transDoneIn, NAKSentIn,
|
slaveControlSelect,
|
slaveControlSelect,
|
clrEP0Ready, clrEP1Ready, clrEP2Ready, clrEP3Ready,
|
clrEP0Ready, clrEP1Ready, clrEP2Ready, clrEP3Ready,
|
TxLineState,
|
TxLineState,
|
LineDirectControlEn,
|
LineDirectControlEn,
|
fullSpeedPol,
|
fullSpeedPol,
|
fullSpeedRate,
|
fullSpeedRate,
|
SCGlobalEn
|
SCGlobalEn
|
);
|
);
|
input [4:0] address;
|
input [4:0] address;
|
input [7:0] dataIn;
|
input [7:0] dataIn;
|
input writeEn;
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input writeEn;
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input strobe_i;
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input strobe_i;
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input clk;
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input clk;
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input rst;
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input rst;
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output [7:0] dataOut;
|
output [7:0] dataOut;
|
output SOFRxedIntOut;
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output SOFRxedIntOut;
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output resetEventIntOut;
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output resetEventIntOut;
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output resumeIntOut;
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output resumeIntOut;
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output transDoneIntOut;
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output transDoneIntOut;
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output NAKSentIntOut;
|
output NAKSentIntOut;
|
|
|
input [1:0] endP0TransTypeReg;
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input [1:0] endP0TransTypeReg;
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input [1:0] endP0NAKTransTypeReg;
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input [1:0] endP0NAKTransTypeReg;
|
input [1:0] endP1TransTypeReg;
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input [1:0] endP1TransTypeReg;
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input [1:0] endP1NAKTransTypeReg;
|
input [1:0] endP1NAKTransTypeReg;
|
input [1:0] endP2TransTypeReg;
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input [1:0] endP2TransTypeReg;
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input [1:0] endP2NAKTransTypeReg;
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input [1:0] endP2NAKTransTypeReg;
|
input [1:0] endP3TransTypeReg;
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input [1:0] endP3TransTypeReg;
|
input [1:0] endP3NAKTransTypeReg;
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input [1:0] endP3NAKTransTypeReg;
|
output [3:0] endP0ControlReg;
|
output [3:0] endP0ControlReg;
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output [3:0] endP1ControlReg;
|
output [3:0] endP1ControlReg;
|
output [3:0] endP2ControlReg;
|
output [3:0] endP2ControlReg;
|
output [3:0] endP3ControlReg;
|
output [3:0] endP3ControlReg;
|
input [7:0] EP0StatusReg;
|
input [7:0] EP0StatusReg;
|
input [7:0] EP1StatusReg;
|
input [7:0] EP1StatusReg;
|
input [7:0] EP2StatusReg;
|
input [7:0] EP2StatusReg;
|
input [7:0] EP3StatusReg;
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input [7:0] EP3StatusReg;
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output [6:0] SCAddrReg;
|
output [6:0] SCAddrReg;
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input [10:0] frameNum;
|
input [10:0] frameNum;
|
input [1:0] connectStateIn;
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input [1:0] connectStateIn;
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input SOFRxedIn;
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input SOFRxedIn;
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input resetEventIn;
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input resetEventIn;
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input resumeIntIn;
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input resumeIntIn;
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input transDoneIn;
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input transDoneIn;
|
input NAKSentIn;
|
input NAKSentIn;
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input slaveControlSelect;
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input slaveControlSelect;
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input clrEP0Ready;
|
input clrEP0Ready;
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input clrEP1Ready;
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input clrEP1Ready;
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input clrEP2Ready;
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input clrEP2Ready;
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input clrEP3Ready;
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input clrEP3Ready;
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output [1:0] TxLineState;
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output [1:0] TxLineState;
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output LineDirectControlEn;
|
output LineDirectControlEn;
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output fullSpeedPol;
|
output fullSpeedPol;
|
output fullSpeedRate;
|
output fullSpeedRate;
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output SCGlobalEn;
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output SCGlobalEn;
|
|
|
wire [4:0] address;
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wire [4:0] address;
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wire [7:0] dataIn;
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wire [7:0] dataIn;
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wire writeEn;
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wire writeEn;
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wire strobe_i;
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wire strobe_i;
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wire clk;
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wire clk;
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wire rst;
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wire rst;
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reg [7:0] dataOut;
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reg [7:0] dataOut;
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|
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reg SOFRxedIntOut;
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reg SOFRxedIntOut;
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reg resetEventIntOut;
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reg resetEventIntOut;
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reg resumeIntOut;
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reg resumeIntOut;
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reg transDoneIntOut;
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reg transDoneIntOut;
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reg NAKSentIntOut;
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reg NAKSentIntOut;
|
|
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wire [1:0] endP0TransTypeReg;
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wire [1:0] endP0TransTypeReg;
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wire [1:0] endP0NAKTransTypeReg;
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wire [1:0] endP0NAKTransTypeReg;
|
wire [1:0] endP1TransTypeReg;
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wire [1:0] endP1TransTypeReg;
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wire [1:0] endP1NAKTransTypeReg;
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wire [1:0] endP1NAKTransTypeReg;
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wire [1:0] endP2TransTypeReg;
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wire [1:0] endP2TransTypeReg;
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wire [1:0] endP2NAKTransTypeReg;
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wire [1:0] endP2NAKTransTypeReg;
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wire [1:0] endP3TransTypeReg;
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wire [1:0] endP3TransTypeReg;
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wire [1:0] endP3NAKTransTypeReg;
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wire [1:0] endP3NAKTransTypeReg;
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reg [3:0] endP0ControlReg;
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reg [3:0] endP0ControlReg;
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reg [3:0] endP1ControlReg;
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reg [3:0] endP1ControlReg;
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reg [3:0] endP2ControlReg;
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reg [3:0] endP2ControlReg;
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reg [3:0] endP3ControlReg;
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reg [3:0] endP3ControlReg;
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wire [7:0] EP0StatusReg;
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wire [7:0] EP0StatusReg;
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wire [7:0] EP1StatusReg;
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wire [7:0] EP1StatusReg;
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wire [7:0] EP2StatusReg;
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wire [7:0] EP2StatusReg;
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wire [7:0] EP3StatusReg;
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wire [7:0] EP3StatusReg;
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reg [6:0] SCAddrReg;
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reg [6:0] SCAddrReg;
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reg [3:0] TxEndPReg;
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reg [3:0] TxEndPReg;
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wire [10:0] frameNum;
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wire [10:0] frameNum;
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wire [1:0] connectStateIn;
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wire [1:0] connectStateIn;
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|
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wire SOFRxedIn;
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wire SOFRxedIn;
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wire resetEventIn;
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wire resetEventIn;
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wire resumeIntIn;
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wire resumeIntIn;
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wire transDoneIn;
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wire transDoneIn;
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wire NAKSentIn;
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wire NAKSentIn;
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wire slaveControlSelect;
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wire slaveControlSelect;
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wire clrEP0Ready;
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wire clrEP0Ready;
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wire clrEP1Ready;
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wire clrEP1Ready;
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wire clrEP2Ready;
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wire clrEP2Ready;
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wire clrEP3Ready;
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wire clrEP3Ready;
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reg [1:0] TxLineState;
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reg [1:0] TxLineState;
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reg LineDirectControlEn;
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reg LineDirectControlEn;
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reg fullSpeedPol;
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reg fullSpeedPol;
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reg fullSpeedRate;
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reg fullSpeedRate;
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reg SCGlobalEn;
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reg SCGlobalEn;
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//internal wire and regs
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//internal wire and regs
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reg [5:0] SCControlReg;
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reg [5:0] SCControlReg;
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reg clrNAKReq;
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reg clrNAKReq;
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reg clrSOFReq;
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reg clrSOFReq;
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reg clrResetReq;
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reg clrResetReq;
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reg clrResInReq;
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reg clrResInReq;
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reg clrTransDoneReq;
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reg clrTransDoneReq;
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reg SOFRxedInt;
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reg SOFRxedInt;
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reg resetEventInt;
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reg resetEventInt;
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reg resumeInt;
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reg resumeInt;
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reg transDoneInt;
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reg transDoneInt;
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reg NAKSentInt;
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reg NAKSentInt;
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reg [4:0] interruptMaskReg;
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reg [4:0] interruptMaskReg;
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reg EP0SetReady;
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reg EP0SetReady;
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reg EP1SetReady;
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reg EP1SetReady;
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reg EP2SetReady;
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reg EP2SetReady;
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reg EP3SetReady;
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reg EP3SetReady;
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reg EP0SendStall;
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reg EP0SendStall;
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reg EP1SendStall;
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reg EP1SendStall;
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reg EP2SendStall;
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reg EP2SendStall;
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reg EP3SendStall;
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reg EP3SendStall;
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reg EP0DataSequence;
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reg EP0DataSequence;
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reg EP1DataSequence;
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reg EP1DataSequence;
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reg EP2DataSequence;
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reg EP2DataSequence;
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reg EP3DataSequence;
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reg EP3DataSequence;
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reg EP0Enable;
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reg EP0Enable;
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reg EP1Enable;
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reg EP1Enable;
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reg EP2Enable;
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reg EP2Enable;
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reg EP3Enable;
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reg EP3Enable;
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reg EP0Ready;
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reg EP0Ready;
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reg EP1Ready;
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reg EP1Ready;
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reg EP2Ready;
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reg EP2Ready;
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reg EP3Ready;
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reg EP3Ready;
|
|
|
|
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//sync write demux
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//sync write demux
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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clrNAKReq <= 1'b0;
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clrNAKReq <= 1'b0;
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clrSOFReq <= 1'b0;
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clrSOFReq <= 1'b0;
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clrResetReq <= 1'b0;
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clrResetReq <= 1'b0;
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clrResInReq <= 1'b0;
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clrResInReq <= 1'b0;
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clrTransDoneReq <= 1'b0;
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clrTransDoneReq <= 1'b0;
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EP0SetReady <= 1'b0;
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EP0SetReady <= 1'b0;
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EP1SetReady <= 1'b0;
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EP1SetReady <= 1'b0;
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EP2SetReady <= 1'b0;
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EP2SetReady <= 1'b0;
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EP3SetReady <= 1'b0;
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EP3SetReady <= 1'b0;
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if (writeEn == 1'b1 && strobe_i == 1'b1 && slaveControlSelect == 1'b1)
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if (writeEn == 1'b1 && strobe_i == 1'b1 && slaveControlSelect == 1'b1)
|
begin
|
begin
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case (address)
|
case (address)
|
`EP0_CTRL_REG : begin
|
`EP0_CTRL_REG : begin
|
EP0SendStall <= dataIn[3];
|
EP0SendStall <= dataIn[3];
|
EP0DataSequence <= dataIn[2];
|
EP0DataSequence <= dataIn[2];
|
EP0SetReady <= dataIn[1];
|
EP0SetReady <= dataIn[1];
|
EP0Enable <= dataIn[0];
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EP0Enable <= dataIn[0];
|
end
|
end
|
`EP1_CTRL_REG : begin
|
`EP1_CTRL_REG : begin
|
EP1SendStall <= dataIn[3];
|
EP1SendStall <= dataIn[3];
|
EP1DataSequence <= dataIn[2];
|
EP1DataSequence <= dataIn[2];
|
EP1SetReady <= dataIn[1];
|
EP1SetReady <= dataIn[1];
|
EP1Enable <= dataIn[0];
|
EP1Enable <= dataIn[0];
|
end
|
end
|
`EP2_CTRL_REG : begin
|
`EP2_CTRL_REG : begin
|
EP2SendStall <= dataIn[3];
|
EP2SendStall <= dataIn[3];
|
EP2DataSequence <= dataIn[2];
|
EP2DataSequence <= dataIn[2];
|
EP2SetReady <= dataIn[1];
|
EP2SetReady <= dataIn[1];
|
EP2Enable <= dataIn[0];
|
EP2Enable <= dataIn[0];
|
end
|
end
|
`EP3_CTRL_REG : begin
|
`EP3_CTRL_REG : begin
|
EP3SendStall <= dataIn[3];
|
EP3SendStall <= dataIn[3];
|
EP3DataSequence <= dataIn[2];
|
EP3DataSequence <= dataIn[2];
|
EP3SetReady <= dataIn[1];
|
EP3SetReady <= dataIn[1];
|
EP3Enable <= dataIn[0];
|
EP3Enable <= dataIn[0];
|
end
|
end
|
`SC_CONTROL_REG : SCControlReg <= dataIn[5:0];
|
`SC_CONTROL_REG : SCControlReg <= dataIn[5:0];
|
`SC_ADDRESS : SCAddrReg <= dataIn[6:0];
|
`SC_ADDRESS : SCAddrReg <= dataIn[6:0];
|
`SC_INTERRUPT_STATUS_REG : begin
|
`SC_INTERRUPT_STATUS_REG : begin
|
clrNAKReq <= dataIn[4];
|
clrNAKReq <= dataIn[4];
|
clrSOFReq <= dataIn[3];
|
clrSOFReq <= dataIn[3];
|
clrResetReq <= dataIn[2];
|
clrResetReq <= dataIn[2];
|
clrResInReq <= dataIn[1];
|
clrResInReq <= dataIn[1];
|
clrTransDoneReq <= dataIn[0];
|
clrTransDoneReq <= dataIn[0];
|
end
|
end
|
`SC_INTERRUPT_MASK_REG : interruptMaskReg <= dataIn[4:0];
|
`SC_INTERRUPT_MASK_REG : interruptMaskReg <= dataIn[4:0];
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
//interrupt control
|
//interrupt control
|
always @(posedge clk)
|
always @(posedge clk)
|
begin
|
begin
|
if (NAKSentIn == 1'b1)
|
if (NAKSentIn == 1'b1)
|
NAKSentInt <= 1'b1;
|
NAKSentInt <= 1'b1;
|
else if (clrNAKReq == 1'b1)
|
else if (clrNAKReq == 1'b1)
|
NAKSentInt <= 1'b0;
|
NAKSentInt <= 1'b0;
|
|
|
if (SOFRxedIn == 1'b1)
|
if (SOFRxedIn == 1'b1)
|
SOFRxedInt <= 1'b1;
|
SOFRxedInt <= 1'b1;
|
else if (clrSOFReq == 1'b1)
|
else if (clrSOFReq == 1'b1)
|
SOFRxedInt <= 1'b0;
|
SOFRxedInt <= 1'b0;
|
|
|
if (resetEventIn == 1'b1)
|
if (resetEventIn == 1'b1)
|
resetEventInt <= 1'b1;
|
resetEventInt <= 1'b1;
|
else if (clrResetReq == 1'b1)
|
else if (clrResetReq == 1'b1)
|
resetEventInt <= 1'b0;
|
resetEventInt <= 1'b0;
|
|
|
if (resumeIntIn == 1'b1)
|
if (resumeIntIn == 1'b1)
|
resumeInt <= 1'b1;
|
resumeInt <= 1'b1;
|
else if (clrResInReq == 1'b1)
|
else if (clrResInReq == 1'b1)
|
resumeInt <= 1'b0;
|
resumeInt <= 1'b0;
|
|
|
if (transDoneIn == 1'b1)
|
if (transDoneIn == 1'b1)
|
transDoneInt <= 1'b1;
|
transDoneInt <= 1'b1;
|
else if (clrTransDoneReq == 1'b1)
|
else if (clrTransDoneReq == 1'b1)
|
transDoneInt <= 1'b0;
|
transDoneInt <= 1'b0;
|
end
|
end
|
|
|
//mask interrupts
|
//mask interrupts
|
always @(interruptMaskReg or transDoneInt or resumeInt or resetEventInt or SOFRxedInt or NAKSentInt) begin
|
always @(interruptMaskReg or transDoneInt or resumeInt or resetEventInt or SOFRxedInt or NAKSentInt) begin
|
transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
|
transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
|
resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
|
resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
|
resetEventIntOut <= resetEventInt & interruptMaskReg[`RESET_EVENT_BIT];
|
resetEventIntOut <= resetEventInt & interruptMaskReg[`RESET_EVENT_BIT];
|
SOFRxedIntOut <= SOFRxedInt & interruptMaskReg[`SOF_RECEIVED_BIT];
|
SOFRxedIntOut <= SOFRxedInt & interruptMaskReg[`SOF_RECEIVED_BIT];
|
NAKSentIntOut <= NAKSentInt & interruptMaskReg[`NAK_SENT_INT_BIT];
|
NAKSentIntOut <= NAKSentInt & interruptMaskReg[`NAK_SENT_INT_BIT];
|
end
|
end
|
|
|
//end point ready, set/clear
|
//end point ready, set/clear
|
always @(posedge clk)
|
always @(posedge clk)
|
begin
|
begin
|
if (EP0SetReady == 1'b1)
|
if (EP0SetReady == 1'b1)
|
EP0Ready <= 1'b1;
|
EP0Ready <= 1'b1;
|
else if (clrEP0Ready == 1'b1)
|
else if (clrEP0Ready == 1'b1)
|
EP0Ready <= 1'b0;
|
EP0Ready <= 1'b0;
|
|
|
if (EP1SetReady == 1'b1)
|
if (EP1SetReady == 1'b1)
|
EP1Ready <= 1'b1;
|
EP1Ready <= 1'b1;
|
else if (clrEP1Ready == 1'b1)
|
else if (clrEP1Ready == 1'b1)
|
EP1Ready <= 1'b0;
|
EP1Ready <= 1'b0;
|
|
|
if (EP2SetReady == 1'b1)
|
if (EP2SetReady == 1'b1)
|
EP2Ready <= 1'b1;
|
EP2Ready <= 1'b1;
|
else if (clrEP2Ready == 1'b1)
|
else if (clrEP2Ready == 1'b1)
|
EP2Ready <= 1'b0;
|
EP2Ready <= 1'b0;
|
|
|
if (EP3SetReady == 1'b1)
|
if (EP3SetReady == 1'b1)
|
EP3Ready <= 1'b1;
|
EP3Ready <= 1'b1;
|
else if (clrEP3Ready == 1'b1)
|
else if (clrEP3Ready == 1'b1)
|
EP3Ready <= 1'b0;
|
EP3Ready <= 1'b0;
|
end
|
end
|
|
|
//break out control signals
|
//break out control signals
|
always @(SCControlReg) begin
|
always @(SCControlReg) begin
|
SCGlobalEn <= SCControlReg[`SC_GLOBAL_ENABLE_BIT];
|
SCGlobalEn <= SCControlReg[`SC_GLOBAL_ENABLE_BIT];
|
TxLineState <= SCControlReg[`SC_TX_LINE_STATE_MSBIT:`SC_TX_LINE_STATE_LSBIT];
|
TxLineState <= SCControlReg[`SC_TX_LINE_STATE_MSBIT:`SC_TX_LINE_STATE_LSBIT];
|
LineDirectControlEn <= SCControlReg[`SC_DIRECT_CONTROL_BIT];
|
LineDirectControlEn <= SCControlReg[`SC_DIRECT_CONTROL_BIT];
|
fullSpeedPol <= SCControlReg[`SC_FULL_SPEED_LINE_POLARITY_BIT];
|
fullSpeedPol <= SCControlReg[`SC_FULL_SPEED_LINE_POLARITY_BIT];
|
fullSpeedRate <= SCControlReg[`SC_FULL_SPEED_LINE_RATE_BIT];
|
fullSpeedRate <= SCControlReg[`SC_FULL_SPEED_LINE_RATE_BIT];
|
end
|
end
|
|
|
//combine endpoint control signals
|
//combine endpoint control signals
|
always @(EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
|
always @(EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
|
EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
|
EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
|
EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
|
EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
|
EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable)
|
EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable)
|
begin
|
begin
|
endP0ControlReg <= {EP0SendStall, EP0DataSequence, EP0Ready, EP0Enable};
|
endP0ControlReg <= {EP0SendStall, EP0DataSequence, EP0Ready, EP0Enable};
|
endP1ControlReg <= {EP1SendStall, EP1DataSequence, EP1Ready, EP1Enable};
|
endP1ControlReg <= {EP1SendStall, EP1DataSequence, EP1Ready, EP1Enable};
|
endP2ControlReg <= {EP2SendStall, EP2DataSequence, EP2Ready, EP2Enable};
|
endP2ControlReg <= {EP2SendStall, EP2DataSequence, EP2Ready, EP2Enable};
|
endP3ControlReg <= {EP3SendStall, EP3DataSequence, EP3Ready, EP3Enable};
|
endP3ControlReg <= {EP3SendStall, EP3DataSequence, EP3Ready, EP3Enable};
|
end
|
end
|
|
|
|
|
// async read mux
|
// async read mux
|
always @(address or
|
always @(address or
|
EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
|
EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
|
EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
|
EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
|
EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
|
EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
|
EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable or
|
EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable or
|
EP0StatusReg or EP1StatusReg or EP2StatusReg or EP3StatusReg or
|
EP0StatusReg or EP1StatusReg or EP2StatusReg or EP3StatusReg or
|
endP0ControlReg or endP1ControlReg or endP2ControlReg or endP3ControlReg or
|
endP0ControlReg or endP1ControlReg or endP2ControlReg or endP3ControlReg or
|
endP0NAKTransTypeReg or endP1NAKTransTypeReg or endP2NAKTransTypeReg or endP3NAKTransTypeReg or
|
endP0NAKTransTypeReg or endP1NAKTransTypeReg or endP2NAKTransTypeReg or endP3NAKTransTypeReg or
|
endP0TransTypeReg or endP1TransTypeReg or endP2TransTypeReg or endP3TransTypeReg or
|
endP0TransTypeReg or endP1TransTypeReg or endP2TransTypeReg or endP3TransTypeReg or
|
SCControlReg or connectStateIn or
|
SCControlReg or connectStateIn or
|
NAKSentInt or SOFRxedInt or resetEventInt or resumeInt or transDoneInt or
|
NAKSentInt or SOFRxedInt or resetEventInt or resumeInt or transDoneInt or
|
interruptMaskReg or SCAddrReg or frameNum)
|
interruptMaskReg or SCAddrReg or frameNum)
|
begin
|
begin
|
case (address)
|
case (address)
|
`EP0_CTRL_REG : dataOut <= endP0ControlReg;
|
`EP0_CTRL_REG : dataOut <= endP0ControlReg;
|
`EP0_STS_REG : dataOut <= EP0StatusReg;
|
`EP0_STS_REG : dataOut <= EP0StatusReg;
|
`EP0_TRAN_TYPE_STS_REG : dataOut <= endP0TransTypeReg;
|
`EP0_TRAN_TYPE_STS_REG : dataOut <= endP0TransTypeReg;
|
`EP0_NAK_TRAN_TYPE_STS_REG : dataOut <= endP0NAKTransTypeReg;
|
`EP0_NAK_TRAN_TYPE_STS_REG : dataOut <= endP0NAKTransTypeReg;
|
`EP1_CTRL_REG : dataOut <= endP1ControlReg;
|
`EP1_CTRL_REG : dataOut <= endP1ControlReg;
|
`EP1_STS_REG : dataOut <= EP1StatusReg;
|
`EP1_STS_REG : dataOut <= EP1StatusReg;
|
`EP1_TRAN_TYPE_STS_REG : dataOut <= endP1TransTypeReg;
|
`EP1_TRAN_TYPE_STS_REG : dataOut <= endP1TransTypeReg;
|
`EP1_NAK_TRAN_TYPE_STS_REG : dataOut <= endP1NAKTransTypeReg;
|
`EP1_NAK_TRAN_TYPE_STS_REG : dataOut <= endP1NAKTransTypeReg;
|
`EP2_CTRL_REG : dataOut <= endP2ControlReg;
|
`EP2_CTRL_REG : dataOut <= endP2ControlReg;
|
`EP2_STS_REG : dataOut <= EP2StatusReg;
|
`EP2_STS_REG : dataOut <= EP2StatusReg;
|
`EP2_TRAN_TYPE_STS_REG : dataOut <= endP2TransTypeReg;
|
`EP2_TRAN_TYPE_STS_REG : dataOut <= endP2TransTypeReg;
|
`EP2_NAK_TRAN_TYPE_STS_REG : dataOut <= endP2NAKTransTypeReg;
|
`EP2_NAK_TRAN_TYPE_STS_REG : dataOut <= endP2NAKTransTypeReg;
|
`EP3_CTRL_REG : dataOut <= endP3ControlReg;
|
`EP3_CTRL_REG : dataOut <= endP3ControlReg;
|
`EP3_STS_REG : dataOut <= EP3StatusReg;
|
`EP3_STS_REG : dataOut <= EP3StatusReg;
|
`EP3_TRAN_TYPE_STS_REG : dataOut <= endP3TransTypeReg;
|
`EP3_TRAN_TYPE_STS_REG : dataOut <= endP3TransTypeReg;
|
`EP3_NAK_TRAN_TYPE_STS_REG : dataOut <= endP3NAKTransTypeReg;
|
`EP3_NAK_TRAN_TYPE_STS_REG : dataOut <= endP3NAKTransTypeReg;
|
`SC_CONTROL_REG : dataOut <= SCControlReg;
|
`SC_CONTROL_REG : dataOut <= SCControlReg;
|
`SC_LINE_STATUS_REG : dataOut <= {6'b000000, connectStateIn};
|
`SC_LINE_STATUS_REG : dataOut <= {6'b000000, connectStateIn};
|
`SC_INTERRUPT_STATUS_REG : dataOut <= {3'b000, NAKSentInt, SOFRxedInt, resetEventInt, resumeInt, transDoneInt};
|
`SC_INTERRUPT_STATUS_REG : dataOut <= {3'b000, NAKSentInt, SOFRxedInt, resetEventInt, resumeInt, transDoneInt};
|
`SC_INTERRUPT_MASK_REG : dataOut <= {3'b000, interruptMaskReg};
|
`SC_INTERRUPT_MASK_REG : dataOut <= {3'b000, interruptMaskReg};
|
`SC_ADDRESS : dataOut <= {1'b0, SCAddrReg};
|
`SC_ADDRESS : dataOut <= {1'b0, SCAddrReg};
|
`SC_FRAME_NUM_MSP : dataOut <= frameNum[10:3];
|
`SC_FRAME_NUM_MSP : dataOut <= frameNum[10:3];
|
`SC_FRAME_NUM_LSP : dataOut <= {5'b00000, frameNum[2:0]};
|
`SC_FRAME_NUM_LSP : dataOut <= {5'b00000, frameNum[2:0]};
|
default: dataOut <= 8'h00;
|
default: dataOut <= 8'h00;
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
|
|
