VERSION=1.21
|
VERSION=1.21
|
HEADER
|
HEADER
|
FILE="sctxportarbiter.asf"
|
FILE="sctxportarbiter.asf"
|
FID=405ea588
|
FID=405ea588
|
LANGUAGE=VERILOG
|
LANGUAGE=VERILOG
|
ENTITY="SCTxPortArbiter"
|
ENTITY="SCTxPortArbiter"
|
FREEOID=101
|
FREEOID=101
|
"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// SCTxPortArbiter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n"
|
"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// SCTxPortArbiter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n"
|
MULTIPLEARCHSTATUS=FALSE
|
MULTIPLEARCHSTATUS=FALSE
|
SYNTHESISATTRIBUTES=TRUE
|
SYNTHESISATTRIBUTES=TRUE
|
HEADER_PARAM="AUTHOR,"
|
HEADER_PARAM="AUTHOR,"
|
HEADER_PARAM="COMPANY,"
|
HEADER_PARAM="COMPANY,"
|
HEADER_PARAM="CREATIONDATE,"
|
HEADER_PARAM="CREATIONDATE,"
|
HEADER_PARAM="TITLE,No Title"
|
HEADER_PARAM="TITLE,No Title"
|
BLOCKTABLE_FILE=""
|
BLOCKTABLE_FILE=""
|
BLOCKTABLE_TEMPL="0"
|
BLOCKTABLE_TEMPL="0"
|
BLOCKTABLE_VISIBLE="1"
|
BLOCKTABLE_VISIBLE="1"
|
END
|
END
|
BUNDLES
|
BUNDLES
|
B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
|
B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
|
B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
|
B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
|
B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
|
B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
|
B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
|
B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
|
B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 0
|
B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 0
|
B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
|
B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
|
B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
|
B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
|
B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
|
B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
|
B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 4
|
B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 4
|
B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
|
B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
|
B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
|
B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
|
B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
|
B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
|
B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
|
B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
|
B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
|
B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
|
B T "Alias" 0,128,0 0 0 1 255,255,255 0 3527 1480 0000 0 "Arial" 0
|
B T "Alias" 0,128,0 0 0 1 255,255,255 0 3527 1480 0000 0 "Arial" 0
|
B F "Delay" 0,0,0 0 0 1 180,180,180 1 3527 1480 0000 0 "Arial" 0
|
B F "Delay" 0,0,0 0 0 1 180,180,180 1 3527 1480 0000 0 "Arial" 0
|
END
|
END
|
INSTHEADER 1
|
INSTHEADER 1
|
PAGE 0,0 431800,558800
|
PAGE 0,0 431800,558800
|
MARGINS 12700,0 0,12700
|
MARGINS 12700,0 0,12700
|
END
|
END
|
OBJECTS
|
OBJECTS
|
G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,530400 1 0 0 "Module: SCTxPortArbiter"
|
G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,530400 1 0 0 "Module: SCTxPortArbiter"
|
F 6 0 671089152 41 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 138680,265200 323180,400245
|
F 6 0 671089152 41 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 138680,265200 323180,400245
|
L 7 6 0 TEXT "Labels" | 153720,386820 1 0 0 "SCTxArb"
|
L 7 6 0 TEXT "Labels" | 153720,386820 1 0 0 "SCTxArb"
|
S 8 6 12288 ELLIPSE "States" | 225591,382670 6500 6500
|
S 8 6 12288 ELLIPSE "States" | 225591,382670 6500 6500
|
L 9 8 0 TEXT "State Labels" | 225591,382670 1 0 0 "START_SARB\n/3/"
|
L 9 8 0 TEXT "State Labels" | 225591,382670 1 0 0 "START_SARB\n/3/"
|
S 10 6 0 ELLIPSE "States" | 224972,352339 6500 6500
|
S 10 6 0 ELLIPSE "States" | 224972,352339 6500 6500
|
L 11 10 0 TEXT "State Labels" | 224972,350953 1 0 0 "SARB1_WAIT_REQ\n/0/"
|
L 11 10 0 TEXT "State Labels" | 224972,350953 1 0 0 "SARB1_WAIT_REQ\n/0/"
|
S 14 6 4096 ELLIPSE "States" | 269063,283692 6500 6500
|
S 14 6 4096 ELLIPSE "States" | 269063,283692 6500 6500
|
L 15 14 0 TEXT "State Labels" | 269063,283692 1 0 0 "SARB_SEND_PACKET\n/1/"
|
L 15 14 0 TEXT "State Labels" | 269063,283692 1 0 0 "SARB_SEND_PACKET\n/1/"
|
I 16 6 0 Builtin Reset | 178237,383010
|
I 16 6 0 Builtin Reset | 178237,383010
|
W 17 6 0 16 8 BEZIER "Transitions" | 178237,383010 187522,379237 210185,378778 219470,380486
|
W 17 6 0 16 8 BEZIER "Transitions" | 178237,383010 187522,379237 210185,378778 219470,380486
|
W 18 6 0 8 10 BEZIER "Transitions" | 225224,376194 225070,371714 224938,363311 224784,358831
|
W 18 6 0 8 10 BEZIER "Transitions" | 225224,376194 225070,371714 224938,363311 224784,358831
|
W 19 6 4097 10 14 BEZIER "Transitions" | 229757,347941 236477,342379 258220,303210 265438,289087
|
W 19 6 4097 10 14 BEZIER "Transitions" | 229757,347941 236477,342379 258220,303210 265438,289087
|
C 22 19 0 TEXT "Conditions" | 235353,345815 1 0 0 "sendPacketReq == 1'b1"
|
C 22 19 0 TEXT "Conditions" | 235353,345815 1 0 0 "sendPacketReq == 1'b1"
|
A 23 19 16 TEXT "Actions" | 233291,327240 1 0 0 "sendPacketGnt <= 1'b1;\nmuxDCEn <= 1'b0;"
|
A 23 19 16 TEXT "Actions" | 233291,327240 1 0 0 "sendPacketGnt <= 1'b1;\nmuxDCEn <= 1'b0;"
|
A 25 8 2 TEXT "Actions" | 234434,398687 1 0 0 "sendPacketGnt <= 1'b0;\ndirectCntlGnt <= 1'b0;\nmuxDCEn <= 1'b0;"
|
A 25 8 2 TEXT "Actions" | 234434,398687 1 0 0 "sendPacketGnt <= 1'b0;\ndirectCntlGnt <= 1'b0;\nmuxDCEn <= 1'b0;"
|
C 26 17 0 TEXT "Conditions" | 202073,378708 1 0 0 "rst"
|
C 26 17 0 TEXT "Conditions" | 202073,378708 1 0 0 "rst"
|
W 27 6 0 14 10 BEZIER "Transitions" | 272129,289421 294143,309321 288020,333532 288403,340102\
|
W 27 6 0 14 10 BEZIER "Transitions" | 272129,289421 294143,309321 288020,333532 288403,340102\
|
288786,346672 287077,358761 282417,364209 277757,369657\
|
288786,346672 287077,358761 282417,364209 277757,369657\
|
274547,368787 268775,368864 263003,368942 254872,368666\
|
274547,368787 268775,368864 263003,368942 254872,368666\
|
248267,366271 241663,363877 234289,358857 230118,356308
|
248267,366271 241663,363877 234289,358857 230118,356308
|
C 31 27 0 TEXT "Conditions" | 272024,302471 1 0 0 "sendPacketReq == 1'b0"
|
C 31 27 0 TEXT "Conditions" | 272024,302471 1 0 0 "sendPacketReq == 1'b0"
|
A 32 27 16 TEXT "Actions" | 268756,358479 1 0 0 "sendPacketGnt <= 1'b0;"
|
A 32 27 16 TEXT "Actions" | 268756,358479 1 0 0 "sendPacketGnt <= 1'b0;"
|
I 35 0 2 Builtin OutPort | 164373,445096 "" ""
|
I 35 0 2 Builtin OutPort | 164373,445096 "" ""
|
L 36 35 0 TEXT "Labels" | 170373,445096 1 0 0 "SCTxPortWEnable"
|
L 36 35 0 TEXT "Labels" | 170373,445096 1 0 0 "SCTxPortWEnable"
|
I 37 0 2 Builtin OutPort | 164033,473151 "" ""
|
I 37 0 2 Builtin OutPort | 164033,473151 "" ""
|
L 38 37 0 TEXT "Labels" | 170033,473151 1 0 0 "sendPacketGnt"
|
L 38 37 0 TEXT "Labels" | 170033,473151 1 0 0 "sendPacketGnt"
|
I 39 0 2 Builtin InPort | 189447,529426 "" ""
|
I 39 0 2 Builtin InPort | 189447,529426 "" ""
|
L 40 39 0 TEXT "Labels" | 195447,529426 1 0 0 "rst"
|
L 40 39 0 TEXT "Labels" | 195447,529426 1 0 0 "rst"
|
I 41 0 3 Builtin InPort | 190061,523882 "" ""
|
I 41 0 3 Builtin InPort | 190061,523882 "" ""
|
I 42 0 2 Builtin InPort | 166566,450081 "" ""
|
I 42 0 2 Builtin InPort | 166566,450081 "" ""
|
L 43 42 0 TEXT "Labels" | 172566,450081 1 0 0 "SCTxPortRdyIn"
|
L 43 42 0 TEXT "Labels" | 172566,450081 1 0 0 "SCTxPortRdyIn"
|
I 44 0 130 Builtin InPort | 166169,486799 "" ""
|
I 44 0 130 Builtin InPort | 166169,486799 "" ""
|
L 45 44 0 TEXT "Labels" | 172169,486799 1 0 0 "sendPacketData[7:0]"
|
L 45 44 0 TEXT "Labels" | 172169,486799 1 0 0 "sendPacketData[7:0]"
|
I 52 0 2 Builtin InPort | 165981,477939 "" ""
|
I 52 0 2 Builtin InPort | 165981,477939 "" ""
|
L 53 52 0 TEXT "Labels" | 171981,477939 1 0 0 "sendPacketWEn"
|
L 53 52 0 TEXT "Labels" | 171981,477939 1 0 0 "sendPacketWEn"
|
A 54 0 1 TEXT "Actions" | 21871,406257 1 0 0 "// SOFController/directContol/sendPacket mux\nalways @(SCTxPortRdyIn)\nbegin\n SCTxPortRdyOut <= SCTxPortRdyIn;\nend\n \nalways @(muxDCEn or\n directCntlWEn or directCntlData or directCntlCntl or\n directCntlWEn or directCntlData or directCntlCntl or\n sendPacketWEn or sendPacketData or sendPacketCntl)\nbegin\nif (muxDCEn == 1'b1)\n begin \n SCTxPortWEnable <= directCntlWEn;\n SCTxPortData <= directCntlData;\n SCTxPortCntl <= directCntlCntl;\n end\nelse\n begin \n SCTxPortWEnable <= sendPacketWEn;\n SCTxPortData <= sendPacketData;\n SCTxPortCntl <= sendPacketCntl;\n end\nend"
|
A 54 0 1 TEXT "Actions" | 21871,406257 1 0 0 "// SOFController/directContol/sendPacket mux\nalways @(SCTxPortRdyIn)\nbegin\n SCTxPortRdyOut <= SCTxPortRdyIn;\nend\n \nalways @(muxDCEn or\n directCntlWEn or directCntlData or directCntlCntl or\n directCntlWEn or directCntlData or directCntlCntl or\n sendPacketWEn or sendPacketData or sendPacketCntl)\nbegin\nif (muxDCEn == 1'b1)\n begin \n SCTxPortWEnable <= directCntlWEn;\n SCTxPortData <= directCntlData;\n SCTxPortCntl <= directCntlCntl;\n end\nelse\n begin \n SCTxPortWEnable <= sendPacketWEn;\n SCTxPortData <= sendPacketData;\n SCTxPortCntl <= sendPacketCntl;\n end\nend"
|
I 56 0 2 Builtin InPort | 166286,468363 "" ""
|
I 56 0 2 Builtin InPort | 166286,468363 "" ""
|
L 57 56 0 TEXT "Labels" | 172286,468363 1 0 0 "sendPacketReq"
|
L 57 56 0 TEXT "Labels" | 172286,468363 1 0 0 "sendPacketReq"
|
I 58 0 130 Builtin OutPort | 164296,440578 "" ""
|
I 58 0 130 Builtin OutPort | 164296,440578 "" ""
|
L 59 58 0 TEXT "Labels" | 170296,440578 1 0 0 "SCTxPortData[7:0]"
|
L 59 58 0 TEXT "Labels" | 170296,440578 1 0 0 "SCTxPortData[7:0]"
|
L 61 41 0 TEXT "Labels" | 196061,523882 1 0 0 "clk"
|
L 61 41 0 TEXT "Labels" | 196061,523882 1 0 0 "clk"
|
I 62 0 130 Builtin InPort | 166256,482420 "" ""
|
I 62 0 130 Builtin InPort | 166256,482420 "" ""
|
L 63 62 0 TEXT "Labels" | 172256,482420 1 0 0 "sendPacketCntl[7:0]"
|
L 63 62 0 TEXT "Labels" | 172256,482420 1 0 0 "sendPacketCntl[7:0]"
|
I 64 0 2 Builtin OutPort | 164048,454434 "" ""
|
I 64 0 2 Builtin OutPort | 164048,454434 "" ""
|
L 65 64 0 TEXT "Labels" | 170048,454434 1 0 0 "SCTxPortRdyOut"
|
L 65 64 0 TEXT "Labels" | 170048,454434 1 0 0 "SCTxPortRdyOut"
|
I 66 0 130 Builtin OutPort | 164124,458856 "" ""
|
I 66 0 130 Builtin OutPort | 164124,458856 "" ""
|
L 67 66 0 TEXT "Labels" | 170124,458856 1 0 0 "SCTxPortCntl[7:0]"
|
L 67 66 0 TEXT "Labels" | 170124,458856 1 0 0 "SCTxPortCntl[7:0]"
|
I 78 0 2 Builtin OutPort | 117944,444360 "" ""
|
I 78 0 2 Builtin OutPort | 117944,444360 "" ""
|
L 79 78 0 TEXT "Labels" | 123944,444360 1 0 0 "directCntlGnt"
|
L 79 78 0 TEXT "Labels" | 123944,444360 1 0 0 "directCntlGnt"
|
I 80 0 2 Builtin InPort | 120331,439767 "" ""
|
I 80 0 2 Builtin InPort | 120331,439767 "" ""
|
L 81 80 0 TEXT "Labels" | 126331,439767 1 0 0 "directCntlReq"
|
L 81 80 0 TEXT "Labels" | 126331,439767 1 0 0 "directCntlReq"
|
I 82 0 2 Builtin InPort | 120527,449241 "" ""
|
I 82 0 2 Builtin InPort | 120527,449241 "" ""
|
L 83 82 0 TEXT "Labels" | 126527,449241 1 0 0 "directCntlWEn"
|
L 83 82 0 TEXT "Labels" | 126527,449241 1 0 0 "directCntlWEn"
|
I 84 0 130 Builtin InPort | 120256,458649 "" ""
|
I 84 0 130 Builtin InPort | 120256,458649 "" ""
|
L 85 84 0 TEXT "Labels" | 126256,458649 1 0 0 "directCntlData[7:0]"
|
L 85 84 0 TEXT "Labels" | 126256,458649 1 0 0 "directCntlData[7:0]"
|
I 86 0 130 Builtin InPort | 120356,454026 "" ""
|
I 86 0 130 Builtin InPort | 120356,454026 "" ""
|
L 87 86 0 TEXT "Labels" | 126356,454026 1 0 0 "directCntlCntl[7:0]"
|
L 87 86 0 TEXT "Labels" | 126356,454026 1 0 0 "directCntlCntl[7:0]"
|
L 88 89 0 TEXT "Labels" | 144050,516112 1 0 0 "muxDCEn"
|
L 88 89 0 TEXT "Labels" | 144050,516112 1 0 0 "muxDCEn"
|
I 89 0 2 Builtin Signal | 141050,516112 "" ""
|
I 89 0 2 Builtin Signal | 141050,516112 "" ""
|
L 90 91 0 TEXT "State Labels" | 230314,277248 1 0 0 "SARB_DC\n/2/"
|
L 90 91 0 TEXT "State Labels" | 230314,277248 1 0 0 "SARB_DC\n/2/"
|
S 91 6 8192 ELLIPSE "States" | 230314,277248 6500 6500
|
S 91 6 8192 ELLIPSE "States" | 230314,277248 6500 6500
|
W 92 6 4098 10 91 BEZIER "Transitions" | 225187,345873 226192,330195 228547,299373 229552,283695
|
W 92 6 4098 10 91 BEZIER "Transitions" | 225187,345873 226192,330195 228547,299373 229552,283695
|
C 94 92 0 TEXT "Conditions" | 216646,306594 1 0 0 "directCntlReq == 1'b1"
|
C 94 92 0 TEXT "Conditions" | 216646,306594 1 0 0 "directCntlReq == 1'b1"
|
A 95 92 16 TEXT "Actions" | 205993,298152 1 0 0 "directCntlGnt <= 1'b1;\nmuxDCEn <= 1'b1;"
|
A 95 92 16 TEXT "Actions" | 205993,298152 1 0 0 "directCntlGnt <= 1'b1;\nmuxDCEn <= 1'b1;"
|
W 96 6 0 91 10 BEZIER "Transitions" | 235538,273381 238258,272374 242316,270375 251081,269871\
|
W 96 6 0 91 10 BEZIER "Transitions" | 235538,273381 238258,272374 242316,270375 251081,269871\
|
259846,269368 289467,269368 298484,271534 307501,273700\
|
259846,269368 289467,269368 298484,271534 307501,273700\
|
313949,282365 315460,295059 316972,307753 316568,349868\
|
313949,282365 315460,295059 316972,307753 316568,349868\
|
311430,362360 306292,374853 286142,382712 275462,382410\
|
311430,362360 306292,374853 286142,382712 275462,382410\
|
264783,382108 242215,373039 236069,369412 229924,365786\
|
264783,382108 242215,373039 236069,369412 229924,365786\
|
228216,361158 227209,358438
|
228216,361158 227209,358438
|
C 97 96 0 TEXT "Conditions" | 246245,274204 1 0 0 "directCntlReq == 1'b0"
|
C 97 96 0 TEXT "Conditions" | 246245,274204 1 0 0 "directCntlReq == 1'b0"
|
A 98 96 16 TEXT "Actions" | 290172,277428 1 0 0 "directCntlGnt <= 1'b0;"
|
A 98 96 16 TEXT "Actions" | 290172,277428 1 0 0 "directCntlGnt <= 1'b0;"
|
END
|
END
|
|
|
