|
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// File : ../RTL/slaveController/slaveGetpacket.v
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// File : ../RTL/slaveController/slaveGetpacket.v
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// Generated : 11/10/06 05:37:25
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// Generated : 11/10/06 05:37:25
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// From : ../RTL/slaveController/slaveGetpacket.asf
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// From : ../RTL/slaveController/slaveGetpacket.asf
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// By : FSM2VHDL ver. 5.0.0.9
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// By : FSM2VHDL ver. 5.0.0.9
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|
|
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// slaveGetPacket
|
//// slaveGetPacket
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//// ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
|
//// This file is part of the usbhostslave opencores effort.
|
//// http://www.opencores.org/cores/usbhostslave/ ////
|
//// http://www.opencores.org/cores/usbhostslave/ ////
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//// ////
|
//// ////
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//// Module Description: ////
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//// Module Description: ////
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////
|
////
|
//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
|
////
|
////
|
//// ////
|
//// ////
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//// Author(s): ////
|
//// Author(s): ////
|
//// - Steve Fielding, sfielding@base2designs.com ////
|
//// - Steve Fielding, sfielding@base2designs.com ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
|
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
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//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
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//
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//
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`include "timescale.v"
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`include "timescale.v"
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbConstants_h.v"
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`include "usbConstants_h.v"
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|
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module slaveGetPacket (ACKRxed, CRCError, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RXStreamStatusIn, RXTimeOut, RxPID, SIERxTimeOut, SIERxTimeOutEn, bitStuffError, clk, dataSequence, endPointReady, getPacketEn, rst);
|
module slaveGetPacket (ACKRxed, CRCError, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RXStreamStatusIn, RXTimeOut, RxPID, SIERxTimeOut, SIERxTimeOutEn, bitStuffError, clk, dataSequence, endPointReady, getPacketEn, rst);
|
input [7:0] RXDataIn;
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input [7:0] RXDataIn;
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input RXDataValid;
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input RXDataValid;
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input RXFifoFull;
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input RXFifoFull;
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input [7:0] RXStreamStatusIn;
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input [7:0] RXStreamStatusIn;
|
input SIERxTimeOut; // Single cycle pulse
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input SIERxTimeOut; // Single cycle pulse
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input clk;
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input clk;
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input endPointReady;
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input endPointReady;
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input getPacketEn;
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input getPacketEn;
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input rst;
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input rst;
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output ACKRxed;
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output ACKRxed;
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output CRCError;
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output CRCError;
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output [7:0] RXFifoData;
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output [7:0] RXFifoData;
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output RXFifoWEn;
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output RXFifoWEn;
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output RXOverflow;
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output RXOverflow;
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output RXPacketRdy;
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output RXPacketRdy;
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output RXTimeOut;
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output RXTimeOut;
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output [3:0] RxPID;
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output [3:0] RxPID;
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output SIERxTimeOutEn;
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output SIERxTimeOutEn;
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output bitStuffError;
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output bitStuffError;
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output dataSequence;
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output dataSequence;
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|
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reg ACKRxed, next_ACKRxed;
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reg ACKRxed, next_ACKRxed;
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reg CRCError, next_CRCError;
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reg CRCError, next_CRCError;
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wire [7:0] RXDataIn;
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wire [7:0] RXDataIn;
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wire RXDataValid;
|
wire RXDataValid;
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reg [7:0] RXFifoData, next_RXFifoData;
|
reg [7:0] RXFifoData, next_RXFifoData;
|
wire RXFifoFull;
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wire RXFifoFull;
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reg RXFifoWEn, next_RXFifoWEn;
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reg RXFifoWEn, next_RXFifoWEn;
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reg RXOverflow, next_RXOverflow;
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reg RXOverflow, next_RXOverflow;
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reg RXPacketRdy, next_RXPacketRdy;
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reg RXPacketRdy, next_RXPacketRdy;
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wire [7:0] RXStreamStatusIn;
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wire [7:0] RXStreamStatusIn;
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reg RXTimeOut, next_RXTimeOut;
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reg RXTimeOut, next_RXTimeOut;
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reg [3:0] RxPID, next_RxPID;
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reg [3:0] RxPID, next_RxPID;
|
wire SIERxTimeOut;
|
wire SIERxTimeOut;
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reg SIERxTimeOutEn, next_SIERxTimeOutEn;
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reg SIERxTimeOutEn, next_SIERxTimeOutEn;
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reg bitStuffError, next_bitStuffError;
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reg bitStuffError, next_bitStuffError;
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wire clk;
|
wire clk;
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reg dataSequence, next_dataSequence;
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reg dataSequence, next_dataSequence;
|
wire endPointReady;
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wire endPointReady;
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wire getPacketEn;
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wire getPacketEn;
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wire rst;
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wire rst;
|
|
|
// diagram signals declarations
|
// diagram signals declarations
|
reg [7:0]RXByteOld, next_RXByteOld;
|
reg [7:0]RXByteOld, next_RXByteOld;
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reg [7:0]RXByteOldest, next_RXByteOldest;
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reg [7:0]RXByteOldest, next_RXByteOldest;
|
reg [7:0]RXByte, next_RXByte;
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reg [7:0]RXByte, next_RXByte;
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reg [7:0]RXStreamStatus, next_RXStreamStatus;
|
reg [7:0]RXStreamStatus, next_RXStreamStatus;
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|
|
// BINARY ENCODED state machine: slvGetPkt
|
// BINARY ENCODED state machine: slvGetPkt
|
// State codes definitions:
|
// State codes definitions:
|
`define PROC_PKT_CHK_PID 5'b00000
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`define PROC_PKT_CHK_PID 5'b00000
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`define PROC_PKT_HS 5'b00001
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`define PROC_PKT_HS 5'b00001
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`define PROC_PKT_DATA_W_D1 5'b00010
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`define PROC_PKT_DATA_W_D1 5'b00010
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`define PROC_PKT_DATA_CHK_D1 5'b00011
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`define PROC_PKT_DATA_CHK_D1 5'b00011
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`define PROC_PKT_DATA_W_D2 5'b00100
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`define PROC_PKT_DATA_W_D2 5'b00100
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`define PROC_PKT_DATA_FIN 5'b00101
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`define PROC_PKT_DATA_FIN 5'b00101
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`define PROC_PKT_DATA_CHK_D2 5'b00110
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`define PROC_PKT_DATA_CHK_D2 5'b00110
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`define PROC_PKT_DATA_W_D3 5'b00111
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`define PROC_PKT_DATA_W_D3 5'b00111
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`define PROC_PKT_DATA_CHK_D3 5'b01000
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`define PROC_PKT_DATA_CHK_D3 5'b01000
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`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
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`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
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`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
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`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
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`define PROC_PKT_DATA_LOOP_W_D 5'b01011
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`define PROC_PKT_DATA_LOOP_W_D 5'b01011
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`define START_GP 5'b01100
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`define START_GP 5'b01100
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`define WAIT_PKT 5'b01101
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`define WAIT_PKT 5'b01101
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`define CHK_PKT_START 5'b01110
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`define CHK_PKT_START 5'b01110
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`define WAIT_EN 5'b01111
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`define WAIT_EN 5'b01111
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`define PKT_RDY 5'b10000
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`define PKT_RDY 5'b10000
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`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
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`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
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`define PROC_PKT_DATA_LOOP_EP_N_RDY 5'b10010
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`define PROC_PKT_DATA_LOOP_EP_N_RDY 5'b10010
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|
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reg [4:0] CurrState_slvGetPkt;
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reg [4:0] CurrState_slvGetPkt;
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reg [4:0] NextState_slvGetPkt;
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reg [4:0] NextState_slvGetPkt;
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|
|
|
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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// Machine: slvGetPkt
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// Machine: slvGetPkt
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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//----------------------------------
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//----------------------------------
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// Next State Logic (combinatorial)
|
// Next State Logic (combinatorial)
|
//----------------------------------
|
//----------------------------------
|
always @ (RXDataIn or RXStreamStatusIn or RXByte or RXByteOldest or RXByteOld or RXDataValid or SIERxTimeOut or RXStreamStatus or getPacketEn or endPointReady or RXFifoFull or CRCError or bitStuffError or RXOverflow or RXTimeOut or ACKRxed or dataSequence or SIERxTimeOutEn or RxPID or RXPacketRdy or RXFifoWEn or RXFifoData or CurrState_slvGetPkt)
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always @ (RXDataIn or RXStreamStatusIn or RXByte or RXByteOldest or RXByteOld or RXDataValid or SIERxTimeOut or RXStreamStatus or getPacketEn or endPointReady or RXFifoFull or CRCError or bitStuffError or RXOverflow or RXTimeOut or ACKRxed or dataSequence or SIERxTimeOutEn or RxPID or RXPacketRdy or RXFifoWEn or RXFifoData or CurrState_slvGetPkt)
|
begin : slvGetPkt_NextState
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begin : slvGetPkt_NextState
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NextState_slvGetPkt <= CurrState_slvGetPkt;
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NextState_slvGetPkt <= CurrState_slvGetPkt;
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// Set default values for outputs and signals
|
// Set default values for outputs and signals
|
next_CRCError <= CRCError;
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next_CRCError <= CRCError;
|
next_bitStuffError <= bitStuffError;
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next_bitStuffError <= bitStuffError;
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next_RXOverflow <= RXOverflow;
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next_RXOverflow <= RXOverflow;
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next_RXTimeOut <= RXTimeOut;
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next_RXTimeOut <= RXTimeOut;
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next_ACKRxed <= ACKRxed;
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next_ACKRxed <= ACKRxed;
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next_dataSequence <= dataSequence;
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next_dataSequence <= dataSequence;
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next_SIERxTimeOutEn <= SIERxTimeOutEn;
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next_SIERxTimeOutEn <= SIERxTimeOutEn;
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next_RXByte <= RXByte;
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next_RXByte <= RXByte;
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next_RXStreamStatus <= RXStreamStatus;
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next_RXStreamStatus <= RXStreamStatus;
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next_RxPID <= RxPID;
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next_RxPID <= RxPID;
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next_RXPacketRdy <= RXPacketRdy;
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next_RXPacketRdy <= RXPacketRdy;
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next_RXByteOldest <= RXByteOldest;
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next_RXByteOldest <= RXByteOldest;
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next_RXByteOld <= RXByteOld;
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next_RXByteOld <= RXByteOld;
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next_RXFifoWEn <= RXFifoWEn;
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next_RXFifoWEn <= RXFifoWEn;
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next_RXFifoData <= RXFifoData;
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next_RXFifoData <= RXFifoData;
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case (CurrState_slvGetPkt)
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case (CurrState_slvGetPkt)
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`START_GP:
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`START_GP:
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NextState_slvGetPkt <= `WAIT_EN;
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NextState_slvGetPkt <= `WAIT_EN;
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`WAIT_PKT:
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`WAIT_PKT:
|
begin
|
begin
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next_CRCError <= 1'b0;
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next_CRCError <= 1'b0;
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next_bitStuffError <= 1'b0;
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next_bitStuffError <= 1'b0;
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next_RXOverflow <= 1'b0;
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next_RXOverflow <= 1'b0;
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next_RXTimeOut <= 1'b0;
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next_RXTimeOut <= 1'b0;
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next_ACKRxed <= 1'b0;
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next_ACKRxed <= 1'b0;
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next_dataSequence <= 1'b0;
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next_dataSequence <= 1'b0;
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next_SIERxTimeOutEn <= 1'b1;
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next_SIERxTimeOutEn <= 1'b1;
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if (RXDataValid == 1'b1)
|
if (RXDataValid == 1'b1)
|
begin
|
begin
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NextState_slvGetPkt <= `CHK_PKT_START;
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NextState_slvGetPkt <= `CHK_PKT_START;
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next_RXByte <= RXDataIn;
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next_RXByte <= RXDataIn;
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next_RXStreamStatus <= RXStreamStatusIn;
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next_RXStreamStatus <= RXStreamStatusIn;
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end
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end
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else if (SIERxTimeOut == 1'b1)
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else if (SIERxTimeOut == 1'b1)
|
begin
|
begin
|
NextState_slvGetPkt <= `PKT_RDY;
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NextState_slvGetPkt <= `PKT_RDY;
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next_RXTimeOut <= 1'b1;
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next_RXTimeOut <= 1'b1;
|
end
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end
|
end
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end
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`CHK_PKT_START:
|
`CHK_PKT_START:
|
if (RXStreamStatus == `RX_PACKET_START)
|
if (RXStreamStatus == `RX_PACKET_START)
|
begin
|
begin
|
NextState_slvGetPkt <= `PROC_PKT_CHK_PID;
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NextState_slvGetPkt <= `PROC_PKT_CHK_PID;
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next_RxPID <= RXByte[3:0];
|
next_RxPID <= RXByte[3:0];
|
end
|
end
|
else
|
else
|
begin
|
begin
|
NextState_slvGetPkt <= `PKT_RDY;
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NextState_slvGetPkt <= `PKT_RDY;
|
next_RXTimeOut <= 1'b1;
|
next_RXTimeOut <= 1'b1;
|
end
|
end
|
`WAIT_EN:
|
`WAIT_EN:
|
begin
|
begin
|
next_RXPacketRdy <= 1'b0;
|
next_RXPacketRdy <= 1'b0;
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next_SIERxTimeOutEn <= 1'b0;
|
next_SIERxTimeOutEn <= 1'b0;
|
if (getPacketEn == 1'b1)
|
if (getPacketEn == 1'b1)
|
NextState_slvGetPkt <= `WAIT_PKT;
|
NextState_slvGetPkt <= `WAIT_PKT;
|
end
|
end
|
`PKT_RDY:
|
`PKT_RDY:
|
begin
|
begin
|
next_RXPacketRdy <= 1'b1;
|
next_RXPacketRdy <= 1'b1;
|
NextState_slvGetPkt <= `WAIT_EN;
|
NextState_slvGetPkt <= `WAIT_EN;
|
end
|
end
|
`PROC_PKT_CHK_PID:
|
`PROC_PKT_CHK_PID:
|
if (RXByte[1:0] == `HANDSHAKE)
|
if (RXByte[1:0] == `HANDSHAKE)
|
NextState_slvGetPkt <= `PROC_PKT_HS;
|
NextState_slvGetPkt <= `PROC_PKT_HS;
|
else if (RXByte[1:0] == `DATA)
|
else if (RXByte[1:0] == `DATA)
|
NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1;
|
NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1;
|
else
|
else
|
NextState_slvGetPkt <= `PKT_RDY;
|
NextState_slvGetPkt <= `PKT_RDY;
|
`PROC_PKT_HS:
|
`PROC_PKT_HS:
|
if (RXDataValid == 1'b1)
|
if (RXDataValid == 1'b1)
|
begin
|
begin
|
NextState_slvGetPkt <= `PKT_RDY;
|
NextState_slvGetPkt <= `PKT_RDY;
|
next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
|
next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
|
next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
|
next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
|
end
|
end
|
`PROC_PKT_DATA_W_D1:
|
`PROC_PKT_DATA_W_D1:
|
if (RXDataValid == 1'b1)
|
if (RXDataValid == 1'b1)
|
begin
|
begin
|
NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1;
|
NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1;
|
next_RXByte <= RXDataIn;
|
next_RXByte <= RXDataIn;
|
next_RXStreamStatus <= RXStreamStatusIn;
|
next_RXStreamStatus <= RXStreamStatusIn;
|
end
|
end
|
`PROC_PKT_DATA_CHK_D1:
|
`PROC_PKT_DATA_CHK_D1:
|
if (RXStreamStatus == `RX_PACKET_STREAM)
|
if (RXStreamStatus == `RX_PACKET_STREAM)
|
begin
|
begin
|
NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2;
|
NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2;
|
next_RXByteOldest <= RXByte;
|
next_RXByteOldest <= RXByte;
|
end
|
end
|
else
|
else
|
NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
|
NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
|
`PROC_PKT_DATA_W_D2:
|
`PROC_PKT_DATA_W_D2:
|
if (RXDataValid == 1'b1)
|
if (RXDataValid == 1'b1)
|
begin
|
begin
|
NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2;
|
NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2;
|
next_RXByte <= RXDataIn;
|
next_RXByte <= RXDataIn;
|
next_RXStreamStatus <= RXStreamStatusIn;
|
next_RXStreamStatus <= RXStreamStatusIn;
|
end
|
end
|
`PROC_PKT_DATA_FIN:
|
`PROC_PKT_DATA_FIN:
|
begin
|
begin
|
next_CRCError <= RXByte[`CRC_ERROR_BIT];
|
next_CRCError <= RXByte[`CRC_ERROR_BIT];
|
next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
|
next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
|
next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
|
next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
|
NextState_slvGetPkt <= `PKT_RDY;
|
NextState_slvGetPkt <= `PKT_RDY;
|
end
|
end
|
`PROC_PKT_DATA_CHK_D2:
|
`PROC_PKT_DATA_CHK_D2:
|
if (RXStreamStatus == `RX_PACKET_STREAM)
|
if (RXStreamStatus == `RX_PACKET_STREAM)
|
begin
|
begin
|
NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3;
|
NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3;
|
next_RXByteOld <= RXByte;
|
next_RXByteOld <= RXByte;
|
end
|
end
|
else
|
else
|
NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
|
NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
|
`PROC_PKT_DATA_W_D3:
|
`PROC_PKT_DATA_W_D3:
|
if (RXDataValid == 1'b1)
|
if (RXDataValid == 1'b1)
|
begin
|
begin
|
NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3;
|
NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3;
|
next_RXByte <= RXDataIn;
|
next_RXByte <= RXDataIn;
|
next_RXStreamStatus <= RXStreamStatusIn;
|
next_RXStreamStatus <= RXStreamStatusIn;
|
end
|
end
|
`PROC_PKT_DATA_CHK_D3:
|
`PROC_PKT_DATA_CHK_D3:
|
if (RXStreamStatus == `RX_PACKET_STREAM)
|
if (RXStreamStatus == `RX_PACKET_STREAM)
|
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
|
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
|
else
|
else
|
NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
|
NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
|
`PROC_PKT_DATA_LOOP_CHK_FIFO:
|
`PROC_PKT_DATA_LOOP_CHK_FIFO:
|
if (endPointReady == 1'b0)
|
if (endPointReady == 1'b0)
|
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_EP_N_RDY;
|
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_EP_N_RDY;
|
else if (RXFifoFull == 1'b1)
|
else if (RXFifoFull == 1'b1)
|
begin
|
begin
|
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
|
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
|
next_RXOverflow <= 1'b1;
|
next_RXOverflow <= 1'b1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
|
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
|
next_RXFifoWEn <= 1'b1;
|
next_RXFifoWEn <= 1'b1;
|
next_RXFifoData <= RXByteOldest;
|
next_RXFifoData <= RXByteOldest;
|
next_RXByteOldest <= RXByteOld;
|
next_RXByteOldest <= RXByteOld;
|
next_RXByteOld <= RXByte;
|
next_RXByteOld <= RXByte;
|
end
|
end
|
`PROC_PKT_DATA_LOOP_FIFO_FULL:
|
`PROC_PKT_DATA_LOOP_FIFO_FULL:
|
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
|
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
|
`PROC_PKT_DATA_LOOP_W_D:
|
`PROC_PKT_DATA_LOOP_W_D:
|
begin
|
begin
|
next_RXFifoWEn <= 1'b0;
|
next_RXFifoWEn <= 1'b0;
|
if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
|
if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
|
begin
|
begin
|
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_DELAY;
|
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_DELAY;
|
next_RXByte <= RXDataIn;
|
next_RXByte <= RXDataIn;
|
end
|
end
|
else if (RXDataValid == 1'b1)
|
else if (RXDataValid == 1'b1)
|
begin
|
begin
|
NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
|
NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
|
next_RXByte <= RXDataIn;
|
next_RXByte <= RXDataIn;
|
end
|
end
|
end
|
end
|
`PROC_PKT_DATA_LOOP_DELAY:
|
`PROC_PKT_DATA_LOOP_DELAY:
|
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
|
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
|
`PROC_PKT_DATA_LOOP_EP_N_RDY: // Discard data
|
`PROC_PKT_DATA_LOOP_EP_N_RDY: // Discard data
|
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
|
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
|
endcase
|
endcase
|
end
|
end
|
|
|
//----------------------------------
|
//----------------------------------
|
// Current State Logic (sequential)
|
// Current State Logic (sequential)
|
//----------------------------------
|
//----------------------------------
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin : slvGetPkt_CurrentState
|
begin : slvGetPkt_CurrentState
|
if (rst)
|
if (rst)
|
CurrState_slvGetPkt <= `START_GP;
|
CurrState_slvGetPkt <= `START_GP;
|
else
|
else
|
CurrState_slvGetPkt <= NextState_slvGetPkt;
|
CurrState_slvGetPkt <= NextState_slvGetPkt;
|
end
|
end
|
|
|
//----------------------------------
|
//----------------------------------
|
// Registered outputs logic
|
// Registered outputs logic
|
//----------------------------------
|
//----------------------------------
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin : slvGetPkt_RegOutput
|
begin : slvGetPkt_RegOutput
|
if (rst)
|
if (rst)
|
begin
|
begin
|
RXByteOld <= 8'h00;
|
RXByteOld <= 8'h00;
|
RXByteOldest <= 8'h00;
|
RXByteOldest <= 8'h00;
|
RXByte <= 8'h00;
|
RXByte <= 8'h00;
|
RXStreamStatus <= 8'h00;
|
RXStreamStatus <= 8'h00;
|
RXPacketRdy <= 1'b0;
|
RXPacketRdy <= 1'b0;
|
RXFifoWEn <= 1'b0;
|
RXFifoWEn <= 1'b0;
|
RXFifoData <= 8'h00;
|
RXFifoData <= 8'h00;
|
CRCError <= 1'b0;
|
CRCError <= 1'b0;
|
bitStuffError <= 1'b0;
|
bitStuffError <= 1'b0;
|
RXOverflow <= 1'b0;
|
RXOverflow <= 1'b0;
|
RXTimeOut <= 1'b0;
|
RXTimeOut <= 1'b0;
|
ACKRxed <= 1'b0;
|
ACKRxed <= 1'b0;
|
dataSequence <= 1'b0;
|
dataSequence <= 1'b0;
|
SIERxTimeOutEn <= 1'b0;
|
SIERxTimeOutEn <= 1'b0;
|
RxPID <= 4'h0;
|
RxPID <= 4'h0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
RXByteOld <= next_RXByteOld;
|
RXByteOld <= next_RXByteOld;
|
RXByteOldest <= next_RXByteOldest;
|
RXByteOldest <= next_RXByteOldest;
|
RXByte <= next_RXByte;
|
RXByte <= next_RXByte;
|
RXStreamStatus <= next_RXStreamStatus;
|
RXStreamStatus <= next_RXStreamStatus;
|
RXPacketRdy <= next_RXPacketRdy;
|
RXPacketRdy <= next_RXPacketRdy;
|
RXFifoWEn <= next_RXFifoWEn;
|
RXFifoWEn <= next_RXFifoWEn;
|
RXFifoData <= next_RXFifoData;
|
RXFifoData <= next_RXFifoData;
|
CRCError <= next_CRCError;
|
CRCError <= next_CRCError;
|
bitStuffError <= next_bitStuffError;
|
bitStuffError <= next_bitStuffError;
|
RXOverflow <= next_RXOverflow;
|
RXOverflow <= next_RXOverflow;
|
RXTimeOut <= next_RXTimeOut;
|
RXTimeOut <= next_RXTimeOut;
|
ACKRxed <= next_ACKRxed;
|
ACKRxed <= next_ACKRxed;
|
dataSequence <= next_dataSequence;
|
dataSequence <= next_dataSequence;
|
SIERxTimeOutEn <= next_SIERxTimeOutEn;
|
SIERxTimeOutEn <= next_SIERxTimeOutEn;
|
RxPID <= next_RxPID;
|
RxPID <= next_RxPID;
|
end
|
end
|
end
|
end
|
|
|
|
|
