|
|
// File : ../RTL/slaveController/slaveSendpacket.v
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// File : ../RTL/slaveController/slaveSendpacket.v
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// Generated : 10/06/06 19:35:33
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// Generated : 10/15/06 20:31:24
|
// From : ../RTL/slaveController/slaveSendpacket.asf
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// From : ../RTL/slaveController/slaveSendpacket.asf
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// By : FSM2VHDL ver. 5.0.0.9
|
// By : FSM2VHDL ver. 5.0.0.9
|
|
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
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//// slaveSendPacket
|
//// slaveSendPacket
|
//// ////
|
//// ////
|
//// This file is part of the usbhostslave opencores effort.
|
//// This file is part of the usbhostslave opencores effort.
|
//// http://www.opencores.org/cores/usbhostslave/ ////
|
//// http://www.opencores.org/cores/usbhostslave/ ////
|
//// ////
|
//// ////
|
//// Module Description: ////
|
//// Module Description: ////
|
////
|
////
|
//// ////
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//// ////
|
//// To Do: ////
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//// To Do: ////
|
////
|
////
|
//// ////
|
//// ////
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//// Author(s): ////
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//// Author(s): ////
|
//// - Steve Fielding, sfielding@base2designs.com ////
|
//// - Steve Fielding, sfielding@base2designs.com ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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`include "timescale.v"
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`include "timescale.v"
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbConstants_h.v"
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`include "usbConstants_h.v"
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|
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module slaveSendPacket (PID, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, clk, fifoData, fifoEmpty, fifoReadEn, rst, sendPacketRdy, sendPacketWEn);
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module slaveSendPacket (PID, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, clk, fifoData, fifoEmpty, fifoReadEn, rst, sendPacketRdy, sendPacketWEn);
|
input [3:0] PID;
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input [3:0] PID;
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input SCTxPortGnt;
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input SCTxPortGnt;
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input SCTxPortRdy;
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input SCTxPortRdy;
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input clk;
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input clk;
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input [7:0] fifoData;
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input [7:0] fifoData;
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input fifoEmpty;
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input fifoEmpty;
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input rst;
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input rst;
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input sendPacketWEn;
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input sendPacketWEn;
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output [7:0] SCTxPortCntl;
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output [7:0] SCTxPortCntl;
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output [7:0] SCTxPortData;
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output [7:0] SCTxPortData;
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output SCTxPortReq;
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output SCTxPortReq;
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output SCTxPortWEn;
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output SCTxPortWEn;
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output fifoReadEn;
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output fifoReadEn;
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output sendPacketRdy;
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output sendPacketRdy;
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|
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wire [3:0] PID;
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wire [3:0] PID;
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reg [7:0] SCTxPortCntl, next_SCTxPortCntl;
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reg [7:0] SCTxPortCntl, next_SCTxPortCntl;
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reg [7:0] SCTxPortData, next_SCTxPortData;
|
reg [7:0] SCTxPortData, next_SCTxPortData;
|
wire SCTxPortGnt;
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wire SCTxPortGnt;
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wire SCTxPortRdy;
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wire SCTxPortRdy;
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reg SCTxPortReq, next_SCTxPortReq;
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reg SCTxPortReq, next_SCTxPortReq;
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reg SCTxPortWEn, next_SCTxPortWEn;
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reg SCTxPortWEn, next_SCTxPortWEn;
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wire clk;
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wire clk;
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wire [7:0] fifoData;
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wire [7:0] fifoData;
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wire fifoEmpty;
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wire fifoEmpty;
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reg fifoReadEn, next_fifoReadEn;
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reg fifoReadEn, next_fifoReadEn;
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wire rst;
|
wire rst;
|
reg sendPacketRdy, next_sendPacketRdy;
|
reg sendPacketRdy, next_sendPacketRdy;
|
wire sendPacketWEn;
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wire sendPacketWEn;
|
|
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// diagram signals declarations
|
// diagram signals declarations
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reg [7:0]PIDNotPID;
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reg [7:0]PIDNotPID;
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|
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// BINARY ENCODED state machine: slvSndPkt
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// BINARY ENCODED state machine: slvSndPkt
|
// State codes definitions:
|
// State codes definitions:
|
`define START_SP1 4'b0000
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`define START_SP1 4'b0000
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`define SP_WAIT_ENABLE 4'b0001
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`define SP_WAIT_ENABLE 4'b0001
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`define SP1_WAIT_GNT 4'b0010
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`define SP1_WAIT_GNT 4'b0010
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`define SP_SEND_PID_WAIT_RDY 4'b0011
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`define SP_SEND_PID_WAIT_RDY 4'b0011
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`define SP_SEND_PID_FIN 4'b0100
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`define SP_SEND_PID_FIN 4'b0100
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`define FIN_SP1 4'b0101
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`define FIN_SP1 4'b0101
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`define SP_D0_D1_READ_FIFO 4'b0110
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`define SP_D0_D1_READ_FIFO 4'b0110
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`define SP_D0_D1_WAIT_READ_FIFO 4'b0111
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`define SP_D0_D1_WAIT_READ_FIFO 4'b0111
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`define SP_D0_D1_FIFO_EMPTY 4'b1000
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`define SP_D0_D1_FIFO_EMPTY 4'b1000
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`define SP_D0_D1_FIN 4'b1001
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`define SP_D0_D1_FIN 4'b1001
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`define SP_D0_D1_TERM_BYTE 4'b1010
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`define SP_D0_D1_TERM_BYTE 4'b1010
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`define SP_NOT_DATA 4'b1011
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`define SP_NOT_DATA 4'b1011
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`define SP_D0_D1_CLR_WEN 4'b1100
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`define SP_D0_D1_CLR_WEN 4'b1100
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`define SP_D0_D1_CLR_REN 4'b1101
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`define SP_D0_D1_CLR_REN 4'b1101
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|
|
reg [3:0] CurrState_slvSndPkt;
|
reg [3:0] CurrState_slvSndPkt;
|
reg [3:0] NextState_slvSndPkt;
|
reg [3:0] NextState_slvSndPkt;
|
|
|
// Diagram actions (continuous assignments allowed only: assign ...)
|
// Diagram actions (continuous assignments allowed only: assign ...)
|
|
|
always @(PID)
|
always @(PID)
|
begin
|
begin
|
PIDNotPID <= { (PID ^ 4'hf), PID };
|
PIDNotPID <= { (PID ^ 4'hf), PID };
|
end
|
end
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|
|
//--------------------------------------------------------------------
|
//--------------------------------------------------------------------
|
// Machine: slvSndPkt
|
// Machine: slvSndPkt
|
//--------------------------------------------------------------------
|
//--------------------------------------------------------------------
|
//----------------------------------
|
//----------------------------------
|
// Next State Logic (combinatorial)
|
// Next State Logic (combinatorial)
|
//----------------------------------
|
//----------------------------------
|
always @ (PIDNotPID or fifoData or sendPacketWEn or SCTxPortGnt or SCTxPortRdy or PID or fifoEmpty or sendPacketRdy or SCTxPortReq or SCTxPortWEn or SCTxPortData or SCTxPortCntl or fifoReadEn or CurrState_slvSndPkt)
|
always @ (PIDNotPID or fifoData or sendPacketWEn or SCTxPortGnt or SCTxPortRdy or PID or fifoEmpty or sendPacketRdy or SCTxPortReq or SCTxPortWEn or SCTxPortData or SCTxPortCntl or fifoReadEn or CurrState_slvSndPkt)
|
begin : slvSndPkt_NextState
|
begin : slvSndPkt_NextState
|
NextState_slvSndPkt <= CurrState_slvSndPkt;
|
NextState_slvSndPkt <= CurrState_slvSndPkt;
|
// Set default values for outputs and signals
|
// Set default values for outputs and signals
|
next_sendPacketRdy <= sendPacketRdy;
|
next_sendPacketRdy <= sendPacketRdy;
|
next_SCTxPortReq <= SCTxPortReq;
|
next_SCTxPortReq <= SCTxPortReq;
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next_SCTxPortWEn <= SCTxPortWEn;
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next_SCTxPortWEn <= SCTxPortWEn;
|
next_SCTxPortData <= SCTxPortData;
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next_SCTxPortData <= SCTxPortData;
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next_SCTxPortCntl <= SCTxPortCntl;
|
next_SCTxPortCntl <= SCTxPortCntl;
|
next_fifoReadEn <= fifoReadEn;
|
next_fifoReadEn <= fifoReadEn;
|
case (CurrState_slvSndPkt)
|
case (CurrState_slvSndPkt)
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`START_SP1:
|
`START_SP1:
|
NextState_slvSndPkt <= `SP_WAIT_ENABLE;
|
NextState_slvSndPkt <= `SP_WAIT_ENABLE;
|
`SP_WAIT_ENABLE:
|
`SP_WAIT_ENABLE:
|
if (sendPacketWEn == 1'b1)
|
if (sendPacketWEn == 1'b1)
|
begin
|
begin
|
NextState_slvSndPkt <= `SP1_WAIT_GNT;
|
NextState_slvSndPkt <= `SP1_WAIT_GNT;
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next_sendPacketRdy <= 1'b0;
|
next_sendPacketRdy <= 1'b0;
|
next_SCTxPortReq <= 1'b1;
|
next_SCTxPortReq <= 1'b1;
|
end
|
end
|
`SP1_WAIT_GNT:
|
`SP1_WAIT_GNT:
|
if (SCTxPortGnt == 1'b1)
|
if (SCTxPortGnt == 1'b1)
|
NextState_slvSndPkt <= `SP_SEND_PID_WAIT_RDY;
|
NextState_slvSndPkt <= `SP_SEND_PID_WAIT_RDY;
|
`FIN_SP1:
|
`FIN_SP1:
|
begin
|
begin
|
NextState_slvSndPkt <= `SP_WAIT_ENABLE;
|
NextState_slvSndPkt <= `SP_WAIT_ENABLE;
|
next_sendPacketRdy <= 1'b1;
|
next_sendPacketRdy <= 1'b1;
|
next_SCTxPortReq <= 1'b0;
|
next_SCTxPortReq <= 1'b0;
|
end
|
end
|
`SP_NOT_DATA:
|
`SP_NOT_DATA:
|
NextState_slvSndPkt <= `FIN_SP1;
|
NextState_slvSndPkt <= `FIN_SP1;
|
`SP_SEND_PID_WAIT_RDY:
|
`SP_SEND_PID_WAIT_RDY:
|
if (SCTxPortRdy == 1'b1)
|
if (SCTxPortRdy == 1'b1)
|
begin
|
begin
|
NextState_slvSndPkt <= `SP_SEND_PID_FIN;
|
NextState_slvSndPkt <= `SP_SEND_PID_FIN;
|
next_SCTxPortWEn <= 1'b1;
|
next_SCTxPortWEn <= 1'b1;
|
next_SCTxPortData <= PIDNotPID;
|
next_SCTxPortData <= PIDNotPID;
|
next_SCTxPortCntl <= `TX_PACKET_START;
|
next_SCTxPortCntl <= `TX_PACKET_START;
|
end
|
end
|
`SP_SEND_PID_FIN:
|
`SP_SEND_PID_FIN:
|
begin
|
begin
|
next_SCTxPortWEn <= 1'b0;
|
next_SCTxPortWEn <= 1'b0;
|
if (PID == `DATA0 || PID == `DATA1)
|
if (PID == `DATA0 || PID == `DATA1)
|
NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
|
NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
|
else
|
else
|
NextState_slvSndPkt <= `SP_NOT_DATA;
|
NextState_slvSndPkt <= `SP_NOT_DATA;
|
end
|
end
|
`SP_D0_D1_READ_FIFO:
|
`SP_D0_D1_READ_FIFO:
|
begin
|
begin
|
next_SCTxPortWEn <= 1'b1;
|
next_SCTxPortWEn <= 1'b1;
|
next_SCTxPortData <= fifoData;
|
next_SCTxPortData <= fifoData;
|
next_SCTxPortCntl <= `TX_PACKET_STREAM;
|
next_SCTxPortCntl <= `TX_PACKET_STREAM;
|
NextState_slvSndPkt <= `SP_D0_D1_CLR_WEN;
|
NextState_slvSndPkt <= `SP_D0_D1_CLR_WEN;
|
end
|
end
|
`SP_D0_D1_WAIT_READ_FIFO:
|
`SP_D0_D1_WAIT_READ_FIFO:
|
if (SCTxPortRdy == 1'b1)
|
if (SCTxPortRdy == 1'b1)
|
begin
|
begin
|
NextState_slvSndPkt <= `SP_D0_D1_CLR_REN;
|
NextState_slvSndPkt <= `SP_D0_D1_CLR_REN;
|
next_fifoReadEn <= 1'b1;
|
next_fifoReadEn <= 1'b1;
|
end
|
end
|
`SP_D0_D1_FIFO_EMPTY:
|
`SP_D0_D1_FIFO_EMPTY:
|
if (fifoEmpty == 1'b0)
|
if (fifoEmpty == 1'b0)
|
NextState_slvSndPkt <= `SP_D0_D1_WAIT_READ_FIFO;
|
NextState_slvSndPkt <= `SP_D0_D1_WAIT_READ_FIFO;
|
else
|
else
|
NextState_slvSndPkt <= `SP_D0_D1_TERM_BYTE;
|
NextState_slvSndPkt <= `SP_D0_D1_TERM_BYTE;
|
`SP_D0_D1_FIN:
|
`SP_D0_D1_FIN:
|
begin
|
begin
|
next_SCTxPortWEn <= 1'b0;
|
next_SCTxPortWEn <= 1'b0;
|
NextState_slvSndPkt <= `FIN_SP1;
|
NextState_slvSndPkt <= `FIN_SP1;
|
end
|
end
|
`SP_D0_D1_TERM_BYTE:
|
`SP_D0_D1_TERM_BYTE:
|
if (SCTxPortRdy == 1'b1)
|
if (SCTxPortRdy == 1'b1)
|
begin
|
begin
|
NextState_slvSndPkt <= `SP_D0_D1_FIN;
|
NextState_slvSndPkt <= `SP_D0_D1_FIN;
|
//Last byte is not valid data,
|
//Last byte is not valid data,
|
//but the 'TX_PACKET_STOP' flag is required
|
//but the 'TX_PACKET_STOP' flag is required
|
//by the SIE state machine to detect end of data packet
|
//by the SIE state machine to detect end of data packet
|
next_SCTxPortWEn <= 1'b1;
|
next_SCTxPortWEn <= 1'b1;
|
next_SCTxPortData <= 8'h00;
|
next_SCTxPortData <= 8'h00;
|
next_SCTxPortCntl <= `TX_PACKET_STOP;
|
next_SCTxPortCntl <= `TX_PACKET_STOP;
|
end
|
end
|
`SP_D0_D1_CLR_WEN:
|
`SP_D0_D1_CLR_WEN:
|
begin
|
begin
|
next_SCTxPortWEn <= 1'b0;
|
next_SCTxPortWEn <= 1'b0;
|
NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
|
NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
|
end
|
end
|
`SP_D0_D1_CLR_REN:
|
`SP_D0_D1_CLR_REN:
|
begin
|
begin
|
next_fifoReadEn <= 1'b0;
|
next_fifoReadEn <= 1'b0;
|
NextState_slvSndPkt <= `SP_D0_D1_READ_FIFO;
|
NextState_slvSndPkt <= `SP_D0_D1_READ_FIFO;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
//----------------------------------
|
//----------------------------------
|
// Current State Logic (sequential)
|
// Current State Logic (sequential)
|
//----------------------------------
|
//----------------------------------
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin : slvSndPkt_CurrentState
|
begin : slvSndPkt_CurrentState
|
if (rst)
|
if (rst)
|
CurrState_slvSndPkt <= `START_SP1;
|
CurrState_slvSndPkt <= `START_SP1;
|
else
|
else
|
CurrState_slvSndPkt <= NextState_slvSndPkt;
|
CurrState_slvSndPkt <= NextState_slvSndPkt;
|
end
|
end
|
|
|
//----------------------------------
|
//----------------------------------
|
// Registered outputs logic
|
// Registered outputs logic
|
//----------------------------------
|
//----------------------------------
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin : slvSndPkt_RegOutput
|
begin : slvSndPkt_RegOutput
|
if (rst)
|
if (rst)
|
begin
|
begin
|
sendPacketRdy <= 1'b1;
|
sendPacketRdy <= 1'b1;
|
SCTxPortReq <= 1'b0;
|
SCTxPortReq <= 1'b0;
|
SCTxPortWEn <= 1'b0;
|
SCTxPortWEn <= 1'b0;
|
SCTxPortData <= 8'h00;
|
SCTxPortData <= 8'h00;
|
SCTxPortCntl <= 8'h00;
|
SCTxPortCntl <= 8'h00;
|
fifoReadEn <= 1'b0;
|
fifoReadEn <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
sendPacketRdy <= next_sendPacketRdy;
|
sendPacketRdy <= next_sendPacketRdy;
|
SCTxPortReq <= next_SCTxPortReq;
|
SCTxPortReq <= next_SCTxPortReq;
|
SCTxPortWEn <= next_SCTxPortWEn;
|
SCTxPortWEn <= next_SCTxPortWEn;
|
SCTxPortData <= next_SCTxPortData;
|
SCTxPortData <= next_SCTxPortData;
|
SCTxPortCntl <= next_SCTxPortCntl;
|
SCTxPortCntl <= next_SCTxPortCntl;
|
fifoReadEn <= next_fifoReadEn;
|
fifoReadEn <= next_fifoReadEn;
|
end
|
end
|
end
|
end
|
|
|
|
|
