//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// usbSlaveControl.v ////
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//// usbSlaveControl.v ////
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//// ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// ////
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//// Module Description: ////
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//// Module Description: ////
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////
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////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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////
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////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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`timescale 1ns / 1ps
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`include "timescale.v"
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|
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module usbSlaveControl(
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module usbSlaveControl(
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busClk,
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busClk,
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rstSyncToBusClk,
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rstSyncToBusClk,
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usbClk,
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usbClk,
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rstSyncToUsbClk,
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rstSyncToUsbClk,
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//getPacket
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//getPacket
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RxByteStatus, RxData, RxDataValid,
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RxByteStatus, RxData, RxDataValid,
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SIERxTimeOut, RxFifoData, SIERxTimeOutEn,
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SIERxTimeOut, RxFifoData, SIERxTimeOutEn,
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//speedCtrlMux
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//speedCtrlMux
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fullSpeedRate, fullSpeedPol,
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fullSpeedRate, fullSpeedPol,
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//SCTxPortArbiter
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//SCTxPortArbiter
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SCTxPortEn, SCTxPortRdy,
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SCTxPortEn, SCTxPortRdy,
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SCTxPortData, SCTxPortCtrl,
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SCTxPortData, SCTxPortCtrl,
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//rxStatusMonitor
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//rxStatusMonitor
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connectStateIn,
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connectStateIn,
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resumeDetectedIn,
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resumeDetectedIn,
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//USBHostControlBI
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//USBHostControlBI
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busAddress,
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busAddress,
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busDataIn,
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busDataIn,
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busDataOut,
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busDataOut,
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busWriteEn,
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busWriteEn,
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busStrobe_i,
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busStrobe_i,
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SOFRxedIntOut,
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SOFRxedIntOut,
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resetEventIntOut,
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resetEventIntOut,
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resumeIntOut,
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resumeIntOut,
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transDoneIntOut,
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transDoneIntOut,
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NAKSentIntOut,
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NAKSentIntOut,
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slaveControlSelect,
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slaveControlSelect,
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//fifoMux
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//fifoMux
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TxFifoEP0REn,
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TxFifoEP0REn,
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TxFifoEP1REn,
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TxFifoEP1REn,
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TxFifoEP2REn,
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TxFifoEP2REn,
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TxFifoEP3REn,
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TxFifoEP3REn,
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TxFifoEP0Data,
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TxFifoEP0Data,
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TxFifoEP1Data,
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TxFifoEP1Data,
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TxFifoEP2Data,
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TxFifoEP2Data,
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TxFifoEP3Data,
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TxFifoEP3Data,
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TxFifoEP0Empty,
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TxFifoEP0Empty,
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TxFifoEP1Empty,
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TxFifoEP1Empty,
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TxFifoEP2Empty,
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TxFifoEP2Empty,
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TxFifoEP3Empty,
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TxFifoEP3Empty,
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RxFifoEP0WEn,
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RxFifoEP0WEn,
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RxFifoEP1WEn,
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RxFifoEP1WEn,
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RxFifoEP2WEn,
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RxFifoEP2WEn,
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RxFifoEP3WEn,
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RxFifoEP3WEn,
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RxFifoEP0Full,
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RxFifoEP0Full,
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RxFifoEP1Full,
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RxFifoEP1Full,
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RxFifoEP2Full,
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RxFifoEP2Full,
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RxFifoEP3Full
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RxFifoEP3Full
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);
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);
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|
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input busClk;
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input busClk;
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input rstSyncToBusClk;
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input rstSyncToBusClk;
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input usbClk;
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input usbClk;
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input rstSyncToUsbClk;
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input rstSyncToUsbClk;
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//getPacket
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//getPacket
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input [7:0] RxByteStatus;
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input [7:0] RxByteStatus;
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input [7:0] RxData;
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input [7:0] RxData;
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input RxDataValid;
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input RxDataValid;
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input SIERxTimeOut;
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input SIERxTimeOut;
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output SIERxTimeOutEn;
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output SIERxTimeOutEn;
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output [7:0] RxFifoData;
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output [7:0] RxFifoData;
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//speedCtrlMux
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//speedCtrlMux
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output fullSpeedRate;
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output fullSpeedRate;
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output fullSpeedPol;
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output fullSpeedPol;
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//HCTxPortArbiter
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//HCTxPortArbiter
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output SCTxPortEn;
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output SCTxPortEn;
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input SCTxPortRdy;
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input SCTxPortRdy;
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output [7:0] SCTxPortData;
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output [7:0] SCTxPortData;
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output [7:0] SCTxPortCtrl;
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output [7:0] SCTxPortCtrl;
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//rxStatusMonitor
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//rxStatusMonitor
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input [1:0] connectStateIn;
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input [1:0] connectStateIn;
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input resumeDetectedIn;
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input resumeDetectedIn;
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//USBHostControlBI
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//USBHostControlBI
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input [4:0] busAddress;
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input [4:0] busAddress;
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input [7:0] busDataIn;
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input [7:0] busDataIn;
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output [7:0] busDataOut;
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output [7:0] busDataOut;
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input busWriteEn;
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input busWriteEn;
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input busStrobe_i;
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input busStrobe_i;
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output SOFRxedIntOut;
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output SOFRxedIntOut;
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output resetEventIntOut;
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output resetEventIntOut;
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output resumeIntOut;
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output resumeIntOut;
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output transDoneIntOut;
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output transDoneIntOut;
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output NAKSentIntOut;
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output NAKSentIntOut;
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input slaveControlSelect;
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input slaveControlSelect;
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//fifoMux
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//fifoMux
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output TxFifoEP0REn;
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output TxFifoEP0REn;
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output TxFifoEP1REn;
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output TxFifoEP1REn;
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output TxFifoEP2REn;
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output TxFifoEP2REn;
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output TxFifoEP3REn;
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output TxFifoEP3REn;
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input [7:0] TxFifoEP0Data;
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input [7:0] TxFifoEP0Data;
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input [7:0] TxFifoEP1Data;
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input [7:0] TxFifoEP1Data;
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input [7:0] TxFifoEP2Data;
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input [7:0] TxFifoEP2Data;
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input [7:0] TxFifoEP3Data;
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input [7:0] TxFifoEP3Data;
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input TxFifoEP0Empty;
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input TxFifoEP0Empty;
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input TxFifoEP1Empty;
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input TxFifoEP1Empty;
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input TxFifoEP2Empty;
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input TxFifoEP2Empty;
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input TxFifoEP3Empty;
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input TxFifoEP3Empty;
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output RxFifoEP0WEn;
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output RxFifoEP0WEn;
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output RxFifoEP1WEn;
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output RxFifoEP1WEn;
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output RxFifoEP2WEn;
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output RxFifoEP2WEn;
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output RxFifoEP3WEn;
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output RxFifoEP3WEn;
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input RxFifoEP0Full;
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input RxFifoEP0Full;
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input RxFifoEP1Full;
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input RxFifoEP1Full;
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input RxFifoEP2Full;
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input RxFifoEP2Full;
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input RxFifoEP3Full;
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input RxFifoEP3Full;
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|
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wire busClk;
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wire busClk;
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wire rstSyncToBusClk;
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wire rstSyncToBusClk;
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wire usbClk;
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wire usbClk;
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wire rstSyncToUsbClk;
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wire rstSyncToUsbClk;
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wire [7:0] RxByteStatus;
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wire [7:0] RxByteStatus;
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wire [7:0] RxData;
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wire [7:0] RxData;
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wire RxDataValid;
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wire RxDataValid;
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wire SIERxTimeOut;
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wire SIERxTimeOut;
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wire SIERxTimeOutEn;
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wire SIERxTimeOutEn;
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wire [7:0] RxFifoData;
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wire [7:0] RxFifoData;
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wire fullSpeedRate;
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wire fullSpeedRate;
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wire fullSpeedPol;
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wire fullSpeedPol;
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wire [7:0] SCTxPortData;
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wire [7:0] SCTxPortData;
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wire [7:0] SCTxPortCtrl;
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wire [7:0] SCTxPortCtrl;
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wire [1:0] connectStateIn;
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wire [1:0] connectStateIn;
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wire resumeDetectedIn;
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wire resumeDetectedIn;
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wire [4:0] busAddress;
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wire [4:0] busAddress;
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wire [7:0] busDataIn;
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wire [7:0] busDataIn;
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wire [7:0] busDataOut;
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wire [7:0] busDataOut;
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wire busWriteEn;
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wire busWriteEn;
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wire busStrobe_i;
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wire busStrobe_i;
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wire SOFRxedIntOut;
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wire SOFRxedIntOut;
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wire resetEventIntOut;
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wire resetEventIntOut;
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wire resumeIntOut;
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wire resumeIntOut;
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wire transDoneIntOut;
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wire transDoneIntOut;
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wire NAKSentIntOut;
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wire NAKSentIntOut;
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wire slaveControlSelect;
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wire slaveControlSelect;
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wire TxFifoEP0REn;
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wire TxFifoEP0REn;
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wire TxFifoEP1REn;
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wire TxFifoEP1REn;
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wire TxFifoEP2REn;
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wire TxFifoEP2REn;
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wire TxFifoEP3REn;
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wire TxFifoEP3REn;
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wire [7:0] TxFifoEP0Data;
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wire [7:0] TxFifoEP0Data;
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wire [7:0] TxFifoEP1Data;
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wire [7:0] TxFifoEP1Data;
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wire [7:0] TxFifoEP2Data;
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wire [7:0] TxFifoEP2Data;
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wire [7:0] TxFifoEP3Data;
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wire [7:0] TxFifoEP3Data;
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wire TxFifoEP0Empty;
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wire TxFifoEP0Empty;
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wire TxFifoEP1Empty;
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wire TxFifoEP1Empty;
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wire TxFifoEP2Empty;
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wire TxFifoEP2Empty;
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wire TxFifoEP3Empty;
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wire TxFifoEP3Empty;
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wire RxFifoEP0WEn;
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wire RxFifoEP0WEn;
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wire RxFifoEP1WEn;
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wire RxFifoEP1WEn;
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wire RxFifoEP2WEn;
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wire RxFifoEP2WEn;
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wire RxFifoEP3WEn;
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wire RxFifoEP3WEn;
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wire RxFifoEP0Full;
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wire RxFifoEP0Full;
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wire RxFifoEP1Full;
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wire RxFifoEP1Full;
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wire RxFifoEP2Full;
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wire RxFifoEP2Full;
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wire RxFifoEP3Full;
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wire RxFifoEP3Full;
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//internal wiring
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//internal wiring
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wire [7:0] directCntlCntl;
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wire [7:0] directCntlCntl;
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wire [7:0] directCntlData;
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wire [7:0] directCntlData;
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wire directCntlGnt;
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wire directCntlGnt;
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wire directCntlReq;
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wire directCntlReq;
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wire directCntlWEn;
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wire directCntlWEn;
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wire [7:0] sendPacketCntl;
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wire [7:0] sendPacketCntl;
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wire [7:0] sendPacketData;
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wire [7:0] sendPacketData;
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wire sendPacketGnt;
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wire sendPacketGnt;
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wire sendPacketReq;
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wire sendPacketReq;
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wire sendPacketWEn;
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wire sendPacketWEn;
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wire SCTxPortArbRdyOut;
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wire SCTxPortArbRdyOut;
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wire transDone;
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wire transDone;
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wire [1:0] directLineState;
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wire [1:0] directLineState;
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wire directLineCtrlEn;
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wire directLineCtrlEn;
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wire [3:0] RxPID;
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wire [3:0] RxPID;
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wire [1:0] connectStateOut;
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wire [1:0] connectStateOut;
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wire resumeIntFromRxStatusMon;
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wire resumeIntFromRxStatusMon;
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wire [1:0] endP0TransTypeReg;
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wire [1:0] endP0TransTypeReg;
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wire [1:0] endP1TransTypeReg;
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wire [1:0] endP1TransTypeReg;
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wire [1:0] endP2TransTypeReg;
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wire [1:0] endP2TransTypeReg;
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wire [1:0] endP3TransTypeReg;
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wire [1:0] endP3TransTypeReg;
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wire [1:0] endP0NAKTransTypeReg;
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wire [1:0] endP0NAKTransTypeReg;
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wire [1:0] endP1NAKTransTypeReg;
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wire [1:0] endP1NAKTransTypeReg;
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wire [1:0] endP2NAKTransTypeReg;
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wire [1:0] endP2NAKTransTypeReg;
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wire [1:0] endP3NAKTransTypeReg;
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wire [1:0] endP3NAKTransTypeReg;
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wire [4:0] endP0ControlReg;
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wire [4:0] endP0ControlReg;
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wire [4:0] endP1ControlReg;
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wire [4:0] endP1ControlReg;
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wire [4:0] endP2ControlReg;
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wire [4:0] endP2ControlReg;
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wire [4:0] endP3ControlReg;
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wire [4:0] endP3ControlReg;
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wire [7:0] endP0StatusReg;
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wire [7:0] endP0StatusReg;
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wire [7:0] endP1StatusReg;
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wire [7:0] endP1StatusReg;
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wire [7:0] endP2StatusReg;
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wire [7:0] endP2StatusReg;
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wire [7:0] endP3StatusReg;
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wire [7:0] endP3StatusReg;
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wire [6:0] USBTgtAddress;
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wire [6:0] USBTgtAddress;
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wire [10:0] frameNum;
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wire [10:0] frameNum;
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wire clrEP0Rdy;
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wire clrEP0Rdy;
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wire clrEP1Rdy;
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wire clrEP1Rdy;
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wire clrEP2Rdy;
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wire clrEP2Rdy;
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wire clrEP3Rdy;
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wire clrEP3Rdy;
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wire SCGlobalEn;
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wire SCGlobalEn;
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wire ACKRxed;
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wire ACKRxed;
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wire CRCError;
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wire CRCError;
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wire RXOverflow;
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wire RXOverflow;
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wire RXTimeOut;
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wire RXTimeOut;
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wire bitStuffError;
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wire bitStuffError;
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wire dataSequence;
|
wire dataSequence;
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wire stallSent;
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wire stallSent;
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wire NAKSent;
|
wire NAKSent;
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wire SOFRxed;
|
wire SOFRxed;
|
wire [4:0] endPControlReg;
|
wire [4:0] endPControlReg;
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wire [1:0] transTypeNAK;
|
wire [1:0] transTypeNAK;
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wire [1:0] transType;
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wire [1:0] transType;
|
wire [3:0] currEndP;
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wire [3:0] currEndP;
|
wire getPacketREn;
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wire getPacketREn;
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wire getPacketRdy;
|
wire getPacketRdy;
|
wire [3:0] slaveControllerPIDOut;
|
wire [3:0] slaveControllerPIDOut;
|
wire slaveControllerReadyIn;
|
wire slaveControllerReadyIn;
|
wire slaveControllerWEnOut;
|
wire slaveControllerWEnOut;
|
wire TxFifoRE;
|
wire TxFifoRE;
|
wire [7:0] TxFifoData;
|
wire [7:0] TxFifoData;
|
wire TxFifoEmpty;
|
wire TxFifoEmpty;
|
wire RxFifoWE;
|
wire RxFifoWE;
|
wire RxFifoFull;
|
wire RxFifoFull;
|
wire resetEventFromRxStatusMon;
|
wire resetEventFromRxStatusMon;
|
wire clrEPRdy;
|
wire clrEPRdy;
|
wire endPMuxErrorsWEn;
|
wire endPMuxErrorsWEn;
|
wire endPointReadyFromSlaveCtrlrToGetPkt;
|
wire endPointReadyFromSlaveCtrlrToGetPkt;
|
|
|
USBSlaveControlBI u_USBSlaveControlBI
|
USBSlaveControlBI u_USBSlaveControlBI
|
(.address(busAddress),
|
(.address(busAddress),
|
.dataIn(busDataIn),
|
.dataIn(busDataIn),
|
.dataOut(busDataOut),
|
.dataOut(busDataOut),
|
.writeEn(busWriteEn),
|
.writeEn(busWriteEn),
|
.strobe_i(busStrobe_i),
|
.strobe_i(busStrobe_i),
|
.busClk(busClk),
|
.busClk(busClk),
|
.rstSyncToBusClk(rstSyncToBusClk),
|
.rstSyncToBusClk(rstSyncToBusClk),
|
.usbClk(usbClk),
|
.usbClk(usbClk),
|
.rstSyncToUsbClk(rstSyncToUsbClk),
|
.rstSyncToUsbClk(rstSyncToUsbClk),
|
.SOFRxedIntOut(SOFRxedIntOut),
|
.SOFRxedIntOut(SOFRxedIntOut),
|
.resetEventIntOut(resetEventIntOut),
|
.resetEventIntOut(resetEventIntOut),
|
.resumeIntOut(resumeIntOut),
|
.resumeIntOut(resumeIntOut),
|
.transDoneIntOut(transDoneIntOut),
|
.transDoneIntOut(transDoneIntOut),
|
.NAKSentIntOut(NAKSentIntOut),
|
.NAKSentIntOut(NAKSentIntOut),
|
.endP0TransTypeReg(endP0TransTypeReg),
|
.endP0TransTypeReg(endP0TransTypeReg),
|
.endP0NAKTransTypeReg(endP0NAKTransTypeReg),
|
.endP0NAKTransTypeReg(endP0NAKTransTypeReg),
|
.endP1TransTypeReg(endP1TransTypeReg),
|
.endP1TransTypeReg(endP1TransTypeReg),
|
.endP1NAKTransTypeReg(endP1NAKTransTypeReg),
|
.endP1NAKTransTypeReg(endP1NAKTransTypeReg),
|
.endP2TransTypeReg(endP2TransTypeReg),
|
.endP2TransTypeReg(endP2TransTypeReg),
|
.endP2NAKTransTypeReg(endP2NAKTransTypeReg),
|
.endP2NAKTransTypeReg(endP2NAKTransTypeReg),
|
.endP3TransTypeReg(endP3TransTypeReg),
|
.endP3TransTypeReg(endP3TransTypeReg),
|
.endP3NAKTransTypeReg(endP3NAKTransTypeReg),
|
.endP3NAKTransTypeReg(endP3NAKTransTypeReg),
|
.endP0ControlReg(endP0ControlReg),
|
.endP0ControlReg(endP0ControlReg),
|
.endP1ControlReg(endP1ControlReg),
|
.endP1ControlReg(endP1ControlReg),
|
.endP2ControlReg(endP2ControlReg),
|
.endP2ControlReg(endP2ControlReg),
|
.endP3ControlReg(endP3ControlReg),
|
.endP3ControlReg(endP3ControlReg),
|
.EP0StatusReg(endP0StatusReg),
|
.EP0StatusReg(endP0StatusReg),
|
.EP1StatusReg(endP1StatusReg),
|
.EP1StatusReg(endP1StatusReg),
|
.EP2StatusReg(endP2StatusReg),
|
.EP2StatusReg(endP2StatusReg),
|
.EP3StatusReg(endP3StatusReg),
|
.EP3StatusReg(endP3StatusReg),
|
.SCAddrReg(USBTgtAddress),
|
.SCAddrReg(USBTgtAddress),
|
.frameNum(frameNum),
|
.frameNum(frameNum),
|
.connectStateIn(connectStateOut),
|
.connectStateIn(connectStateOut),
|
.SOFRxedIn(SOFRxed),
|
.SOFRxedIn(SOFRxed),
|
.resetEventIn(resetEventFromRxStatusMon),
|
.resetEventIn(resetEventFromRxStatusMon),
|
.resumeIntIn(resumeIntFromRxStatusMon),
|
.resumeIntIn(resumeIntFromRxStatusMon),
|
.transDoneIn(transDone),
|
.transDoneIn(transDone),
|
.NAKSentIn(NAKSent),
|
.NAKSentIn(NAKSent),
|
.slaveControlSelect(slaveControlSelect),
|
.slaveControlSelect(slaveControlSelect),
|
.clrEP0Ready(clrEP0Rdy),
|
.clrEP0Ready(clrEP0Rdy),
|
.clrEP1Ready(clrEP1Rdy),
|
.clrEP1Ready(clrEP1Rdy),
|
.clrEP2Ready(clrEP2Rdy),
|
.clrEP2Ready(clrEP2Rdy),
|
.clrEP3Ready(clrEP3Rdy),
|
.clrEP3Ready(clrEP3Rdy),
|
.TxLineState(directLineState),
|
.TxLineState(directLineState),
|
.LineDirectControlEn(directLineCtrlEn),
|
.LineDirectControlEn(directLineCtrlEn),
|
.fullSpeedPol(fullSpeedPol),
|
.fullSpeedPol(fullSpeedPol),
|
.fullSpeedRate(fullSpeedRate),
|
.fullSpeedRate(fullSpeedRate),
|
.SCGlobalEn(SCGlobalEn)
|
.SCGlobalEn(SCGlobalEn)
|
);
|
);
|
|
|
slavecontroller u_slavecontroller
|
slavecontroller u_slavecontroller
|
(.CRCError(CRCError),
|
(.CRCError(CRCError),
|
.NAKSent(NAKSent),
|
.NAKSent(NAKSent),
|
.RxByte(RxData),
|
.RxByte(RxData),
|
.RxDataWEn(RxDataValid),
|
.RxDataWEn(RxDataValid),
|
.RxOverflow(RXOverflow),
|
.RxOverflow(RXOverflow),
|
.RxStatus(RxByteStatus),
|
.RxStatus(RxByteStatus),
|
.RxTimeOut(RXTimeOut),
|
.RxTimeOut(RXTimeOut),
|
.SCGlobalEn(SCGlobalEn),
|
.SCGlobalEn(SCGlobalEn),
|
.SOFRxed(SOFRxed),
|
.SOFRxed(SOFRxed),
|
.USBEndPControlReg(endPControlReg),
|
.USBEndPControlReg(endPControlReg),
|
.USBEndPNakTransTypeReg(transTypeNAK),
|
.USBEndPNakTransTypeReg(transTypeNAK),
|
.USBEndPTransTypeReg(transType),
|
.USBEndPTransTypeReg(transType),
|
.USBEndP(currEndP),
|
.USBEndP(currEndP),
|
.USBTgtAddress(USBTgtAddress),
|
.USBTgtAddress(USBTgtAddress),
|
.bitStuffError(bitStuffError),
|
.bitStuffError(bitStuffError),
|
.clk(usbClk),
|
.clk(usbClk),
|
.clrEPRdy(clrEPRdy),
|
.clrEPRdy(clrEPRdy),
|
.endPMuxErrorsWEn(endPMuxErrorsWEn),
|
.endPMuxErrorsWEn(endPMuxErrorsWEn),
|
.frameNum(frameNum),
|
.frameNum(frameNum),
|
.getPacketREn(getPacketREn),
|
.getPacketREn(getPacketREn),
|
.getPacketRdy(getPacketRdy),
|
.getPacketRdy(getPacketRdy),
|
.rst(rstSyncToUsbClk),
|
.rst(rstSyncToUsbClk),
|
.sendPacketPID(slaveControllerPIDOut),
|
.sendPacketPID(slaveControllerPIDOut),
|
.sendPacketRdy(slaveControllerReadyIn),
|
.sendPacketRdy(slaveControllerReadyIn),
|
.sendPacketWEn(slaveControllerWEnOut),
|
.sendPacketWEn(slaveControllerWEnOut),
|
.stallSent(stallSent),
|
.stallSent(stallSent),
|
.transDone(transDone),
|
.transDone(transDone),
|
.endPointReadyToGetPkt(endPointReadyFromSlaveCtrlrToGetPkt)
|
.endPointReadyToGetPkt(endPointReadyFromSlaveCtrlrToGetPkt)
|
);
|
);
|
|
|
|
|
endpMux u_endpMux (
|
endpMux u_endpMux (
|
.clk(usbClk),
|
.clk(usbClk),
|
.rst(rstSyncToUsbClk),
|
.rst(rstSyncToUsbClk),
|
.currEndP(currEndP),
|
.currEndP(currEndP),
|
.NAKSent(NAKSent),
|
.NAKSent(NAKSent),
|
.stallSent(stallSent),
|
.stallSent(stallSent),
|
.CRCError(CRCError),
|
.CRCError(CRCError),
|
.bitStuffError(bitStuffError),
|
.bitStuffError(bitStuffError),
|
.RxOverflow(RXOverflow),
|
.RxOverflow(RXOverflow),
|
.RxTimeOut(RXTimeOut),
|
.RxTimeOut(RXTimeOut),
|
.dataSequence(dataSequence),
|
.dataSequence(dataSequence),
|
.ACKRxed(ACKRxed),
|
.ACKRxed(ACKRxed),
|
.transType(transType),
|
.transType(transType),
|
.transTypeNAK(transTypeNAK),
|
.transTypeNAK(transTypeNAK),
|
.endPControlReg(endPControlReg),
|
.endPControlReg(endPControlReg),
|
.clrEPRdy(clrEPRdy),
|
.clrEPRdy(clrEPRdy),
|
.endPMuxErrorsWEn(endPMuxErrorsWEn),
|
.endPMuxErrorsWEn(endPMuxErrorsWEn),
|
.endP0ControlReg(endP0ControlReg),
|
.endP0ControlReg(endP0ControlReg),
|
.endP1ControlReg(endP1ControlReg),
|
.endP1ControlReg(endP1ControlReg),
|
.endP2ControlReg(endP2ControlReg),
|
.endP2ControlReg(endP2ControlReg),
|
.endP3ControlReg(endP3ControlReg),
|
.endP3ControlReg(endP3ControlReg),
|
.endP0StatusReg(endP0StatusReg),
|
.endP0StatusReg(endP0StatusReg),
|
.endP1StatusReg(endP1StatusReg),
|
.endP1StatusReg(endP1StatusReg),
|
.endP2StatusReg(endP2StatusReg),
|
.endP2StatusReg(endP2StatusReg),
|
.endP3StatusReg(endP3StatusReg),
|
.endP3StatusReg(endP3StatusReg),
|
.endP0TransTypeReg(endP0TransTypeReg),
|
.endP0TransTypeReg(endP0TransTypeReg),
|
.endP1TransTypeReg(endP1TransTypeReg),
|
.endP1TransTypeReg(endP1TransTypeReg),
|
.endP2TransTypeReg(endP2TransTypeReg),
|
.endP2TransTypeReg(endP2TransTypeReg),
|
.endP3TransTypeReg(endP3TransTypeReg),
|
.endP3TransTypeReg(endP3TransTypeReg),
|
.endP0NAKTransTypeReg(endP0NAKTransTypeReg),
|
.endP0NAKTransTypeReg(endP0NAKTransTypeReg),
|
.endP1NAKTransTypeReg(endP1NAKTransTypeReg),
|
.endP1NAKTransTypeReg(endP1NAKTransTypeReg),
|
.endP2NAKTransTypeReg(endP2NAKTransTypeReg),
|
.endP2NAKTransTypeReg(endP2NAKTransTypeReg),
|
.endP3NAKTransTypeReg(endP3NAKTransTypeReg),
|
.endP3NAKTransTypeReg(endP3NAKTransTypeReg),
|
.clrEP0Rdy(clrEP0Rdy),
|
.clrEP0Rdy(clrEP0Rdy),
|
.clrEP1Rdy(clrEP1Rdy),
|
.clrEP1Rdy(clrEP1Rdy),
|
.clrEP2Rdy(clrEP2Rdy),
|
.clrEP2Rdy(clrEP2Rdy),
|
.clrEP3Rdy(clrEP3Rdy)
|
.clrEP3Rdy(clrEP3Rdy)
|
);
|
);
|
|
|
slaveSendPacket u_slaveSendPacket
|
slaveSendPacket u_slaveSendPacket
|
(.PID(slaveControllerPIDOut),
|
(.PID(slaveControllerPIDOut),
|
.SCTxPortCntl(sendPacketCntl),
|
.SCTxPortCntl(sendPacketCntl),
|
.SCTxPortData(sendPacketData),
|
.SCTxPortData(sendPacketData),
|
.SCTxPortGnt(sendPacketGnt),
|
.SCTxPortGnt(sendPacketGnt),
|
.SCTxPortRdy(SCTxPortArbRdyOut),
|
.SCTxPortRdy(SCTxPortArbRdyOut),
|
.SCTxPortReq(sendPacketReq),
|
.SCTxPortReq(sendPacketReq),
|
.SCTxPortWEn(sendPacketWEn),
|
.SCTxPortWEn(sendPacketWEn),
|
.clk(usbClk),
|
.clk(usbClk),
|
.fifoData(TxFifoData),
|
.fifoData(TxFifoData),
|
.fifoEmpty(TxFifoEmpty),
|
.fifoEmpty(TxFifoEmpty),
|
.fifoReadEn(TxFifoRE),
|
.fifoReadEn(TxFifoRE),
|
.rst(rstSyncToUsbClk),
|
.rst(rstSyncToUsbClk),
|
.sendPacketRdy(slaveControllerReadyIn),
|
.sendPacketRdy(slaveControllerReadyIn),
|
.sendPacketWEn(slaveControllerWEnOut) );
|
.sendPacketWEn(slaveControllerWEnOut) );
|
|
|
slaveDirectControl u_slaveDirectControl
|
slaveDirectControl u_slaveDirectControl
|
(.SCTxPortCntl(directCntlCntl),
|
(.SCTxPortCntl(directCntlCntl),
|
.SCTxPortData(directCntlData),
|
.SCTxPortData(directCntlData),
|
.SCTxPortGnt(directCntlGnt),
|
.SCTxPortGnt(directCntlGnt),
|
.SCTxPortRdy(SCTxPortArbRdyOut),
|
.SCTxPortRdy(SCTxPortArbRdyOut),
|
.SCTxPortReq(directCntlReq),
|
.SCTxPortReq(directCntlReq),
|
.SCTxPortWEn(directCntlWEn),
|
.SCTxPortWEn(directCntlWEn),
|
.clk(usbClk),
|
.clk(usbClk),
|
.directControlEn(directLineCtrlEn),
|
.directControlEn(directLineCtrlEn),
|
.directControlLineState(directLineState),
|
.directControlLineState(directLineState),
|
.rst(rstSyncToUsbClk) );
|
.rst(rstSyncToUsbClk) );
|
|
|
SCTxPortArbiter u_SCTxPortArbiter
|
SCTxPortArbiter u_SCTxPortArbiter
|
(.SCTxPortCntl(SCTxPortCtrl),
|
(.SCTxPortCntl(SCTxPortCtrl),
|
.SCTxPortData(SCTxPortData),
|
.SCTxPortData(SCTxPortData),
|
.SCTxPortRdyIn(SCTxPortRdy),
|
.SCTxPortRdyIn(SCTxPortRdy),
|
.SCTxPortRdyOut(SCTxPortArbRdyOut),
|
.SCTxPortRdyOut(SCTxPortArbRdyOut),
|
.SCTxPortWEnable(SCTxPortEn),
|
.SCTxPortWEnable(SCTxPortEn),
|
.clk(usbClk),
|
.clk(usbClk),
|
.directCntlCntl(directCntlCntl),
|
.directCntlCntl(directCntlCntl),
|
.directCntlData(directCntlData),
|
.directCntlData(directCntlData),
|
.directCntlGnt(directCntlGnt),
|
.directCntlGnt(directCntlGnt),
|
.directCntlReq(directCntlReq),
|
.directCntlReq(directCntlReq),
|
.directCntlWEn(directCntlWEn),
|
.directCntlWEn(directCntlWEn),
|
.rst(rstSyncToUsbClk),
|
.rst(rstSyncToUsbClk),
|
.sendPacketCntl(sendPacketCntl),
|
.sendPacketCntl(sendPacketCntl),
|
.sendPacketData(sendPacketData),
|
.sendPacketData(sendPacketData),
|
.sendPacketGnt(sendPacketGnt),
|
.sendPacketGnt(sendPacketGnt),
|
.sendPacketReq(sendPacketReq),
|
.sendPacketReq(sendPacketReq),
|
.sendPacketWEn(sendPacketWEn) );
|
.sendPacketWEn(sendPacketWEn) );
|
|
|
|
|
slaveGetPacket u_slaveGetPacket
|
slaveGetPacket u_slaveGetPacket
|
(.ACKRxed(ACKRxed),
|
(.ACKRxed(ACKRxed),
|
.CRCError(CRCError),
|
.CRCError(CRCError),
|
.RXDataIn(RxData),
|
.RXDataIn(RxData),
|
.RXDataValid(RxDataValid),
|
.RXDataValid(RxDataValid),
|
.RXFifoData(RxFifoData),
|
.RXFifoData(RxFifoData),
|
.RXFifoFull(RxFifoFull),
|
.RXFifoFull(RxFifoFull),
|
.RXFifoWEn(RxFifoWE),
|
.RXFifoWEn(RxFifoWE),
|
.RXPacketRdy(getPacketRdy),
|
.RXPacketRdy(getPacketRdy),
|
.RXStreamStatusIn(RxByteStatus),
|
.RXStreamStatusIn(RxByteStatus),
|
.RxPID(RxPID),
|
.RxPID(RxPID),
|
.SIERxTimeOut(SIERxTimeOut),
|
.SIERxTimeOut(SIERxTimeOut),
|
.SIERxTimeOutEn(SIERxTimeOutEn),
|
.SIERxTimeOutEn(SIERxTimeOutEn),
|
.clk(usbClk),
|
.clk(usbClk),
|
.RXOverflow(RXOverflow),
|
.RXOverflow(RXOverflow),
|
.RXTimeOut(RXTimeOut),
|
.RXTimeOut(RXTimeOut),
|
.bitStuffError(bitStuffError),
|
.bitStuffError(bitStuffError),
|
.dataSequence(dataSequence),
|
.dataSequence(dataSequence),
|
.getPacketEn(getPacketREn),
|
.getPacketEn(getPacketREn),
|
.rst(rstSyncToUsbClk),
|
.rst(rstSyncToUsbClk),
|
.endPointReady(endPointReadyFromSlaveCtrlrToGetPkt)
|
.endPointReady(endPointReadyFromSlaveCtrlrToGetPkt)
|
);
|
);
|
|
|
slaveRxStatusMonitor u_slaveRxStatusMonitor
|
slaveRxStatusMonitor u_slaveRxStatusMonitor
|
(.connectStateIn(connectStateIn),
|
(.connectStateIn(connectStateIn),
|
.connectStateOut(connectStateOut),
|
.connectStateOut(connectStateOut),
|
.resumeDetectedIn(resumeDetectedIn),
|
.resumeDetectedIn(resumeDetectedIn),
|
.resetEventOut(resetEventFromRxStatusMon),
|
.resetEventOut(resetEventFromRxStatusMon),
|
.resumeIntOut(resumeIntFromRxStatusMon),
|
.resumeIntOut(resumeIntFromRxStatusMon),
|
.clk(usbClk),
|
.clk(usbClk),
|
.rst(rstSyncToUsbClk) );
|
.rst(rstSyncToUsbClk) );
|
|
|
fifoMux u_fifoMux (
|
fifoMux u_fifoMux (
|
.currEndP(currEndP),
|
.currEndP(currEndP),
|
//TxFifo
|
//TxFifo
|
.TxFifoREn(TxFifoRE),
|
.TxFifoREn(TxFifoRE),
|
.TxFifoEP0REn(TxFifoEP0REn),
|
.TxFifoEP0REn(TxFifoEP0REn),
|
.TxFifoEP1REn(TxFifoEP1REn),
|
.TxFifoEP1REn(TxFifoEP1REn),
|
.TxFifoEP2REn(TxFifoEP2REn),
|
.TxFifoEP2REn(TxFifoEP2REn),
|
.TxFifoEP3REn(TxFifoEP3REn),
|
.TxFifoEP3REn(TxFifoEP3REn),
|
.TxFifoData(TxFifoData),
|
.TxFifoData(TxFifoData),
|
.TxFifoEP0Data(TxFifoEP0Data),
|
.TxFifoEP0Data(TxFifoEP0Data),
|
.TxFifoEP1Data(TxFifoEP1Data),
|
.TxFifoEP1Data(TxFifoEP1Data),
|
.TxFifoEP2Data(TxFifoEP2Data),
|
.TxFifoEP2Data(TxFifoEP2Data),
|
.TxFifoEP3Data(TxFifoEP3Data),
|
.TxFifoEP3Data(TxFifoEP3Data),
|
.TxFifoEmpty(TxFifoEmpty),
|
.TxFifoEmpty(TxFifoEmpty),
|
.TxFifoEP0Empty(TxFifoEP0Empty),
|
.TxFifoEP0Empty(TxFifoEP0Empty),
|
.TxFifoEP1Empty(TxFifoEP1Empty),
|
.TxFifoEP1Empty(TxFifoEP1Empty),
|
.TxFifoEP2Empty(TxFifoEP2Empty),
|
.TxFifoEP2Empty(TxFifoEP2Empty),
|
.TxFifoEP3Empty(TxFifoEP3Empty),
|
.TxFifoEP3Empty(TxFifoEP3Empty),
|
//RxFifo
|
//RxFifo
|
.RxFifoWEn(RxFifoWE),
|
.RxFifoWEn(RxFifoWE),
|
.RxFifoEP0WEn(RxFifoEP0WEn),
|
.RxFifoEP0WEn(RxFifoEP0WEn),
|
.RxFifoEP1WEn(RxFifoEP1WEn),
|
.RxFifoEP1WEn(RxFifoEP1WEn),
|
.RxFifoEP2WEn(RxFifoEP2WEn),
|
.RxFifoEP2WEn(RxFifoEP2WEn),
|
.RxFifoEP3WEn(RxFifoEP3WEn),
|
.RxFifoEP3WEn(RxFifoEP3WEn),
|
.RxFifoFull(RxFifoFull),
|
.RxFifoFull(RxFifoFull),
|
.RxFifoEP0Full(RxFifoEP0Full),
|
.RxFifoEP0Full(RxFifoEP0Full),
|
.RxFifoEP1Full(RxFifoEP1Full),
|
.RxFifoEP1Full(RxFifoEP1Full),
|
.RxFifoEP2Full(RxFifoEP2Full),
|
.RxFifoEP2Full(RxFifoEP2Full),
|
.RxFifoEP3Full(RxFifoEP3Full)
|
.RxFifoEP3Full(RxFifoEP3Full)
|
);
|
);
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
