|
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
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//// EP0.v ////
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//// EP0.v ////
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//// ////
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//// ////
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//// This file is part of the usbHostSlave opencores effort.
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//// This file is part of the usbHostSlave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// ////
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//// Module Description: ////
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//// Module Description: ////
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//// Implements EP0 control endpoint
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//// Implements EP0 control endpoint
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//// Responds to 8-byte SETUP packets
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//// Responds to 8-byte SETUP packets
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//// of type GET_STATUS, GET_DESCRIPTOR and
|
//// of type GET_STATUS, GET_DESCRIPTOR and
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//// SET_ADDRESS
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//// SET_ADDRESS
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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////
|
////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
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//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
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//// details. ////
|
//// ////
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//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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`include "timescale.v"
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`include "timescale.v"
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`include "usbHostSlaveReg_define.v"
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`include "usbHostSlaveReg_define.v"
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`include "usbDevice_define.v"
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`include "usbDevice_define.v"
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module EP0 (clk, initComplete, memAddr, memData, memRdEn, rst, wb_ack, wb_addr, wb_data_i, wb_data_o, wb_stb, wb_we, wbBusGnt, wbBusReq);
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module EP0 (clk, initComplete, memAddr, memData, memRdEn, rst, wb_ack, wb_addr, wb_data_i, wb_data_o, wb_stb, wb_we, wbBusGnt, wbBusReq);
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input clk;
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input clk;
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input [7:0]memData;
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input [7:0]memData;
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input rst;
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input rst;
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input wb_ack;
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input wb_ack;
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input [7:0]wb_data_i;
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input [7:0]wb_data_i;
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input wbBusGnt;
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input wbBusGnt;
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output initComplete;
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output initComplete;
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output [7:0]memAddr;
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output [7:0]memAddr;
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output memRdEn;
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output memRdEn;
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output [7:0]wb_addr;
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output [7:0]wb_addr;
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output [7:0]wb_data_o;
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output [7:0]wb_data_o;
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output wb_stb;
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output wb_stb;
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output wb_we;
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output wb_we;
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output wbBusReq;
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output wbBusReq;
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|
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wire clk;
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wire clk;
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reg initComplete, next_initComplete;
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reg initComplete, next_initComplete;
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reg [7:0]memAddr, next_memAddr;
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reg [7:0]memAddr, next_memAddr;
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wire [7:0]memData;
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wire [7:0]memData;
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reg memRdEn, next_memRdEn;
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reg memRdEn, next_memRdEn;
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wire rst;
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wire rst;
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wire wb_ack;
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wire wb_ack;
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reg [7:0]wb_addr, next_wb_addr;
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reg [7:0]wb_addr, next_wb_addr;
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wire [7:0]wb_data_i;
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wire [7:0]wb_data_i;
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reg [7:0]wb_data_o, next_wb_data_o;
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reg [7:0]wb_data_o, next_wb_data_o;
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reg wb_stb, next_wb_stb;
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reg wb_stb, next_wb_stb;
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reg wb_we, next_wb_we;
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reg wb_we, next_wb_we;
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wire wbBusGnt;
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wire wbBusGnt;
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reg wbBusReq, next_wbBusReq;
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reg wbBusReq, next_wbBusReq;
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|
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// diagram signals declarations
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// diagram signals declarations
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reg bm_req_dir, next_bm_req_dir;
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reg bm_req_dir, next_bm_req_dir;
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reg [4:0]bm_req_recp, next_bm_req_recp;
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reg [4:0]bm_req_recp, next_bm_req_recp;
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reg [1:0]bm_req_type, next_bm_req_type;
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reg [1:0]bm_req_type, next_bm_req_type;
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reg [7:0]bRequest, next_bRequest;
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reg [7:0]bRequest, next_bRequest;
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reg [7:0]cnt, next_cnt;
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reg [7:0]cnt, next_cnt;
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reg dataSeq, next_dataSeq;
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reg dataSeq, next_dataSeq;
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reg [7:0]epStatus, next_epStatus;
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reg [7:0]epStatus, next_epStatus;
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reg [7:0]epTransType, next_epTransType;
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reg [7:0]epTransType, next_epTransType;
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reg localRst, next_localRst;
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reg localRst, next_localRst;
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reg [15:0]rxDataSize, next_rxDataSize;
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reg [15:0]rxDataSize, next_rxDataSize;
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reg transDone, next_transDone;
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reg transDone, next_transDone;
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reg [7:0]txDataIndex, next_txDataIndex;
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reg [7:0]txDataIndex, next_txDataIndex;
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reg [7:0]txDataSize, next_txDataSize;
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reg [7:0]txDataSize, next_txDataSize;
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reg [7:0]txPacketRemSize, next_txPacketRemSize;
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reg [7:0]txPacketRemSize, next_txPacketRemSize;
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reg updateUSBAddress, next_updateUSBAddress;
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reg updateUSBAddress, next_updateUSBAddress;
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reg [7:0]USBAddress, next_USBAddress;
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reg [7:0]USBAddress, next_USBAddress;
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reg [15:0]wIndex, next_wIndex;
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reg [15:0]wIndex, next_wIndex;
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reg [15:0]wLength, next_wLength;
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reg [15:0]wLength, next_wLength;
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reg [15:0]wValue, next_wValue;
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reg [15:0]wValue, next_wValue;
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|
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// BINARY ENCODED state machine: EP0St
|
// BINARY ENCODED state machine: EP0St
|
// State codes definitions:
|
// State codes definitions:
|
`define INIT_RST 6'b000000
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`define INIT_RST 6'b000000
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`define INIT_WT_GNT 6'b000001
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`define INIT_WT_GNT 6'b000001
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`define INIT_WT_RST 6'b000010
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`define INIT_WT_RST 6'b000010
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`define INIT_WT_VBUS 6'b000011
|
`define INIT_WT_VBUS 6'b000011
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`define INIT_FIN 6'b000100
|
`define INIT_FIN 6'b000100
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`define DO_TRANS_WT_GNT 6'b000101
|
`define DO_TRANS_WT_GNT 6'b000101
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`define DO_TRANS_TX_EMPTY 6'b000110
|
`define DO_TRANS_TX_EMPTY 6'b000110
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`define DO_TRANS_WR_TX_FIFO 6'b000111
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`define DO_TRANS_WR_TX_FIFO 6'b000111
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`define DO_TRANS_RD_MEM 6'b001000
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`define DO_TRANS_RD_MEM 6'b001000
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`define DO_TRANS_CHK_TX_DONE 6'b001001
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`define DO_TRANS_CHK_TX_DONE 6'b001001
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`define DO_TRANS_TRANS_GO 6'b001010
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`define DO_TRANS_TRANS_GO 6'b001010
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`define DO_TRANS_WT_TRANS_DONE_WT_GNT 6'b001011
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`define DO_TRANS_WT_TRANS_DONE_WT_GNT 6'b001011
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`define DO_TRANS_WT_TRANS_DONE_GET_RDY_STS 6'b001100
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`define DO_TRANS_WT_TRANS_DONE_GET_RDY_STS 6'b001100
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`define DO_TRANS_WT_TRANS_DONE_WT_UNGNT 6'b001101
|
`define DO_TRANS_WT_TRANS_DONE_WT_UNGNT 6'b001101
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`define DO_TRANS_WT_TRANS_DONE_CHK_DONE 6'b001110
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`define DO_TRANS_WT_TRANS_DONE_CHK_DONE 6'b001110
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`define CHK_TRANS_RD_STAT 6'b001111
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`define CHK_TRANS_RD_STAT 6'b001111
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`define CHK_TRANS_WT_GNT 6'b010000
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`define CHK_TRANS_WT_GNT 6'b010000
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`define CHK_TRANS_RD_RX_SIZE1 6'b010001
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`define CHK_TRANS_RD_RX_SIZE1 6'b010001
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`define CHK_TRANS_RD_RX_SIZE2 6'b010010
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`define CHK_TRANS_RD_RX_SIZE2 6'b010010
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`define CHK_TRANS_RD_TRANS_TYPE 6'b010011
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`define CHK_TRANS_RD_TRANS_TYPE 6'b010011
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`define CHK_TRANS_WT_UNGNT 6'b010100
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`define CHK_TRANS_WT_UNGNT 6'b010100
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`define SETUP_CHK_ERR 6'b010101
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`define SETUP_CHK_ERR 6'b010101
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`define SETUP_GET_DATA_DAT1 6'b010110
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`define SETUP_GET_DATA_DAT1 6'b010110
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`define SETUP_GET_DATA_WT_GNT 6'b010111
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`define SETUP_GET_DATA_WT_GNT 6'b010111
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`define SETUP_GET_DATA_DAT2 6'b011000
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`define SETUP_GET_DATA_DAT2 6'b011000
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`define SETUP_GET_DATA_DAT3 6'b011001
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`define SETUP_GET_DATA_DAT3 6'b011001
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`define SETUP_GET_DATA_DAT4 6'b011010
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`define SETUP_GET_DATA_DAT4 6'b011010
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`define SETUP_GET_DATA_DAT6 6'b011011
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`define SETUP_GET_DATA_DAT6 6'b011011
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`define SETUP_GET_DATA_DAT5 6'b011100
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`define SETUP_GET_DATA_DAT5 6'b011100
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`define SETUP_GET_DATA_DAT8 6'b011101
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`define SETUP_GET_DATA_DAT8 6'b011101
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`define SETUP_GET_DATA_DAT7 6'b011110
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`define SETUP_GET_DATA_DAT7 6'b011110
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`define SETUP_GET_DATA_WT_UNGNT 6'b011111
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`define SETUP_GET_DATA_WT_UNGNT 6'b011111
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`define SETUP_GET_STAT 6'b100000
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`define SETUP_GET_STAT 6'b100000
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`define SETUP_SET_ADDR 6'b100001
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`define SETUP_SET_ADDR 6'b100001
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`define SETUP_GET_DESC_S1 6'b100010
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`define SETUP_GET_DESC_S1 6'b100010
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`define SETUP_CHK_MAX_LEN 6'b100011
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`define SETUP_CHK_MAX_LEN 6'b100011
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`define OUT_CHK_SEQ 6'b100100
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`define OUT_CHK_SEQ 6'b100100
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`define IN_CHK_ACK 6'b100101
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`define IN_CHK_ACK 6'b100101
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`define IN_SET_PTR 6'b100110
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`define IN_SET_PTR 6'b100110
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`define IN_SET_ADDR 6'b100111
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`define IN_SET_ADDR 6'b100111
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`define IN_WT_GNT 6'b101000
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`define IN_WT_GNT 6'b101000
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`define IN_WT_UNGNT 6'b101001
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`define IN_WT_UNGNT 6'b101001
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`define DO_TRANS_RX_EMPTY 6'b101010
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`define DO_TRANS_RX_EMPTY 6'b101010
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`define DO_TRANS_WT_TRANS_DONE_DEL 6'b101011
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`define DO_TRANS_WT_TRANS_DONE_DEL 6'b101011
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`define START 6'b101100
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`define START 6'b101100
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`define INIT_CONN 6'b101101
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`define INIT_CONN 6'b101101
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`define INIT_WT_CONN 6'b101110
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`define INIT_WT_CONN 6'b101110
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`define DO_TRANS_DEL 6'b101111
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`define DO_TRANS_DEL 6'b101111
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`define SETUP_PTR_SET 6'b110000
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`define SETUP_PTR_SET 6'b110000
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|
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reg [5:0]CurrState_EP0St, NextState_EP0St;
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reg [5:0]CurrState_EP0St, NextState_EP0St;
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|
|
// Diagram actions (continuous assignments allowed only: assign ...)
|
// Diagram actions (continuous assignments allowed only: assign ...)
|
// diagram ACTION
|
// diagram ACTION
|
|
|
|
|
// Machine: EP0St
|
// Machine: EP0St
|
|
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// NextState logic (combinatorial)
|
// NextState logic (combinatorial)
|
always @ (wb_ack or wbBusGnt or cnt or wb_data_i or memData or txDataIndex or txDataSize or transDone or epStatus or epTransType or rxDataSize or bRequest or wValue or wLength or dataSeq or updateUSBAddress or txPacketRemSize or USBAddress or wb_addr or wb_data_o or wb_stb or wb_we or wbBusReq or initComplete or memAddr or memRdEn or bm_req_dir or bm_req_type or bm_req_recp or wIndex or CurrState_EP0St)
|
always @ (wb_ack or wbBusGnt or cnt or wb_data_i or memData or txDataIndex or txDataSize or transDone or epStatus or epTransType or rxDataSize or bRequest or wValue or wLength or dataSeq or updateUSBAddress or txPacketRemSize or USBAddress or wb_addr or wb_data_o or wb_stb or wb_we or wbBusReq or initComplete or memAddr or memRdEn or bm_req_dir or bm_req_type or bm_req_recp or wIndex or CurrState_EP0St)
|
begin
|
begin
|
NextState_EP0St <= CurrState_EP0St;
|
NextState_EP0St <= CurrState_EP0St;
|
// Set default values for outputs and signals
|
// Set default values for outputs and signals
|
next_wb_addr <= wb_addr;
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next_wb_addr <= wb_addr;
|
next_wb_data_o <= wb_data_o;
|
next_wb_data_o <= wb_data_o;
|
next_wb_stb <= wb_stb;
|
next_wb_stb <= wb_stb;
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next_wb_we <= wb_we;
|
next_wb_we <= wb_we;
|
next_cnt <= cnt;
|
next_cnt <= cnt;
|
next_wbBusReq <= wbBusReq;
|
next_wbBusReq <= wbBusReq;
|
next_initComplete <= initComplete;
|
next_initComplete <= initComplete;
|
next_memAddr <= memAddr;
|
next_memAddr <= memAddr;
|
next_memRdEn <= memRdEn;
|
next_memRdEn <= memRdEn;
|
next_txDataSize <= txDataSize;
|
next_txDataSize <= txDataSize;
|
next_txDataIndex <= txDataIndex;
|
next_txDataIndex <= txDataIndex;
|
next_transDone <= transDone;
|
next_transDone <= transDone;
|
next_epStatus <= epStatus;
|
next_epStatus <= epStatus;
|
next_rxDataSize <= rxDataSize;
|
next_rxDataSize <= rxDataSize;
|
next_epTransType <= epTransType;
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next_epTransType <= epTransType;
|
next_bm_req_dir <= bm_req_dir;
|
next_bm_req_dir <= bm_req_dir;
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next_bm_req_type <= bm_req_type;
|
next_bm_req_type <= bm_req_type;
|
next_bm_req_recp <= bm_req_recp;
|
next_bm_req_recp <= bm_req_recp;
|
next_bRequest <= bRequest;
|
next_bRequest <= bRequest;
|
next_wValue <= wValue;
|
next_wValue <= wValue;
|
next_wIndex <= wIndex;
|
next_wIndex <= wIndex;
|
next_wLength <= wLength;
|
next_wLength <= wLength;
|
next_txPacketRemSize <= txPacketRemSize;
|
next_txPacketRemSize <= txPacketRemSize;
|
next_USBAddress <= USBAddress;
|
next_USBAddress <= USBAddress;
|
next_updateUSBAddress <= updateUSBAddress;
|
next_updateUSBAddress <= updateUSBAddress;
|
next_dataSeq <= dataSeq;
|
next_dataSeq <= dataSeq;
|
case (CurrState_EP0St) // synopsys parallel_case full_case
|
case (CurrState_EP0St) // synopsys parallel_case full_case
|
`START:
|
`START:
|
begin
|
begin
|
next_initComplete <= 1'b0;
|
next_initComplete <= 1'b0;
|
next_wbBusReq <= 1'b0;
|
next_wbBusReq <= 1'b0;
|
next_wb_addr <= 8'h00;
|
next_wb_addr <= 8'h00;
|
next_wb_data_o <= 8'h00;
|
next_wb_data_o <= 8'h00;
|
next_wb_stb <= 1'b0;
|
next_wb_stb <= 1'b0;
|
next_wb_we <= 1'b0;
|
next_wb_we <= 1'b0;
|
next_txPacketRemSize <= 8'h00;
|
next_txPacketRemSize <= 8'h00;
|
next_txDataSize <= 8'h00;
|
next_txDataSize <= 8'h00;
|
next_txDataIndex <= 8'h00;
|
next_txDataIndex <= 8'h00;
|
next_epTransType <= 8'h00;
|
next_epTransType <= 8'h00;
|
next_epStatus <= 8'h00;
|
next_epStatus <= 8'h00;
|
next_rxDataSize <= 16'h0000;
|
next_rxDataSize <= 16'h0000;
|
next_cnt <= 8'h00;
|
next_cnt <= 8'h00;
|
next_memRdEn <= 1'b0;
|
next_memRdEn <= 1'b0;
|
next_memAddr <= 8'h00;
|
next_memAddr <= 8'h00;
|
next_updateUSBAddress <= 1'b0;
|
next_updateUSBAddress <= 1'b0;
|
next_transDone <= 1'b0;
|
next_transDone <= 1'b0;
|
next_bm_req_type <= 2'b00;
|
next_bm_req_type <= 2'b00;
|
next_bm_req_dir <= 1'b0;
|
next_bm_req_dir <= 1'b0;
|
next_bm_req_recp <= 5'b00000;
|
next_bm_req_recp <= 5'b00000;
|
next_bRequest <= 8'h00;
|
next_bRequest <= 8'h00;
|
next_wLength <= 16'h0000;
|
next_wLength <= 16'h0000;
|
next_wIndex <= 16'h0000;
|
next_wIndex <= 16'h0000;
|
next_wValue <= 16'h0000;
|
next_wValue <= 16'h0000;
|
next_dataSeq <= 1'b0;
|
next_dataSeq <= 1'b0;
|
next_USBAddress <= 8'h00;
|
next_USBAddress <= 8'h00;
|
NextState_EP0St <= `INIT_WT_GNT;
|
NextState_EP0St <= `INIT_WT_GNT;
|
end
|
end
|
`CHK_TRANS_RD_STAT:
|
`CHK_TRANS_RD_STAT:
|
begin
|
begin
|
next_wb_addr <= `RA_EP0_STATUS_REG;
|
next_wb_addr <= `RA_EP0_STATUS_REG;
|
next_wb_stb <= 1'b1;
|
next_wb_stb <= 1'b1;
|
next_wb_we <= 1'b0;
|
next_wb_we <= 1'b0;
|
if (wb_ack == 1'b1)
|
if (wb_ack == 1'b1)
|
begin
|
begin
|
NextState_EP0St <= `CHK_TRANS_RD_RX_SIZE1;
|
NextState_EP0St <= `CHK_TRANS_RD_RX_SIZE1;
|
next_wb_stb <= 1'b0;
|
next_wb_stb <= 1'b0;
|
next_epStatus <= wb_data_i;
|
next_epStatus <= wb_data_i;
|
end
|
end
|
end
|
end
|
`CHK_TRANS_WT_GNT:
|
`CHK_TRANS_WT_GNT:
|
begin
|
begin
|
if (wbBusGnt == 1'b1)
|
if (wbBusGnt == 1'b1)
|
begin
|
begin
|
NextState_EP0St <= `CHK_TRANS_RD_STAT;
|
NextState_EP0St <= `CHK_TRANS_RD_STAT;
|
end
|
end
|
end
|
end
|
`CHK_TRANS_RD_RX_SIZE1:
|
`CHK_TRANS_RD_RX_SIZE1:
|
begin
|
begin
|
next_wb_addr <= `RA_EP0_RX_FIFO_DATA_COUNT_MSB;
|
next_wb_addr <= `RA_EP0_RX_FIFO_DATA_COUNT_MSB;
|
next_wb_stb <= 1'b1;
|
next_wb_stb <= 1'b1;
|
next_wb_we <= 1'b0;
|
next_wb_we <= 1'b0;
|
if (wb_ack == 1'b1)
|
if (wb_ack == 1'b1)
|
begin
|
begin
|
NextState_EP0St <= `CHK_TRANS_RD_RX_SIZE2;
|
NextState_EP0St <= `CHK_TRANS_RD_RX_SIZE2;
|
next_wb_stb <= 1'b0;
|
next_wb_stb <= 1'b0;
|
next_rxDataSize[15:8] <= wb_data_i;
|
next_rxDataSize[15:8] <= wb_data_i;
|
end
|
end
|
end
|
end
|
`CHK_TRANS_RD_RX_SIZE2:
|
`CHK_TRANS_RD_RX_SIZE2:
|
begin
|
begin
|
next_wb_addr <= `RA_EP0_RX_FIFO_DATA_COUNT_LSB;
|
next_wb_addr <= `RA_EP0_RX_FIFO_DATA_COUNT_LSB;
|
next_wb_stb <= 1'b1;
|
next_wb_stb <= 1'b1;
|
next_wb_we <= 1'b0;
|
next_wb_we <= 1'b0;
|
if (wb_ack == 1'b1)
|
if (wb_ack == 1'b1)
|
begin
|
begin
|
NextState_EP0St <= `CHK_TRANS_RD_TRANS_TYPE;
|
NextState_EP0St <= `CHK_TRANS_RD_TRANS_TYPE;
|
next_wb_stb <= 1'b0;
|
next_wb_stb <= 1'b0;
|
next_rxDataSize[7:0] <= wb_data_i;
|
next_rxDataSize[7:0] <= wb_data_i;
|
end
|
end
|
end
|
end
|
`CHK_TRANS_RD_TRANS_TYPE:
|
`CHK_TRANS_RD_TRANS_TYPE:
|
begin
|
begin
|
next_wb_addr <= `RA_EP0_TRANSTYPE_STATUS_REG;
|
next_wb_addr <= `RA_EP0_TRANSTYPE_STATUS_REG;
|
next_wb_stb <= 1'b1;
|
next_wb_stb <= 1'b1;
|
next_wb_we <= 1'b0;
|
next_wb_we <= 1'b0;
|
if (wb_ack == 1'b1)
|
if (wb_ack == 1'b1)
|
begin
|
begin
|
NextState_EP0St <= `CHK_TRANS_WT_UNGNT;
|
NextState_EP0St <= `CHK_TRANS_WT_UNGNT;
|
next_wb_stb <= 1'b0;
|
next_wb_stb <= 1'b0;
|
next_epTransType <= wb_data_i;
|
next_epTransType <= wb_data_i;
|
end
|
end
|
end
|
end
|
`CHK_TRANS_WT_UNGNT:
|
`CHK_TRANS_WT_UNGNT:
|
begin
|
begin
|
next_wbBusReq <= 1'b0;
|
next_wbBusReq <= 1'b0;
|
if ((wbBusGnt == 1'b0) && ((epStatus & 8'h0f) != 8'h00))
|
if ((wbBusGnt == 1'b0) && ((epStatus & 8'h0f) != 8'h00))
|
begin
|
begin
|
NextState_EP0St <= `DO_TRANS_WT_GNT;
|
NextState_EP0St <= `DO_TRANS_WT_GNT;
|
end
|
end
|
else if ((wbBusGnt == 1'b0) && (epTransType == `SC_SETUP_TRANS))
|
else if ((wbBusGnt == 1'b0) && (epTransType == `SC_SETUP_TRANS))
|
begin
|
begin
|
NextState_EP0St <= `SETUP_CHK_ERR;
|
NextState_EP0St <= `SETUP_CHK_ERR;
|
end
|
end
|
else if ((wbBusGnt == 1'b0) && (epTransType == `SC_IN_TRANS))
|
else if ((wbBusGnt == 1'b0) && (epTransType == `SC_IN_TRANS))
|
begin
|
begin
|
NextState_EP0St <= `IN_CHK_ACK;
|
NextState_EP0St <= `IN_CHK_ACK;
|
end
|
end
|
else if ((wbBusGnt == 1'b0) && (epTransType == `SC_OUTDATA_TRANS))
|
else if ((wbBusGnt == 1'b0) && (epTransType == `SC_OUTDATA_TRANS))
|
begin
|
begin
|
NextState_EP0St <= `OUT_CHK_SEQ;
|
NextState_EP0St <= `OUT_CHK_SEQ;
|
end
|
end
|
else if (wbBusGnt == 1'b0)
|
else if (wbBusGnt == 1'b0)
|
begin
|
begin
|
NextState_EP0St <= `DO_TRANS_WT_GNT;
|
NextState_EP0St <= `DO_TRANS_WT_GNT;
|
end
|
end
|
end
|
end
|
`DO_TRANS_WT_GNT:
|
`DO_TRANS_WT_GNT:
|
begin
|
begin
|
next_wbBusReq <= 1'b1;
|
next_wbBusReq <= 1'b1;
|
if (wbBusGnt == 1'b1)
|
if (wbBusGnt == 1'b1)
|
begin
|
begin
|
NextState_EP0St <= `DO_TRANS_TX_EMPTY;
|
NextState_EP0St <= `DO_TRANS_TX_EMPTY;
|
end
|
end
|
end
|
end
|
`DO_TRANS_TX_EMPTY:
|
`DO_TRANS_TX_EMPTY:
|
begin
|
begin
|
next_wb_addr <= `RA_EP0_TX_FIFO_CONTROL_REG;
|
next_wb_addr <= `RA_EP0_TX_FIFO_CONTROL_REG;
|
next_wb_data_o <= 8'h01;
|
next_wb_data_o <= 8'h01;
|
//force tx fifo empty
|
//force tx fifo empty
|
next_wb_stb <= 1'b1;
|
next_wb_stb <= 1'b1;
|
next_wb_we <= 1'b1;
|
next_wb_we <= 1'b1;
|
if (wb_ack == 1'b1)
|
if (wb_ack == 1'b1)
|
begin
|
begin
|
NextState_EP0St <= `DO_TRANS_RX_EMPTY;
|
NextState_EP0St <= `DO_TRANS_RX_EMPTY;
|
next_wb_stb <= 1'b0;
|
next_wb_stb <= 1'b0;
|
end
|
end
|
end
|
end
|
`DO_TRANS_WR_TX_FIFO:
|
`DO_TRANS_WR_TX_FIFO:
|
begin
|
begin
|
next_wb_data_o <= memData;
|
next_wb_data_o <= memData;
|
next_wb_addr <= `RA_EP0_TX_FIFO_DATA_REG;
|
next_wb_addr <= `RA_EP0_TX_FIFO_DATA_REG;
|
next_wb_stb <= 1'b1;
|
next_wb_stb <= 1'b1;
|
next_wb_we <= 1'b1;
|
next_wb_we <= 1'b1;
|
if (wb_ack == 1'b1)
|
if (wb_ack == 1'b1)
|
begin
|
begin
|
NextState_EP0St <= `DO_TRANS_CHK_TX_DONE;
|
NextState_EP0St <= `DO_TRANS_CHK_TX_DONE;
|
next_wb_stb <= 1'b0;
|
next_wb_stb <= 1'b0;
|
end
|
end
|
end
|
end
|
`DO_TRANS_RD_MEM:
|
`DO_TRANS_RD_MEM:
|
begin
|
begin
|
next_memAddr <= txDataIndex;
|
next_memAddr <= txDataIndex;
|
next_memRdEn <= 1'b1;
|
next_memRdEn <= 1'b1;
|
next_txDataSize <= txDataSize - 1'b1;
|
next_txDataSize <= txDataSize - 1'b1;
|
next_txDataIndex <= txDataIndex + 1'b1;
|
next_txDataIndex <= txDataIndex + 1'b1;
|
NextState_EP0St <= `DO_TRANS_DEL;
|
NextState_EP0St <= `DO_TRANS_DEL;
|
end
|
end
|
`DO_TRANS_CHK_TX_DONE:
|
`DO_TRANS_CHK_TX_DONE:
|
begin
|
begin
|
if (txDataSize == 8'h00)
|
if (txDataSize == 8'h00)
|
begin
|
begin
|
NextState_EP0St <= `DO_TRANS_TRANS_GO;
|
NextState_EP0St <= `DO_TRANS_TRANS_GO;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
NextState_EP0St <= `DO_TRANS_RD_MEM;
|
NextState_EP0St <= `DO_TRANS_RD_MEM;
|
end
|
end
|
end
|
end
|
`DO_TRANS_TRANS_GO:
|
`DO_TRANS_TRANS_GO:
|
begin
|
begin
|
next_wb_addr <= `RA_EP0_CONTROL_REG;
|
next_wb_addr <= `RA_EP0_CONTROL_REG;
|
if (dataSeq == 1'b1)
|
if (dataSeq == 1'b1)
|
next_wb_data_o <= 8'h07;
|
next_wb_data_o <= 8'h07;
|
else
|
else
|
next_wb_data_o <= 8'h03;
|
next_wb_data_o <= 8'h03;
|
next_wb_stb <= 1'b1;
|
next_wb_stb <= 1'b1;
|
next_wb_we <= 1'b1;
|
next_wb_we <= 1'b1;
|
if (wb_ack == 1'b1)
|
if (wb_ack == 1'b1)
|
begin
|
begin
|
NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_WT_GNT;
|
NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_WT_GNT;
|
next_wb_stb <= 1'b0;
|
next_wb_stb <= 1'b0;
|
next_transDone <= 1'b0;
|
next_transDone <= 1'b0;
|
end
|
end
|
end
|
end
|
`DO_TRANS_RX_EMPTY:
|
`DO_TRANS_RX_EMPTY:
|
begin
|
begin
|
next_wb_addr <= `RA_EP0_RX_FIFO_CONTROL_REG;
|
next_wb_addr <= `RA_EP0_RX_FIFO_CONTROL_REG;
|
next_wb_data_o <= 8'h01;
|
next_wb_data_o <= 8'h01;
|
//force rx fifo empty
|
//force rx fifo empty
|
next_wb_stb <= 1'b1;
|
next_wb_stb <= 1'b1;
|
next_wb_we <= 1'b1;
|
next_wb_we <= 1'b1;
|
if ((wb_ack == 1'b1) && (txDataSize != 8'h00))
|
if ((wb_ack == 1'b1) && (txDataSize != 8'h00))
|
begin
|
begin
|
NextState_EP0St <= `DO_TRANS_RD_MEM;
|
NextState_EP0St <= `DO_TRANS_RD_MEM;
|
next_wb_stb <= 1'b0;
|
next_wb_stb <= 1'b0;
|
end
|
end
|
else if (wb_ack == 1'b1)
|
else if (wb_ack == 1'b1)
|
begin
|
begin
|
NextState_EP0St <= `DO_TRANS_TRANS_GO;
|
NextState_EP0St <= `DO_TRANS_TRANS_GO;
|
next_wb_stb <= 1'b0;
|
next_wb_stb <= 1'b0;
|
end
|
end
|
end
|
end
|
`DO_TRANS_DEL:
|
`DO_TRANS_DEL:
|
begin
|
begin
|
next_memRdEn <= 1'b0;
|
next_memRdEn <= 1'b0;
|
NextState_EP0St <= `DO_TRANS_WR_TX_FIFO;
|
NextState_EP0St <= `DO_TRANS_WR_TX_FIFO;
|
end
|
end
|
`DO_TRANS_WT_TRANS_DONE_WT_GNT:
|
`DO_TRANS_WT_TRANS_DONE_WT_GNT:
|
begin
|
begin
|
next_wbBusReq <= 1'b1;
|
next_wbBusReq <= 1'b1;
|
if (wbBusGnt == 1'b1)
|
if (wbBusGnt == 1'b1)
|
begin
|
begin
|
NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_GET_RDY_STS;
|
NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_GET_RDY_STS;
|
end
|
end
|
end
|
end
|
`DO_TRANS_WT_TRANS_DONE_GET_RDY_STS:
|
`DO_TRANS_WT_TRANS_DONE_GET_RDY_STS:
|
begin
|
begin
|
next_wb_addr <= `RA_EP0_CONTROL_REG;
|
next_wb_addr <= `RA_EP0_CONTROL_REG;
|
next_wb_stb <= 1'b1;
|
next_wb_stb <= 1'b1;
|
next_wb_we <= 1'b0;
|
next_wb_we <= 1'b0;
|
if (wb_ack == 1'b1)
|
if (wb_ack == 1'b1)
|
begin
|
begin
|
NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_WT_UNGNT;
|
NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_WT_UNGNT;
|
next_wb_stb <= 1'b0;
|
next_wb_stb <= 1'b0;
|
next_transDone <= ~wb_data_i[`ENDPOINT_READY_BIT];
|
next_transDone <= ~wb_data_i[`ENDPOINT_READY_BIT];
|
end
|
end
|
end
|
end
|
`DO_TRANS_WT_TRANS_DONE_WT_UNGNT:
|
`DO_TRANS_WT_TRANS_DONE_WT_UNGNT:
|
begin
|
begin
|
next_wbBusReq <= 1'b0;
|
next_wbBusReq <= 1'b0;
|
if (wbBusGnt == 1'b0)
|
if (wbBusGnt == 1'b0)
|
begin
|
begin
|
NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_CHK_DONE;
|
NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_CHK_DONE;
|
end
|
end
|
end
|
end
|
`DO_TRANS_WT_TRANS_DONE_CHK_DONE:
|
`DO_TRANS_WT_TRANS_DONE_CHK_DONE:
|
begin
|
begin
|
if (transDone == 1'b1)
|
if (transDone == 1'b1)
|
begin
|
begin
|
NextState_EP0St <= `CHK_TRANS_WT_GNT;
|
NextState_EP0St <= `CHK_TRANS_WT_GNT;
|
next_wbBusReq <= 1'b1;
|
next_wbBusReq <= 1'b1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_DEL;
|
NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_DEL;
|
next_cnt <= 8'h00;
|
next_cnt <= 8'h00;
|
end
|
end
|
end
|
end
|
`DO_TRANS_WT_TRANS_DONE_DEL:
|
`DO_TRANS_WT_TRANS_DONE_DEL:
|
begin
|
begin
|
next_cnt <= cnt + 1'b1;
|
next_cnt <= cnt + 1'b1;
|
if (cnt == `ONE_USEC_DEL)
|
if (cnt == `ONE_USEC_DEL)
|
begin
|
begin
|
NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_WT_GNT;
|
NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_WT_GNT;
|
end
|
end
|
end
|
end
|
`SETUP_CHK_ERR:
|
`SETUP_CHK_ERR:
|
begin
|
begin
|
if (rxDataSize != 16'h0008)
|
if (rxDataSize != 16'h0008)
|
begin
|
begin
|
NextState_EP0St <= `DO_TRANS_WT_GNT;
|
NextState_EP0St <= `DO_TRANS_WT_GNT;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
NextState_EP0St <= `SETUP_GET_DATA_WT_GNT;
|
NextState_EP0St <= `SETUP_GET_DATA_WT_GNT;
|
next_wbBusReq <= 1'b1;
|
next_wbBusReq <= 1'b1;
|
next_txDataSize <= 8'h00;
|
next_txDataSize <= 8'h00;
|
next_txPacketRemSize <= 8'h00;
|
next_txPacketRemSize <= 8'h00;
|
//default tx packet size
|
//default tx packet size
|
next_dataSeq <= 1'b1;
|
next_dataSeq <= 1'b1;
|
next_wb_addr <= `RA_EP0_RX_FIFO_DATA_REG;
|
next_wb_addr <= `RA_EP0_RX_FIFO_DATA_REG;
|
next_wb_we <= 1'b0;
|
next_wb_we <= 1'b0;
|
end
|
end
|
end
|
end
|
`SETUP_GET_STAT:
|
`SETUP_GET_STAT:
|
begin
|
begin
|
if (bm_req_type == 2'b00) begin
|
if (bm_req_type == 2'b00) begin
|
next_txPacketRemSize <= 8'h02;
|
next_txPacketRemSize <= 8'h02;
|
if (bm_req_recp == 5'b00000)
|
if (bm_req_recp == 5'b00000)
|
next_txDataIndex <= `ONE_ZERO_STAT_INDEX;
|
next_txDataIndex <= `ONE_ZERO_STAT_INDEX;
|
else
|
else
|
next_txDataIndex <= `ZERO_ZERO_STAT_INDEX;
|
next_txDataIndex <= `ZERO_ZERO_STAT_INDEX;
|
end
|
end
|
else if (bm_req_type == 2'b10) begin
|
else if (bm_req_type == 2'b10) begin
|
next_txDataIndex <= `VENDOR_DATA_STAT_INDEX;
|
next_txDataIndex <= `VENDOR_DATA_STAT_INDEX;
|
next_txPacketRemSize <= 8'h02;
|
next_txPacketRemSize <= 8'h02;
|
end
|
end
|
NextState_EP0St <= `SETUP_CHK_MAX_LEN;
|
NextState_EP0St <= `SETUP_CHK_MAX_LEN;
|
end
|
end
|
`SETUP_SET_ADDR:
|
`SETUP_SET_ADDR:
|
begin
|
begin
|
if ( (wValue[15:7] == {9{1'b0}}) && (wIndex == 16'h0000) && (wLength == 16'h0000) ) begin
|
if ( (wValue[15:7] == {9{1'b0}}) && (wIndex == 16'h0000) && (wLength == 16'h0000) ) begin
|
next_USBAddress <= wValue[7:0];
|
next_USBAddress <= wValue[7:0];
|
next_updateUSBAddress <= 1'b1;
|
next_updateUSBAddress <= 1'b1;
|
end
|
end
|
NextState_EP0St <= `SETUP_CHK_MAX_LEN;
|
NextState_EP0St <= `SETUP_CHK_MAX_LEN;
|
end
|
end
|
`SETUP_CHK_MAX_LEN:
|
`SETUP_CHK_MAX_LEN:
|
begin
|
begin
|
if (txPacketRemSize > wLength)
|
if (txPacketRemSize > wLength)
|
next_txPacketRemSize <= wLength;
|
next_txPacketRemSize <= wLength;
|
NextState_EP0St <= `SETUP_PTR_SET;
|
NextState_EP0St <= `SETUP_PTR_SET;
|
end
|
end
|
`SETUP_PTR_SET:
|
`SETUP_PTR_SET:
|
begin
|
begin
|
if (txPacketRemSize > `MAX_RESP_SIZE) begin
|
if (txPacketRemSize > `MAX_RESP_SIZE) begin
|
next_txDataSize <= `MAX_RESP_SIZE;
|
next_txDataSize <= `MAX_RESP_SIZE;
|
next_txPacketRemSize <= txPacketRemSize - `MAX_RESP_SIZE;
|
next_txPacketRemSize <= txPacketRemSize - `MAX_RESP_SIZE;
|
end
|
end
|
else begin
|
else begin
|
next_txDataSize <= txPacketRemSize;
|
next_txDataSize <= txPacketRemSize;
|
next_txPacketRemSize <= 8'h00;
|
next_txPacketRemSize <= 8'h00;
|
end
|
end
|
NextState_EP0St <= `DO_TRANS_WT_GNT;
|
NextState_EP0St <= `DO_TRANS_WT_GNT;
|
end
|
end
|
`SETUP_GET_DATA_DAT1:
|
`SETUP_GET_DATA_DAT1:
|
begin
|
begin
|
next_wb_stb <= 1'b1;
|
next_wb_stb <= 1'b1;
|
if (wb_ack == 1'b1)
|
if (wb_ack == 1'b1)
|
begin
|
begin
|
NextState_EP0St <= `SETUP_GET_DATA_DAT2;
|
NextState_EP0St <= `SETUP_GET_DATA_DAT2;
|
next_wb_stb <= 1'b0;
|
next_wb_stb <= 1'b0;
|
next_bm_req_dir <= wb_data_i[7];
|
next_bm_req_dir <= wb_data_i[7];
|
next_bm_req_type <= wb_data_i[6:5];
|
next_bm_req_type <= wb_data_i[6:5];
|
next_bm_req_recp <= wb_data_i[4:0];
|
next_bm_req_recp <= wb_data_i[4:0];
|
end
|
end
|
end
|
end
|
`SETUP_GET_DATA_WT_GNT:
|
`SETUP_GET_DATA_WT_GNT:
|
begin
|
begin
|
if (wbBusGnt == 1'b1)
|
if (wbBusGnt == 1'b1)
|
begin
|
begin
|
NextState_EP0St <= `SETUP_GET_DATA_DAT1;
|
NextState_EP0St <= `SETUP_GET_DATA_DAT1;
|
end
|
end
|
end
|
end
|
`SETUP_GET_DATA_DAT2:
|
`SETUP_GET_DATA_DAT2:
|
begin
|
begin
|
next_wb_stb <= 1'b1;
|
next_wb_stb <= 1'b1;
|
if (wb_ack == 1'b1)
|
if (wb_ack == 1'b1)
|
begin
|
begin
|
NextState_EP0St <= `SETUP_GET_DATA_DAT3;
|
NextState_EP0St <= `SETUP_GET_DATA_DAT3;
|
next_wb_stb <= 1'b0;
|
next_wb_stb <= 1'b0;
|
next_bRequest <= wb_data_i;
|
next_bRequest <= wb_data_i;
|
end
|
end
|
end
|
end
|
`SETUP_GET_DATA_DAT3:
|
`SETUP_GET_DATA_DAT3:
|
begin
|
begin
|
next_wb_stb <= 1'b1;
|
next_wb_stb <= 1'b1;
|
if (wb_ack == 1'b1)
|
if (wb_ack == 1'b1)
|
begin
|
begin
|
NextState_EP0St <= `SETUP_GET_DATA_DAT4;
|
NextState_EP0St <= `SETUP_GET_DATA_DAT4;
|
next_wb_stb <= 1'b0;
|
next_wb_stb <= 1'b0;
|
next_wValue[7:0] <= wb_data_i;
|
next_wValue[7:0] <= wb_data_i;
|
end
|
end
|
end
|
end
|
`SETUP_GET_DATA_DAT4:
|
`SETUP_GET_DATA_DAT4:
|
begin
|
begin
|
next_wb_stb <= 1'b1;
|
next_wb_stb <= 1'b1;
|
if (wb_ack == 1'b1)
|
if (wb_ack == 1'b1)
|
begin
|
begin
|
NextState_EP0St <= `SETUP_GET_DATA_DAT5;
|
NextState_EP0St <= `SETUP_GET_DATA_DAT5;
|
next_wb_stb <= 1'b0;
|
next_wb_stb <= 1'b0;
|
next_wValue[15:8] <= wb_data_i;
|
next_wValue[15:8] <= wb_data_i;
|
end
|
end
|
end
|
end
|
`SETUP_GET_DATA_DAT6:
|
`SETUP_GET_DATA_DAT6:
|
begin
|
begin
|
next_wb_stb <= 1'b1;
|
next_wb_stb <= 1'b1;
|
if (wb_ack == 1'b1)
|
if (wb_ack == 1'b1)
|
begin
|
begin
|
NextState_EP0St <= `SETUP_GET_DATA_DAT7;
|
NextState_EP0St <= `SETUP_GET_DATA_DAT7;
|
next_wb_stb <= 1'b0;
|
next_wb_stb <= 1'b0;
|
next_wIndex[15:8] <= wb_data_i;
|
next_wIndex[15:8] <= wb_data_i;
|
end
|
end
|
end
|
end
|
`SETUP_GET_DATA_DAT5:
|
`SETUP_GET_DATA_DAT5:
|
begin
|
begin
|
next_wb_stb <= 1'b1;
|
next_wb_stb <= 1'b1;
|
if (wb_ack == 1'b1)
|
if (wb_ack == 1'b1)
|
begin
|
begin
|
NextState_EP0St <= `SETUP_GET_DATA_DAT6;
|
NextState_EP0St <= `SETUP_GET_DATA_DAT6;
|
next_wb_stb <= 1'b0;
|
next_wb_stb <= 1'b0;
|
next_wIndex[7:0] <= wb_data_i;
|
next_wIndex[7:0] <= wb_data_i;
|
end
|
end
|
end
|
end
|
`SETUP_GET_DATA_DAT8:
|
`SETUP_GET_DATA_DAT8:
|
begin
|
begin
|
next_wb_stb <= 1'b1;
|
next_wb_stb <= 1'b1;
|
if (wb_ack == 1'b1)
|
if (wb_ack == 1'b1)
|
begin
|
begin
|
NextState_EP0St <= `SETUP_GET_DATA_WT_UNGNT;
|
NextState_EP0St <= `SETUP_GET_DATA_WT_UNGNT;
|
next_wb_stb <= 1'b0;
|
next_wb_stb <= 1'b0;
|
next_wLength[15:8] <= wb_data_i;
|
next_wLength[15:8] <= wb_data_i;
|
next_wbBusReq <= 1'b0;
|
next_wbBusReq <= 1'b0;
|
end
|
end
|
end
|
end
|
`SETUP_GET_DATA_DAT7:
|
`SETUP_GET_DATA_DAT7:
|
begin
|
begin
|
next_wb_stb <= 1'b1;
|
next_wb_stb <= 1'b1;
|
if (wb_ack == 1'b1)
|
if (wb_ack == 1'b1)
|
begin
|
begin
|
NextState_EP0St <= `SETUP_GET_DATA_DAT8;
|
NextState_EP0St <= `SETUP_GET_DATA_DAT8;
|
next_wb_stb <= 1'b0;
|
next_wb_stb <= 1'b0;
|
next_wLength[7:0] <= wb_data_i;
|
next_wLength[7:0] <= wb_data_i;
|
end
|
end
|
end
|
end
|
`SETUP_GET_DATA_WT_UNGNT:
|
`SETUP_GET_DATA_WT_UNGNT:
|
begin
|
begin
|
if ((wbBusGnt == 1'b0) && (bRequest == `GET_STATUS))
|
if ((wbBusGnt == 1'b0) && (bRequest == `GET_STATUS))
|
begin
|
begin
|
NextState_EP0St <= `SETUP_GET_STAT;
|
NextState_EP0St <= `SETUP_GET_STAT;
|
end
|
end
|
else if ((wbBusGnt == 1'b0) && (bRequest == `GET_DESCRIPTOR))
|
else if ((wbBusGnt == 1'b0) && (bRequest == `GET_DESCRIPTOR))
|
begin
|
begin
|
NextState_EP0St <= `SETUP_GET_DESC_S1;
|
NextState_EP0St <= `SETUP_GET_DESC_S1;
|
end
|
end
|
else if ((wbBusGnt == 1'b0) && (bRequest == `SET_ADDRESS))
|
else if ((wbBusGnt == 1'b0) && (bRequest == `SET_ADDRESS))
|
begin
|
begin
|
NextState_EP0St <= `SETUP_SET_ADDR;
|
NextState_EP0St <= `SETUP_SET_ADDR;
|
end
|
end
|
else if (wbBusGnt == 1'b0)
|
else if (wbBusGnt == 1'b0)
|
begin
|
begin
|
NextState_EP0St <= `DO_TRANS_WT_GNT;
|
NextState_EP0St <= `DO_TRANS_WT_GNT;
|
end
|
end
|
end
|
end
|
`SETUP_GET_DESC_S1:
|
`SETUP_GET_DESC_S1:
|
begin
|
begin
|
case (wValue[15:8])
|
case (wValue[15:8])
|
`DEV_DESC: begin
|
`DEV_DESC: begin
|
next_txPacketRemSize <= `DEV_DESC_SIZE;
|
next_txPacketRemSize <= `DEV_DESC_SIZE;
|
next_txDataIndex <= `DEV_DESC_INDEX;
|
next_txDataIndex <= `DEV_DESC_INDEX;
|
end
|
end
|
`CFG_DESC: begin
|
`CFG_DESC: begin
|
next_txPacketRemSize <= `CFG_DESC_SIZE;
|
next_txPacketRemSize <= `CFG_DESC_SIZE;
|
next_txDataIndex <= `CFG_DESC_INDEX;
|
next_txDataIndex <= `CFG_DESC_INDEX;
|
end
|
end
|
`REP_DESC: begin
|
`REP_DESC: begin
|
next_txPacketRemSize <= `REP_DESC_SIZE;
|
next_txPacketRemSize <= `REP_DESC_SIZE;
|
next_txDataIndex <= `REP_DESC_INDEX;
|
next_txDataIndex <= `REP_DESC_INDEX;
|
end
|
end
|
`STRING_DESC: begin
|
`STRING_DESC: begin
|
case (wValue[3:0])
|
case (wValue[3:0])
|
4'h0: begin
|
4'h0: begin
|
next_txPacketRemSize <= `LANGID_DESC_SIZE;
|
next_txPacketRemSize <= `LANGID_DESC_SIZE;
|
next_txDataIndex <= `LANGID_DESC_INDEX;
|
next_txDataIndex <= `LANGID_DESC_INDEX;
|
end
|
end
|
4'h1: begin
|
4'h1: begin
|
next_txPacketRemSize <= `STRING1_DESC_SIZE;
|
next_txPacketRemSize <= `STRING1_DESC_SIZE;
|
next_txDataIndex <= `STRING1_DESC_INDEX;
|
next_txDataIndex <= `STRING1_DESC_INDEX;
|
end
|
end
|
4'h2: begin
|
4'h2: begin
|
next_txPacketRemSize <= `STRING2_DESC_SIZE;
|
next_txPacketRemSize <= `STRING2_DESC_SIZE;
|
next_txDataIndex <= `STRING2_DESC_INDEX;
|
next_txDataIndex <= `STRING2_DESC_INDEX;
|
end
|
end
|
4'h3: begin
|
4'h3: begin
|
next_txPacketRemSize <= `STRING3_DESC_SIZE;
|
next_txPacketRemSize <= `STRING3_DESC_SIZE;
|
next_txDataIndex <= `STRING3_DESC_INDEX;
|
next_txDataIndex <= `STRING3_DESC_INDEX;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
endcase
|
endcase
|
NextState_EP0St <= `SETUP_CHK_MAX_LEN;
|
NextState_EP0St <= `SETUP_CHK_MAX_LEN;
|
end
|
end
|
`IN_CHK_ACK:
|
`IN_CHK_ACK:
|
begin
|
begin
|
if (epStatus[`SC_ACK_RXED_BIT] != 1'b1)
|
if (epStatus[`SC_ACK_RXED_BIT] != 1'b1)
|
begin
|
begin
|
NextState_EP0St <= `DO_TRANS_WT_GNT;
|
NextState_EP0St <= `DO_TRANS_WT_GNT;
|
end
|
end
|
else if (updateUSBAddress == 1'b1)
|
else if (updateUSBAddress == 1'b1)
|
begin
|
begin
|
NextState_EP0St <= `IN_WT_GNT;
|
NextState_EP0St <= `IN_WT_GNT;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
NextState_EP0St <= `IN_SET_PTR;
|
NextState_EP0St <= `IN_SET_PTR;
|
end
|
end
|
end
|
end
|
`IN_SET_PTR:
|
`IN_SET_PTR:
|
begin
|
begin
|
if (txPacketRemSize > `MAX_RESP_SIZE) begin
|
if (txPacketRemSize > `MAX_RESP_SIZE) begin
|
next_txDataSize <= `MAX_RESP_SIZE;
|
next_txDataSize <= `MAX_RESP_SIZE;
|
next_txPacketRemSize <= txPacketRemSize - `MAX_RESP_SIZE;
|
next_txPacketRemSize <= txPacketRemSize - `MAX_RESP_SIZE;
|
end
|
end
|
else begin
|
else begin
|
next_txDataSize <= txPacketRemSize;
|
next_txDataSize <= txPacketRemSize;
|
next_txPacketRemSize <= 8'h00;
|
next_txPacketRemSize <= 8'h00;
|
end
|
end
|
NextState_EP0St <= `DO_TRANS_WT_GNT;
|
NextState_EP0St <= `DO_TRANS_WT_GNT;
|
end
|
end
|
`IN_SET_ADDR:
|
`IN_SET_ADDR:
|
begin
|
begin
|
next_wb_addr <= `RA_SC_ADDRESS;
|
next_wb_addr <= `RA_SC_ADDRESS;
|
next_wb_data_o <= USBAddress;
|
next_wb_data_o <= USBAddress;
|
next_wb_stb <= 1'b1;
|
next_wb_stb <= 1'b1;
|
next_wb_we <= 1'b1;
|
next_wb_we <= 1'b1;
|
if (wb_ack == 1'b1)
|
if (wb_ack == 1'b1)
|
begin
|
begin
|
NextState_EP0St <= `IN_WT_UNGNT;
|
NextState_EP0St <= `IN_WT_UNGNT;
|
next_wb_stb <= 1'b0;
|
next_wb_stb <= 1'b0;
|
next_wbBusReq <= 1'b0;
|
next_wbBusReq <= 1'b0;
|
end
|
end
|
end
|
end
|
`IN_WT_GNT:
|
`IN_WT_GNT:
|
begin
|
begin
|
next_wbBusReq <= 1'b1;
|
next_wbBusReq <= 1'b1;
|
next_updateUSBAddress <= 1'b0;
|
next_updateUSBAddress <= 1'b0;
|
if (wbBusGnt == 1'b1)
|
if (wbBusGnt == 1'b1)
|
begin
|
begin
|
NextState_EP0St <= `IN_SET_ADDR;
|
NextState_EP0St <= `IN_SET_ADDR;
|
end
|
end
|
end
|
end
|
`IN_WT_UNGNT:
|
`IN_WT_UNGNT:
|
begin
|
begin
|
if (wbBusGnt == 1'b0)
|
if (wbBusGnt == 1'b0)
|
begin
|
begin
|
NextState_EP0St <= `IN_SET_PTR;
|
NextState_EP0St <= `IN_SET_PTR;
|
end
|
end
|
end
|
end
|
`OUT_CHK_SEQ:
|
`OUT_CHK_SEQ:
|
begin
|
begin
|
if (epStatus[`SC_DATA_SEQUENCE_BIT] != dataSeq)
|
if (epStatus[`SC_DATA_SEQUENCE_BIT] != dataSeq)
|
begin
|
begin
|
NextState_EP0St <= `DO_TRANS_WT_GNT;
|
NextState_EP0St <= `DO_TRANS_WT_GNT;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
NextState_EP0St <= `DO_TRANS_WT_GNT;
|
NextState_EP0St <= `DO_TRANS_WT_GNT;
|
next_dataSeq <= ~dataSeq;
|
next_dataSeq <= ~dataSeq;
|
end
|
end
|
end
|
end
|
`INIT_RST:
|
`INIT_RST:
|
begin
|
begin
|
next_wb_addr <= `RA_HOST_SLAVE_MODE;
|
next_wb_addr <= `RA_HOST_SLAVE_MODE;
|
next_wb_data_o <= 8'h2;
|
next_wb_data_o <= 8'h2;
|
//reset usbHostSlave
|
//reset usbHostSlave
|
next_wb_stb <= 1'b1;
|
next_wb_stb <= 1'b1;
|
next_wb_we <= 1'b1;
|
next_wb_we <= 1'b1;
|
if (wb_ack == 1'b1)
|
if (wb_ack == 1'b1)
|
begin
|
begin
|
NextState_EP0St <= `INIT_WT_RST;
|
NextState_EP0St <= `INIT_WT_RST;
|
next_wb_stb <= 1'b0;
|
next_wb_stb <= 1'b0;
|
next_cnt <= 8'h00;
|
next_cnt <= 8'h00;
|
end
|
end
|
end
|
end
|
`INIT_WT_GNT:
|
`INIT_WT_GNT:
|
begin
|
begin
|
next_wbBusReq <= 1'b1;
|
next_wbBusReq <= 1'b1;
|
if (wbBusGnt == 1'b1)
|
if (wbBusGnt == 1'b1)
|
begin
|
begin
|
NextState_EP0St <= `INIT_RST;
|
NextState_EP0St <= `INIT_RST;
|
end
|
end
|
end
|
end
|
`INIT_WT_RST:
|
`INIT_WT_RST:
|
begin
|
begin
|
next_cnt <= cnt + 1'b1;
|
next_cnt <= cnt + 1'b1;
|
if (cnt == 8'hff)
|
if (cnt == 8'hff)
|
begin
|
begin
|
NextState_EP0St <= `INIT_WT_VBUS;
|
NextState_EP0St <= `INIT_WT_VBUS;
|
end
|
end
|
end
|
end
|
`INIT_WT_VBUS:
|
`INIT_WT_VBUS:
|
begin
|
begin
|
next_wb_addr <= `RA_SC_LINE_STATUS_REG;
|
next_wb_addr <= `RA_SC_LINE_STATUS_REG;
|
next_wb_stb <= 1'b1;
|
next_wb_stb <= 1'b1;
|
next_wb_we <= 1'b0;
|
next_wb_we <= 1'b0;
|
if ((wb_ack == 1'b1) && (wb_data_i[`VBUS_PRES_BIT] == 1'b1))
|
if ((wb_ack == 1'b1) && (wb_data_i[`VBUS_PRES_BIT] == 1'b1))
|
begin
|
begin
|
NextState_EP0St <= `INIT_CONN;
|
NextState_EP0St <= `INIT_CONN;
|
next_wb_stb <= 1'b0;
|
next_wb_stb <= 1'b0;
|
end
|
end
|
end
|
end
|
`INIT_FIN:
|
`INIT_FIN:
|
begin
|
begin
|
next_wbBusReq <= 1'b0;
|
next_wbBusReq <= 1'b0;
|
next_initComplete <= 1'b1;
|
next_initComplete <= 1'b1;
|
if (wbBusGnt == 1'b0)
|
if (wbBusGnt == 1'b0)
|
begin
|
begin
|
NextState_EP0St <= `DO_TRANS_WT_GNT;
|
NextState_EP0St <= `DO_TRANS_WT_GNT;
|
end
|
end
|
end
|
end
|
`INIT_CONN:
|
`INIT_CONN:
|
begin
|
begin
|
next_wb_addr <= `RA_SC_CONTROL_REG;
|
next_wb_addr <= `RA_SC_CONTROL_REG;
|
next_wb_data_o <= 8'h71;
|
next_wb_data_o <= 8'h71;
|
//connect to host, full speed
|
//connect to host, full speed
|
next_wb_stb <= 1'b1;
|
next_wb_stb <= 1'b1;
|
next_wb_we <= 1'b1;
|
next_wb_we <= 1'b1;
|
if (wb_ack == 1'b1)
|
if (wb_ack == 1'b1)
|
begin
|
begin
|
NextState_EP0St <= `INIT_WT_CONN;
|
NextState_EP0St <= `INIT_WT_CONN;
|
next_wb_stb <= 1'b0;
|
next_wb_stb <= 1'b0;
|
end
|
end
|
end
|
end
|
`INIT_WT_CONN:
|
`INIT_WT_CONN:
|
begin
|
begin
|
next_wb_addr <= `RA_SC_LINE_STATUS_REG;
|
next_wb_addr <= `RA_SC_LINE_STATUS_REG;
|
next_wb_stb <= 1'b1;
|
next_wb_stb <= 1'b1;
|
next_wb_we <= 1'b0;
|
next_wb_we <= 1'b0;
|
if ((wb_ack == 1'b1) && (wb_data_i[1:0] == `FULL_SPEED_CONNECT))
|
if ((wb_ack == 1'b1) && (wb_data_i[1:0] == `FULL_SPEED_CONNECT))
|
begin
|
begin
|
NextState_EP0St <= `INIT_FIN;
|
NextState_EP0St <= `INIT_FIN;
|
next_wb_stb <= 1'b0;
|
next_wb_stb <= 1'b0;
|
end
|
end
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
// Current State Logic (sequential)
|
// Current State Logic (sequential)
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin
|
if (rst == 1'b1)
|
if (rst == 1'b1)
|
CurrState_EP0St <= `START;
|
CurrState_EP0St <= `START;
|
else
|
else
|
CurrState_EP0St <= NextState_EP0St;
|
CurrState_EP0St <= NextState_EP0St;
|
end
|
end
|
|
|
// Registered outputs logic
|
// Registered outputs logic
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin
|
if (rst == 1'b1)
|
if (rst == 1'b1)
|
begin
|
begin
|
wb_addr <= 8'h00;
|
wb_addr <= 8'h00;
|
wb_data_o <= 8'h00;
|
wb_data_o <= 8'h00;
|
wb_stb <= 1'b0;
|
wb_stb <= 1'b0;
|
wb_we <= 1'b0;
|
wb_we <= 1'b0;
|
wbBusReq <= 1'b0;
|
wbBusReq <= 1'b0;
|
initComplete <= 1'b0;
|
initComplete <= 1'b0;
|
memAddr <= 8'h00;
|
memAddr <= 8'h00;
|
memRdEn <= 1'b0;
|
memRdEn <= 1'b0;
|
cnt <= 8'h00;
|
cnt <= 8'h00;
|
txDataSize <= 8'h00;
|
txDataSize <= 8'h00;
|
txDataIndex <= 8'h00;
|
txDataIndex <= 8'h00;
|
transDone <= 1'b0;
|
transDone <= 1'b0;
|
epStatus <= 8'h00;
|
epStatus <= 8'h00;
|
rxDataSize <= 16'h0000;
|
rxDataSize <= 16'h0000;
|
epTransType <= 8'h00;
|
epTransType <= 8'h00;
|
bm_req_dir <= 1'b0;
|
bm_req_dir <= 1'b0;
|
bm_req_type <= 2'b00;
|
bm_req_type <= 2'b00;
|
bm_req_recp <= 5'b00000;
|
bm_req_recp <= 5'b00000;
|
bRequest <= 8'h00;
|
bRequest <= 8'h00;
|
wValue <= 16'h0000;
|
wValue <= 16'h0000;
|
wIndex <= 16'h0000;
|
wIndex <= 16'h0000;
|
wLength <= 16'h0000;
|
wLength <= 16'h0000;
|
txPacketRemSize <= 8'h00;
|
txPacketRemSize <= 8'h00;
|
USBAddress <= 8'h00;
|
USBAddress <= 8'h00;
|
updateUSBAddress <= 1'b0;
|
updateUSBAddress <= 1'b0;
|
dataSeq <= 1'b0;
|
dataSeq <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
wb_addr <= next_wb_addr;
|
wb_addr <= next_wb_addr;
|
wb_data_o <= next_wb_data_o;
|
wb_data_o <= next_wb_data_o;
|
wb_stb <= next_wb_stb;
|
wb_stb <= next_wb_stb;
|
wb_we <= next_wb_we;
|
wb_we <= next_wb_we;
|
wbBusReq <= next_wbBusReq;
|
wbBusReq <= next_wbBusReq;
|
initComplete <= next_initComplete;
|
initComplete <= next_initComplete;
|
memAddr <= next_memAddr;
|
memAddr <= next_memAddr;
|
memRdEn <= next_memRdEn;
|
memRdEn <= next_memRdEn;
|
cnt <= next_cnt;
|
cnt <= next_cnt;
|
txDataSize <= next_txDataSize;
|
txDataSize <= next_txDataSize;
|
txDataIndex <= next_txDataIndex;
|
txDataIndex <= next_txDataIndex;
|
transDone <= next_transDone;
|
transDone <= next_transDone;
|
epStatus <= next_epStatus;
|
epStatus <= next_epStatus;
|
rxDataSize <= next_rxDataSize;
|
rxDataSize <= next_rxDataSize;
|
epTransType <= next_epTransType;
|
epTransType <= next_epTransType;
|
bm_req_dir <= next_bm_req_dir;
|
bm_req_dir <= next_bm_req_dir;
|
bm_req_type <= next_bm_req_type;
|
bm_req_type <= next_bm_req_type;
|
bm_req_recp <= next_bm_req_recp;
|
bm_req_recp <= next_bm_req_recp;
|
bRequest <= next_bRequest;
|
bRequest <= next_bRequest;
|
wValue <= next_wValue;
|
wValue <= next_wValue;
|
wIndex <= next_wIndex;
|
wIndex <= next_wIndex;
|
wLength <= next_wLength;
|
wLength <= next_wLength;
|
txPacketRemSize <= next_txPacketRemSize;
|
txPacketRemSize <= next_txPacketRemSize;
|
USBAddress <= next_USBAddress;
|
USBAddress <= next_USBAddress;
|
updateUSBAddress <= next_updateUSBAddress;
|
updateUSBAddress <= next_updateUSBAddress;
|
dataSeq <= next_dataSeq;
|
dataSeq <= next_dataSeq;
|
end
|
end
|
end
|
end
|
|
|
|
|