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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// checkLineState.v ////
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//// checkLineState.v ////
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//// ////
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//// ////
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//// This file is part of the usbHostSlave opencores effort.
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//// This file is part of the usbHostSlave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// ////
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//// Module Description: ////
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//// Module Description: ////
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//// Checks USB line state. When reset state detected
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//// Checks USB line state. When reset state detected
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//// asserts usbRstDet for one clock tick
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//// asserts usbRstDet for one clock tick
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//// usbRstDet is used to reset most of the logic.
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//// usbRstDet is used to reset most of the logic.
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////
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////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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////
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////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
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//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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`include "timescale.v"
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`include "timescale.v"
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`include "usbSlaveControl_h.v"
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`include "usbSlaveControl_h.v"
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`include "usbHostSlaveReg_define.v"
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`include "usbHostSlaveReg_define.v"
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbDevice_define.v"
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`include "usbDevice_define.v"
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module checkLineState (clk, initComplete, rst, usbRstDet, wb_ack, wb_addr, wb_data_i, wb_stb, wb_we, wbBusGnt, wbBusReq);
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module checkLineState (clk, initComplete, rst, usbRstDet, wb_ack, wb_addr, wb_data_i, wb_stb, wb_we, wbBusGnt, wbBusReq);
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input clk;
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input clk;
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input initComplete;
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input initComplete;
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input rst;
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input rst;
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input wb_ack;
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input wb_ack;
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input [7:0]wb_data_i;
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input [7:0]wb_data_i;
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input wbBusGnt;
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input wbBusGnt;
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output usbRstDet;
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output usbRstDet;
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output [7:0]wb_addr;
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output [7:0]wb_addr;
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output wb_stb;
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output wb_stb;
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output wb_we;
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output wb_we;
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output wbBusReq;
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output wbBusReq;
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wire clk;
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wire clk;
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wire initComplete;
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wire initComplete;
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wire rst;
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wire rst;
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reg usbRstDet, next_usbRstDet;
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reg usbRstDet, next_usbRstDet;
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wire wb_ack;
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wire wb_ack;
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reg [7:0]wb_addr, next_wb_addr;
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reg [7:0]wb_addr, next_wb_addr;
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wire [7:0]wb_data_i;
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wire [7:0]wb_data_i;
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reg wb_stb, next_wb_stb;
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reg wb_stb, next_wb_stb;
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reg wb_we, next_wb_we;
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reg wb_we, next_wb_we;
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wire wbBusGnt;
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wire wbBusGnt;
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reg wbBusReq, next_wbBusReq;
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reg wbBusReq, next_wbBusReq;
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// diagram signals declarations
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// diagram signals declarations
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reg [15:0]cnt, next_cnt;
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reg [15:0]cnt, next_cnt;
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reg [1:0]resetState, next_resetState;
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reg [1:0]resetState, next_resetState;
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// BINARY ENCODED state machine: chkLSt
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// BINARY ENCODED state machine: chkLSt
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// State codes definitions:
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// State codes definitions:
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`define START 3'b000
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`define START 3'b000
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`define GET_STAT 3'b001
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`define GET_STAT 3'b001
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`define WT_GNT 3'b010
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`define WT_GNT 3'b010
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`define SET_RST_DET 3'b011
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`define SET_RST_DET 3'b011
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`define DEL_ONE_MSEC 3'b100
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`define DEL_ONE_MSEC 3'b100
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reg [2:0]CurrState_chkLSt, NextState_chkLSt;
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reg [2:0]CurrState_chkLSt, NextState_chkLSt;
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// Diagram actions (continuous assignments allowed only: assign ...)
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// Diagram actions (continuous assignments allowed only: assign ...)
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// diagram ACTION
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// diagram ACTION
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// Machine: chkLSt
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// Machine: chkLSt
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// NextState logic (combinatorial)
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// NextState logic (combinatorial)
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always @ (initComplete or wb_ack or resetState or wbBusGnt or cnt or usbRstDet or wbBusReq or wb_addr or wb_stb or wb_we or CurrState_chkLSt)
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always @ (initComplete or wb_ack or resetState or wbBusGnt or cnt or usbRstDet or wbBusReq or wb_addr or wb_stb or wb_we or CurrState_chkLSt)
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begin
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begin
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NextState_chkLSt <= CurrState_chkLSt;
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NextState_chkLSt <= CurrState_chkLSt;
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// Set default values for outputs and signals
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// Set default values for outputs and signals
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next_usbRstDet <= usbRstDet;
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next_usbRstDet <= usbRstDet;
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next_wbBusReq <= wbBusReq;
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next_wbBusReq <= wbBusReq;
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next_wb_addr <= wb_addr;
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next_wb_addr <= wb_addr;
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next_wb_stb <= wb_stb;
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next_wb_stb <= wb_stb;
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next_wb_we <= wb_we;
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next_wb_we <= wb_we;
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next_cnt <= cnt;
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next_cnt <= cnt;
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next_resetState <= resetState;
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next_resetState <= resetState;
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case (CurrState_chkLSt) // synopsys parallel_case full_case
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case (CurrState_chkLSt) // synopsys parallel_case full_case
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`START:
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`START:
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begin
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begin
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next_usbRstDet <= 1'b0;
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next_usbRstDet <= 1'b0;
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next_wbBusReq <= 1'b0;
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next_wbBusReq <= 1'b0;
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next_wb_addr <= 8'h00;
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next_wb_addr <= 8'h00;
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next_wb_stb <= 1'b0;
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next_wb_stb <= 1'b0;
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next_wb_we <= 1'b0;
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next_wb_we <= 1'b0;
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next_cnt <= 16'h0000;
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next_cnt <= 16'h0000;
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next_resetState <= 2'b00;
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next_resetState <= 2'b00;
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if (initComplete == 1'b1)
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if (initComplete == 1'b1)
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begin
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begin
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NextState_chkLSt <= `WT_GNT;
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NextState_chkLSt <= `WT_GNT;
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end
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end
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end
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end
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`GET_STAT:
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`GET_STAT:
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begin
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begin
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next_wb_addr <= `RA_SC_LINE_STATUS_REG;
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next_wb_addr <= `RA_SC_LINE_STATUS_REG;
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next_wb_stb <= 1'b1;
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next_wb_stb <= 1'b1;
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next_wb_we <= 1'b1;
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next_wb_we <= 1'b1;
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if (wb_ack == 1'b1)
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if (wb_ack == 1'b1)
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begin
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begin
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NextState_chkLSt <= `SET_RST_DET;
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NextState_chkLSt <= `SET_RST_DET;
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next_wb_stb <= 1'b0;
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next_wb_stb <= 1'b0;
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if ( (wb_data_i[1:0] == `DISCONNECT) || (wb_data_i[`VBUS_PRES_BIT] == 1'b0) )
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if ( (wb_data_i[1:0] == `DISCONNECT) || (wb_data_i[`VBUS_PRES_BIT] == 1'b0) )
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next_resetState <= {resetState[0], 1'b1};
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next_resetState <= {resetState[0], 1'b1};
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else
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else
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next_resetState <= 2'b00;
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next_resetState <= 2'b00;
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next_wbBusReq <= 1'b0;
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next_wbBusReq <= 1'b0;
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end
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end
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end
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end
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`WT_GNT:
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`WT_GNT:
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begin
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begin
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next_wbBusReq <= 1'b1;
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next_wbBusReq <= 1'b1;
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if (wbBusGnt == 1'b1)
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if (wbBusGnt == 1'b1)
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begin
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begin
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NextState_chkLSt <= `GET_STAT;
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NextState_chkLSt <= `GET_STAT;
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end
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end
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end
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end
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`SET_RST_DET:
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`SET_RST_DET:
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begin
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begin
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NextState_chkLSt <= `DEL_ONE_MSEC;
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NextState_chkLSt <= `DEL_ONE_MSEC;
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if (resetState == 2'b11) // if reset condition aserted for 2mS
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if (resetState == 2'b11) // if reset condition aserted for 2mS
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next_usbRstDet <= 1'b1;
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next_usbRstDet <= 1'b1;
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next_cnt <= 16'h0000;
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next_cnt <= 16'h0000;
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end
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end
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`DEL_ONE_MSEC:
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`DEL_ONE_MSEC:
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begin
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begin
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next_cnt <= cnt + 1'b1;
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next_cnt <= cnt + 1'b1;
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next_usbRstDet <= 1'b0;
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next_usbRstDet <= 1'b0;
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if (cnt == `ONE_MSEC_DEL)
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if (cnt == `ONE_MSEC_DEL)
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begin
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begin
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NextState_chkLSt <= `WT_GNT;
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NextState_chkLSt <= `WT_GNT;
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end
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end
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end
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end
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endcase
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endcase
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end
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end
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// Current State Logic (sequential)
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// Current State Logic (sequential)
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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if (rst == 1'b1)
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if (rst == 1'b1)
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CurrState_chkLSt <= `START;
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CurrState_chkLSt <= `START;
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else
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else
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CurrState_chkLSt <= NextState_chkLSt;
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CurrState_chkLSt <= NextState_chkLSt;
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end
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end
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// Registered outputs logic
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// Registered outputs logic
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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if (rst == 1'b1)
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if (rst == 1'b1)
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begin
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begin
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usbRstDet <= 1'b0;
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usbRstDet <= 1'b0;
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wbBusReq <= 1'b0;
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wbBusReq <= 1'b0;
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wb_addr <= 8'h00;
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wb_addr <= 8'h00;
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wb_stb <= 1'b0;
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wb_stb <= 1'b0;
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wb_we <= 1'b0;
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wb_we <= 1'b0;
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cnt <= 16'h0000;
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cnt <= 16'h0000;
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resetState <= 2'b00;
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resetState <= 2'b00;
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end
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end
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else
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else
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begin
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begin
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usbRstDet <= next_usbRstDet;
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usbRstDet <= next_usbRstDet;
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wbBusReq <= next_wbBusReq;
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wbBusReq <= next_wbBusReq;
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wb_addr <= next_wb_addr;
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wb_addr <= next_wb_addr;
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wb_stb <= next_wb_stb;
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wb_stb <= next_wb_stb;
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wb_we <= next_wb_we;
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wb_we <= next_wb_we;
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cnt <= next_cnt;
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cnt <= next_cnt;
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resetState <= next_resetState;
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resetState <= next_resetState;
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end
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end
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end
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end
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