//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// usbDeviceAlteraTop.v ////
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//// usbDeviceAlteraTop.v ////
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//// ////
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//// ////
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//// This file is part of the spiMaster opencores effort.
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//// This file is part of the spiMaster opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// ////
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//// Module Description: ////
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//// Module Description: ////
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//// Top level module for Altera FPGA and NXP ISP1105 USB PHY.
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//// Top level module for Altera FPGA and NXP ISP1105 USB PHY.
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//// Specifically it targets the Base2Designs Altera Development board.
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//// Specifically it targets the Base2Designs Altera Development board.
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//// Instantiates a PLL so that the lock signal can be used
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//// Instantiates a PLL so that the lock signal can be used
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//// to reset the logic, and ties unused control signals
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//// to reset the logic, and ties unused control signals
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//// to the off or disabled state
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//// to the off or disabled state
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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////
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////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
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//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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//`define PHY_ISP1105
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//`define PHY_ISP1105
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module usbDeviceAlteraTop (
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module usbDeviceAlteraTop (
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|
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//
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//
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// Global signals
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// Global signals
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//
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//
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clk,
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clk,
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|
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//
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//
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// SDRAM
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// SDRAM
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//
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//
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mc_addr,
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mc_addr,
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mc_ba,
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mc_ba,
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mc_dqm,
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mc_dqm,
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mc_we_,
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mc_we_,
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mc_cas_,
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mc_cas_,
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mc_ras_,
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mc_ras_,
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mc_cke_,
|
mc_cke_,
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sdram_cs,
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sdram_cs,
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sdram_clk,
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sdram_clk,
|
|
|
//
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//
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// SPI bus
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// SPI bus
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//
|
//
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spiClk,
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spiClk,
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spiMasterDataOut,
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spiMasterDataOut,
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spiCS_n,
|
spiCS_n,
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|
|
|
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//
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//
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// USB host
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// USB host
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//
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//
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//usbHostOE_n,
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//usbHostOE_n,
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|
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//
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//
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// USB slave
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// USB slave
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//
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//
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//usbSlaveVP,
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//usbSlaveVP,
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//usbSlaveVM,
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//usbSlaveVM,
|
|
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//usbSlaveOE_n,
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//usbSlaveOE_n,
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//usbDPlusPullup,
|
//usbDPlusPullup,
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//vBusDetect,
|
//vBusDetect,
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|
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//
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//
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// Santa Cruz header
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// Santa Cruz header
|
//
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//
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SC_P_CLK,
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SC_P_CLK,
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SC_RST_N,
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SC_RST_N,
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SC_CS_N,
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SC_CS_N,
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SC_P0,
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SC_P0,
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SC_P1,
|
SC_P1,
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SC_P2,
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SC_P2,
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SC_P3,
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SC_P3,
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SC_P4,
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SC_P4,
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SC_P5,
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SC_P5,
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SC_P6,
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SC_P6,
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SC_P7,
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SC_P7,
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SC_P8,
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SC_P8,
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SC_P9,
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SC_P9,
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SC_P10,
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SC_P10,
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SC_P11,
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SC_P11,
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SC_P12,
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SC_P12,
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SC_P13,
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SC_P13,
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SC_P14,
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SC_P14,
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SC_P15,
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SC_P15,
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SC_P16,
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SC_P16,
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SC_P17,
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SC_P17,
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SC_P18,
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SC_P18,
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SC_P19,
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SC_P19,
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SC_P20,
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SC_P20,
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SC_P21,
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SC_P21,
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SC_P22,
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SC_P22,
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SC_P23,
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SC_P23,
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SC_P24,
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SC_P24,
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SC_P25,
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SC_P25,
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SC_P26,
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SC_P26,
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SC_P27,
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SC_P27,
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SC_P28,
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SC_P28,
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SC_P29,
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SC_P29,
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SC_P30,
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SC_P30,
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SC_P31,
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SC_P31,
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SC_P32,
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SC_P32,
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SC_P33,
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SC_P33,
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SC_P34,
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SC_P34,
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SC_P35,
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SC_P35,
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SC_P36,
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SC_P36,
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SC_P37,
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SC_P37,
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SC_P38,
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SC_P38,
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SC_P39
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SC_P39
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|
|
|
|
|
|
);
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);
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//
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//
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// Global signals
|
// Global signals
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//
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//
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input clk;
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input clk;
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|
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//
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//
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// SDRAM
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// SDRAM
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//
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//
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output [11:0] mc_addr;
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output [11:0] mc_addr;
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output [1:0] mc_ba;
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output [1:0] mc_ba;
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output [3:0] mc_dqm;
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output [3:0] mc_dqm;
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output mc_we_;
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output mc_we_;
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output mc_cas_;
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output mc_cas_;
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output mc_ras_;
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output mc_ras_;
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output mc_cke_;
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output mc_cke_;
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output sdram_cs;
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output sdram_cs;
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output sdram_clk;
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output sdram_clk;
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|
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//
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//
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// SPI bus
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// SPI bus
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//
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//
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output spiClk;
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output spiClk;
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output spiMasterDataOut;
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output spiMasterDataOut;
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output spiCS_n;
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output spiCS_n;
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|
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//
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//
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// USB host
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// USB host
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//
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//
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//output usbHostOE_n;
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//output usbHostOE_n;
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|
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//
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//
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// USB slave
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// USB slave
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//
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//
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//inout usbSlaveVP;
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//inout usbSlaveVP;
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//inout usbSlaveVM;
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//inout usbSlaveVM;
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|
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//output usbSlaveOE_n;
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//output usbSlaveOE_n;
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//output usbDPlusPullup;
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//output usbDPlusPullup;
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//input vBusDetect;
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//input vBusDetect;
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`ifdef PHY_ISP1105
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`ifdef PHY_ISP1105
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output SC_P_CLK;
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output SC_P_CLK;
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output SC_RST_N;
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output SC_RST_N;
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output SC_CS_N;
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output SC_CS_N;
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output SC_P0;
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output SC_P0;
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output SC_P1;
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output SC_P1;
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output SC_P2;
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output SC_P2;
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output SC_P3;
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output SC_P3;
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output SC_P4;
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output SC_P4;
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output SC_P5;
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output SC_P5;
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output SC_P6;
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output SC_P6;
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output SC_P7;
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output SC_P7;
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output SC_P8;
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output SC_P8;
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output SC_P9;
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output SC_P9;
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output SC_P10;
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output SC_P10;
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output SC_P11;
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output SC_P11;
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output SC_P12;
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output SC_P12;
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output SC_P13;
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output SC_P13;
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output SC_P14;
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output SC_P14;
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output SC_P15;
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output SC_P15;
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output SC_P16;
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output SC_P16;
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output SC_P17;
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output SC_P17;
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output SC_P18;
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output SC_P18;
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output SC_P19;
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output SC_P19;
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input SC_P20;
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input SC_P20;
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output SC_P21;
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output SC_P21;
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inout SC_P22;
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inout SC_P22;
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inout SC_P23;
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inout SC_P23;
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output SC_P24;
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output SC_P24;
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output SC_P25;
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output SC_P25;
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output SC_P26;
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output SC_P26;
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output SC_P27;
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output SC_P27;
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output SC_P28;
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output SC_P28;
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output SC_P29;
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output SC_P29;
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output SC_P30;
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output SC_P30;
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output SC_P31;
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output SC_P31;
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output SC_P32;
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output SC_P32;
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output SC_P33;
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output SC_P33;
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output SC_P34;
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output SC_P34;
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output SC_P35;
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output SC_P35;
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output SC_P36;
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output SC_P36;
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output SC_P37;
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output SC_P37;
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output SC_P38;
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output SC_P38;
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output SC_P39;
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output SC_P39;
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`else
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`else
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output SC_P_CLK;
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output SC_P_CLK;
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output SC_RST_N;
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output SC_RST_N;
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output SC_CS_N;
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output SC_CS_N;
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output SC_P0;
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output SC_P0;
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output SC_P1;
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output SC_P1;
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input SC_P2;
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input SC_P2;
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output SC_P3;
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output SC_P3;
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input SC_P4;
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input SC_P4;
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output SC_P5;
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output SC_P5;
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output SC_P6;
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output SC_P6;
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output SC_P7;
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output SC_P7;
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output SC_P8;
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output SC_P8;
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output SC_P9;
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output SC_P9;
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output SC_P10;
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output SC_P10;
|
output SC_P11;
|
output SC_P11;
|
output SC_P12;
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output SC_P12;
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output SC_P13;
|
output SC_P13;
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output SC_P14;
|
output SC_P14;
|
output SC_P15;
|
output SC_P15;
|
output SC_P16;
|
output SC_P16;
|
output SC_P17;
|
output SC_P17;
|
output SC_P18;
|
output SC_P18;
|
output SC_P19;
|
output SC_P19;
|
output SC_P20;
|
output SC_P20;
|
output SC_P21;
|
output SC_P21;
|
input SC_P22;
|
input SC_P22;
|
output SC_P23;
|
output SC_P23;
|
input SC_P24;
|
input SC_P24;
|
output SC_P25;
|
output SC_P25;
|
output SC_P26;
|
output SC_P26;
|
output SC_P27;
|
output SC_P27;
|
output SC_P28;
|
output SC_P28;
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output SC_P29;
|
output SC_P29;
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output SC_P30;
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output SC_P30;
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output SC_P31;
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output SC_P31;
|
output SC_P32;
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output SC_P32;
|
output SC_P33;
|
output SC_P33;
|
output SC_P34;
|
output SC_P34;
|
output SC_P35;
|
output SC_P35;
|
output SC_P36;
|
output SC_P36;
|
output SC_P37;
|
output SC_P37;
|
output SC_P38;
|
output SC_P38;
|
output SC_P39;
|
output SC_P39;
|
`endif
|
`endif
|
|
|
|
|
|
|
//local wires and regs
|
//local wires and regs
|
reg [1:0] rstReg;
|
reg [1:0] rstReg;
|
wire rst;
|
wire rst;
|
wire pll_locked;
|
wire pll_locked;
|
wire usbSlaveVP_in;
|
wire usbSlaveVP_in;
|
wire usbSlaveVM_in;
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wire usbSlaveVM_in;
|
wire usbSlaveVP_out;
|
wire usbSlaveVP_out;
|
wire usbSlaveVM_out;
|
wire usbSlaveVM_out;
|
wire usbSlaveFullSpeed;
|
wire usbSlaveFullSpeed;
|
|
|
assign mc_addr = {12{1'b0}};
|
assign mc_addr = {12{1'b0}};
|
assign mc_ba = 2'b00;
|
assign mc_ba = 2'b00;
|
assign mc_dqm = 4'h0;
|
assign mc_dqm = 4'h0;
|
assign mc_we_ = 1'b1;
|
assign mc_we_ = 1'b1;
|
assign mc_cas_ = 1'b1;
|
assign mc_cas_ = 1'b1;
|
assign mc_ras_ = 1'b1;
|
assign mc_ras_ = 1'b1;
|
assign mc_cke_ = 1'b1;
|
assign mc_cke_ = 1'b1;
|
assign sdram_cs = 1'b1;
|
assign sdram_cs = 1'b1;
|
assign sdram_clk = 1'b1;
|
assign sdram_clk = 1'b1;
|
assign spiClk = 1'b0;
|
assign spiClk = 1'b0;
|
assign spiMasterDataOut = 1'b0;
|
assign spiMasterDataOut = 1'b0;
|
assign spiCS_n = 1'b1;
|
assign spiCS_n = 1'b1;
|
assign usbHostOE_n = 1'b1;
|
assign usbHostOE_n = 1'b1;
|
|
|
pll_48MHz pll_48MHz_inst (
|
pll_48MHz pll_48MHz_inst (
|
.inclk0 ( clk ),
|
.inclk0 ( clk ),
|
.locked( pll_locked)
|
.locked( pll_locked)
|
);
|
);
|
|
|
//generate sync reset from pll lock signal
|
//generate sync reset from pll lock signal
|
always @(posedge clk) begin
|
always @(posedge clk) begin
|
rstReg[1:0] <= {rstReg[0], ~pll_locked};
|
rstReg[1:0] <= {rstReg[0], ~pll_locked};
|
end
|
end
|
assign rst = rstReg[1];
|
assign rst = rstReg[1];
|
|
|
|
|
usbDevice u_usbDevice (
|
usbDevice u_usbDevice (
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
.usbSlaveVP_in(usbSlaveVP_in),
|
.usbSlaveVP_in(usbSlaveVP_in),
|
.usbSlaveVM_in(usbSlaveVM_in),
|
.usbSlaveVM_in(usbSlaveVM_in),
|
.usbSlaveVP_out(usbSlaveVP_out),
|
.usbSlaveVP_out(usbSlaveVP_out),
|
.usbSlaveVM_out(usbSlaveVM_out),
|
.usbSlaveVM_out(usbSlaveVM_out),
|
.usbSlaveOE_n(usbSlaveOE_n),
|
.usbSlaveOE_n(usbSlaveOE_n),
|
.USBFullSpeed(usbSlaveFullSpeed),
|
.USBFullSpeed(usbSlaveFullSpeed),
|
.usbDPlusPullup(usbDPlusPullup),
|
.usbDPlusPullup(usbDPlusPullup),
|
.usbDMinusPullup(usbDMinusPullup),
|
.usbDMinusPullup(usbDMinusPullup),
|
.vBusDetect(vBusDetect)
|
.vBusDetect(vBusDetect)
|
);
|
);
|
|
|
`ifdef PHY_ISP1105
|
`ifdef PHY_ISP1105
|
assign {usbSlaveVP_in, usbSlaveVM_in} = {usbSlaveVP, usbSlaveVM};
|
assign {usbSlaveVP_in, usbSlaveVM_in} = {usbSlaveVP, usbSlaveVM};
|
assign {usbSlaveVP, usbSlaveVM} = (usbSlaveOE_n == 1'b0) ? {usbSlaveVP_out, usbSlaveVM_out} : 2'bzz;
|
assign {usbSlaveVP, usbSlaveVM} = (usbSlaveOE_n == 1'b0) ? {usbSlaveVP_out, usbSlaveVM_out} : 2'bzz;
|
`else
|
`else
|
assign vBusDetect = 1'b1;
|
assign vBusDetect = 1'b1;
|
`endif
|
`endif
|
|
|
`ifdef PHY_ISP1105
|
`ifdef PHY_ISP1105
|
assign SC_P_CLK = 1'b0;
|
assign SC_P_CLK = 1'b0;
|
assign SC_RST_N = 1'b0;
|
assign SC_RST_N = 1'b0;
|
assign SC_CS_N = 1'b0;
|
assign SC_CS_N = 1'b0;
|
assign SC_P0 = 1'b0;
|
assign SC_P0 = 1'b0;
|
assign SC_P1 = 1'b0;
|
assign SC_P1 = 1'b0;
|
assign SC_P2 = 1'b0;
|
assign SC_P2 = 1'b0;
|
assign SC_P3 = 1'b0;
|
assign SC_P3 = 1'b0;
|
assign SC_P4 = 1'b0;
|
assign SC_P4 = 1'b0;
|
assign SC_P5 = 1'b0;
|
assign SC_P5 = 1'b0;
|
assign SC_P6 = 1'b0;
|
assign SC_P6 = 1'b0;
|
assign SC_P7 = 1'b0;
|
assign SC_P7 = 1'b0;
|
assign SC_P8 = 1'b0;
|
assign SC_P8 = 1'b0;
|
assign SC_P9 = 1'b0;
|
assign SC_P9 = 1'b0;
|
assign SC_P10 = 1'b0;
|
assign SC_P10 = 1'b0;
|
assign SC_P11 = 1'b0;
|
assign SC_P11 = 1'b0;
|
assign SC_P12 = 1'b0;
|
assign SC_P12 = 1'b0;
|
assign SC_P13 = 1'b0;
|
assign SC_P13 = 1'b0;
|
assign SC_P14 = 1'b0;
|
assign SC_P14 = 1'b0;
|
assign SC_P15 = 1'b0;
|
assign SC_P15 = 1'b0;
|
assign SC_P16 = 1'b0;
|
assign SC_P16 = 1'b0;
|
assign SC_P17 = 1'b0;
|
assign SC_P17 = 1'b0;
|
assign SC_P18 = 1'b0;
|
assign SC_P18 = 1'b0;
|
assign SC_P19 = 1'b0;
|
assign SC_P19 = 1'b0;
|
assign vBusDetect = SC_P20;
|
assign vBusDetect = SC_P20;
|
assign SC_P21 = 1'b0;
|
assign SC_P21 = 1'b0;
|
assign SC_P22 = usbSlaveVM;
|
assign SC_P22 = usbSlaveVM;
|
assign SC_P23 = usbSlaveVP;
|
assign SC_P23 = usbSlaveVP;
|
assign SC_P24 = usbSlaveOE_n;
|
assign SC_P24 = usbSlaveOE_n;
|
assign SC_P25 = 1'b0;
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assign SC_P25 = 1'b0;
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assign SC_P26 = usbDPlusPullup;
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assign SC_P26 = usbDPlusPullup;
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assign SC_P27 = 1'b0;
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assign SC_P27 = 1'b0;
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assign SC_P28 = usbHostOE_n;
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assign SC_P28 = usbHostOE_n;
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assign SC_P29 = 1'b0;
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assign SC_P29 = 1'b0;
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assign SC_P30 = 1'b0;
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assign SC_P30 = 1'b0;
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assign SC_P31 = 1'b0;
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assign SC_P31 = 1'b0;
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assign SC_P32 = 1'b0;
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assign SC_P32 = 1'b0;
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assign SC_P33 = 1'b0;
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assign SC_P33 = 1'b0;
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assign SC_P34 = 1'b0;
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assign SC_P34 = 1'b0;
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assign SC_P35 = 1'b0;
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assign SC_P35 = 1'b0;
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assign SC_P36 = 1'b0;
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assign SC_P36 = 1'b0;
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assign SC_P37 = 1'b0;
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assign SC_P37 = 1'b0;
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assign SC_P38 = 1'b0;
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assign SC_P38 = 1'b0;
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assign SC_P39 = 1'b0;
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assign SC_P39 = 1'b0;
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`else
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`else
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assign SC_P_CLK = 1'b0;
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assign SC_P_CLK = 1'b0;
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assign SC_RST_N = 1'b0;
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assign SC_RST_N = 1'b0;
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assign SC_CS_N = 1'b0;
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assign SC_CS_N = 1'b0;
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assign SC_P0 = usbSlaveFullSpeed;
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assign SC_P0 = usbSlaveFullSpeed;
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assign SC_P1 = 1'b0;
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assign SC_P1 = 1'b0;
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assign usbSlaveVM_in = SC_P2;
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assign usbSlaveVM_in = SC_P2;
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assign SC_P3 = 1'b0;
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assign SC_P3 = 1'b0;
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assign usbSlaveVP_in = SC_P4;
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assign usbSlaveVP_in = SC_P4;
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assign SC_P5 = 1'b0;
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assign SC_P5 = 1'b0;
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assign SC_P6 = usbSlaveOE_n;
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assign SC_P6 = usbSlaveOE_n;
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assign SC_P7 = 1'b0;
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assign SC_P7 = 1'b0;
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assign SC_P8 = usbSlaveVM_out;
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assign SC_P8 = usbSlaveVM_out;
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assign SC_P9 = 1'b0;
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assign SC_P9 = 1'b0;
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assign SC_P10 = usbSlaveVP_out;
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assign SC_P10 = usbSlaveVP_out;
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assign SC_P11 = 1'b0;
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assign SC_P11 = 1'b0;
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assign SC_P12 = usbDPlusPullup;
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assign SC_P12 = usbDPlusPullup;
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assign SC_P13 = 1'b0;
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assign SC_P13 = 1'b0;
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assign SC_P14 = usbDMinusPullup;
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assign SC_P14 = usbDMinusPullup;
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assign SC_P15 = 1'b0;
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assign SC_P15 = 1'b0;
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assign SC_P16 = 1'b0;
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assign SC_P16 = 1'b0;
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assign SC_P17 = 1'b0;
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assign SC_P17 = 1'b0;
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assign SC_P18 = 1'b0;
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assign SC_P18 = 1'b0;
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assign SC_P19 = 1'b0;
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assign SC_P19 = 1'b0;
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assign SC_P20 = 1'b0;
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assign SC_P20 = 1'b0;
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assign SC_P21 = 1'b0;
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assign SC_P21 = 1'b0;
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assign usbHostVM_in = SC_P22;
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assign usbHostVM_in = SC_P22;
|
assign SC_P23 = 1'b0;
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assign SC_P23 = 1'b0;
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assign usbHostVP_in = SC_P24;
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assign usbHostVP_in = SC_P24;
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assign SC_P25 = usbHostOE_n;
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assign SC_P25 = usbHostOE_n;
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assign SC_P26 = 1'b0;
|
assign SC_P26 = 1'b0;
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assign SC_P27 = 1'b0;
|
assign SC_P27 = 1'b0;
|
assign SC_P28 = 1'b0;
|
assign SC_P28 = 1'b0;
|
assign SC_P29 = 1'b0;
|
assign SC_P29 = 1'b0;
|
assign SC_P30 = 1'b0;
|
assign SC_P30 = 1'b0;
|
assign SC_P31 = 1'b0;
|
assign SC_P31 = 1'b0;
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assign SC_P32 = 1'b0;
|
assign SC_P32 = 1'b0;
|
assign SC_P33 = 1'b0;
|
assign SC_P33 = 1'b0;
|
assign SC_P34 = 1'b0;
|
assign SC_P34 = 1'b0;
|
assign SC_P35 = 1'b0;
|
assign SC_P35 = 1'b0;
|
assign SC_P36 = 1'b0;
|
assign SC_P36 = 1'b0;
|
assign SC_P37 = 1'b0;
|
assign SC_P37 = 1'b0;
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assign SC_P38 = 1'b0;
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assign SC_P38 = 1'b0;
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assign SC_P39 = 1'b0;
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assign SC_P39 = 1'b0;
|
`endif
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`endif
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endmodule
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endmodule
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